Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
This document discusses a study that analyzes the implementation and performance of novel self-timed asynchronous logic circuits called NULL Convention Logic (NCL) that use a Return-To-Zero protocol. The study compares NCL threshold gates to conventional static CMOS gates through transistor-level simulations. The simulations show that NCL gates have lower power consumption and generate less noise than CMOS gates, though NCL gates have slightly increased delay. Overall, the study finds that NCL provides benefits like low power operation, reduced noise, and robustness compared to standard static CMOS logic.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Implementation of Effective Code Converters using Reversible Logic Gates IJERA Editor
The development in the field of nanometer technology leads to minimize the power consumption of logic
circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less
dissipation of heat and low power consumption. In the digital design, the code converters are widely used
process. So, the reversible logic gates and reversible circuits for realizing code converters like as Binary to
Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD codes using reversible logic gates is
proposed. Designing of reversible logic circuit is challenging task, since not enough number of gates are
available for design. Reversible processor design needs its building blocks should be reversible in this view the
designing of reversible code converters became essential one. In the digital domain, data or information is
represented by a combination of 0’s and 1’s. A code is basically the pattern of these 0’s and 1’s used to
represent the data. Code converters are a class of combinational digital circuits that are used to convert one type
of code in to another. The proposed design leads to the reduction of power consumption compared with
conventional logic circuits
Study and Performance Analysis of MOS Technology and Nanocomputing QCAVIT-AP University
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.
Design of magnetic dipole based 3D integration nano-circuits for future elect...VIT-AP University
Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectures have been designed using pNML in MagCAD tool, simulated with modelsim platform and correctness shown by simulation waveform. The correctness of these designs can be verified easily when Verilog code is generated from MagCAD tool. The performance of the proposed comparator towards default parameters shows the area of 2.4336 μm2 and critical path of 1.5E-7 sec. As a higher order, the realization of a 4-to-1 multiplexer in NML has also been included in this work.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
This document describes the design of quaternary logical circuits using voltage mode and current mode logic. It summarizes that quaternary voltage mode logic has 51.78% lower power consumption compared to binary, but requires 3 times more transistors. Quaternary current mode logic has lower area than voltage mode, but higher power consumption. Specifically, it presents the design of quaternary logic gates like inverters, MIN, MAX gates for both modes. Comparative analysis shows voltage mode has lower power while current mode has lower area.
Programmable reversible logic is growing for a potential logic design type
concerning execution around advanced nanotechnology as well as quantum computing
with minimum effect upon circuit temperature production. Current improvements in
reversible logic utilizing additionally quantum computer calculations permit enhanced
computer structure plus arithmetical logic unit layouts. Since reversible circuits
continue to be fairly unique, the most significant study effect is found on the synthesis
of these circuits. Quantum-dot cellular automata (QCA) can be a promising part of
investigating at reversible computing. QCA-based design of the reversible 1-bit full
adder is using the Toffoli and Feynman gates have been achieved in this study. We
develop an improved reversible full adder with overflow detection to enhance
reliability. This component promises to complete the fundamental mathematical
functions of addition, subtraction alongside overflow detection, comparison, along with
logic procedures such as significance. Thus our design is very efficient and versatile
alongside lower quantity of lines as well as quantum cost. This work understands and
nurtures the necessity of reversible full adder for future revolutionary computing
technologies. In this paper, a reversible 1-bit full adder is proposed and compared with
other reversible full adders. Proposed gate performs better than existing methods and
ensures maximum logical operations like the full adder, full with less quantum cost
where other existing gates are not viable.
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
This document discusses a study that analyzes the implementation and performance of novel self-timed asynchronous logic circuits called NULL Convention Logic (NCL) that use a Return-To-Zero protocol. The study compares NCL threshold gates to conventional static CMOS gates through transistor-level simulations. The simulations show that NCL gates have lower power consumption and generate less noise than CMOS gates, though NCL gates have slightly increased delay. Overall, the study finds that NCL provides benefits like low power operation, reduced noise, and robustness compared to standard static CMOS logic.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Implementation of Effective Code Converters using Reversible Logic Gates IJERA Editor
The development in the field of nanometer technology leads to minimize the power consumption of logic
circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less
dissipation of heat and low power consumption. In the digital design, the code converters are widely used
process. So, the reversible logic gates and reversible circuits for realizing code converters like as Binary to
Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD codes using reversible logic gates is
proposed. Designing of reversible logic circuit is challenging task, since not enough number of gates are
available for design. Reversible processor design needs its building blocks should be reversible in this view the
designing of reversible code converters became essential one. In the digital domain, data or information is
represented by a combination of 0’s and 1’s. A code is basically the pattern of these 0’s and 1’s used to
represent the data. Code converters are a class of combinational digital circuits that are used to convert one type
of code in to another. The proposed design leads to the reduction of power consumption compared with
conventional logic circuits
Study and Performance Analysis of MOS Technology and Nanocomputing QCAVIT-AP University
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.
Design of magnetic dipole based 3D integration nano-circuits for future elect...VIT-AP University
Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectures have been designed using pNML in MagCAD tool, simulated with modelsim platform and correctness shown by simulation waveform. The correctness of these designs can be verified easily when Verilog code is generated from MagCAD tool. The performance of the proposed comparator towards default parameters shows the area of 2.4336 μm2 and critical path of 1.5E-7 sec. As a higher order, the realization of a 4-to-1 multiplexer in NML has also been included in this work.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
This document describes the design of quaternary logical circuits using voltage mode and current mode logic. It summarizes that quaternary voltage mode logic has 51.78% lower power consumption compared to binary, but requires 3 times more transistors. Quaternary current mode logic has lower area than voltage mode, but higher power consumption. Specifically, it presents the design of quaternary logic gates like inverters, MIN, MAX gates for both modes. Comparative analysis shows voltage mode has lower power while current mode has lower area.
Programmable reversible logic is growing for a potential logic design type
concerning execution around advanced nanotechnology as well as quantum computing
with minimum effect upon circuit temperature production. Current improvements in
reversible logic utilizing additionally quantum computer calculations permit enhanced
computer structure plus arithmetical logic unit layouts. Since reversible circuits
continue to be fairly unique, the most significant study effect is found on the synthesis
of these circuits. Quantum-dot cellular automata (QCA) can be a promising part of
investigating at reversible computing. QCA-based design of the reversible 1-bit full
adder is using the Toffoli and Feynman gates have been achieved in this study. We
develop an improved reversible full adder with overflow detection to enhance
reliability. This component promises to complete the fundamental mathematical
functions of addition, subtraction alongside overflow detection, comparison, along with
logic procedures such as significance. Thus our design is very efficient and versatile
alongside lower quantity of lines as well as quantum cost. This work understands and
nurtures the necessity of reversible full adder for future revolutionary computing
technologies. In this paper, a reversible 1-bit full adder is proposed and compared with
other reversible full adders. Proposed gate performs better than existing methods and
ensures maximum logical operations like the full adder, full with less quantum cost
where other existing gates are not viable.
This document presents a new mesh analytical method for symbolic simulation of linear RLC circuits in the frequency domain. The method formulates the circuit equations as a set of mesh equations that account for both the steady-state impedances of the circuit elements as well as the initialization effects of non-zero initial conditions in the capacitors and inductors. It derives the mesh equations for a simple three-node, three-mesh example circuit and shows that the circuit equations can be expressed in matrix form with impedance matrices representing the steady-state and initialization impedances. The method aims to provide a simple yet robust way to simulate transient responses of linear circuits symbolically in the frequency domain.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Report-Implementation of Quantum Gates using VerilogShashank Kumar
It was a project-based work in which I was guided to implement the quantum-based gates which would be equivalent to classical gates So, the project name was "FPGA Implementation of Digital Logic Design using Quantum Computing". Actually, it is to mitigate the problem, since in quantum any NAND based circuit is not shown universal as in the classical it was so tried by using the "IBM Quantum Composer" to make such circuit which would behave as the NAND gate and also reversible in nature as per the quantum physics says and simulated the circuitry using the "Verilog".
Design of Binary to BCD Code Converter using Area Optimized Quantum Dot Cellu...CSCJournals
The Integrated Circuit Technology (IC) is growing day to day to improve circuit performance and density for compact systems. A novel technology, Quantum dot Cellular Automata (QCA) was introduced to overcome the scaling limitations of CMOS technology. In order to bring a new paradigm of IC design in an efficient and optimized manner, a binary to BCD code converter is designed using QCA technology based area optimized adder. It is observed that the proposed binary to BCD code converter design gives better results in terms of the area and number of QCA cells. The results obtained by the proposed design shows that 61% of area reduced compared to boolean expression based design, this design is further optimized to reduce the QCA cell count by 45% with respect to the design in [1].
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of quantum gates using verilogShashank Kumar
Implementing the XOR, AND, OR gate in the quantum circuits and with the help of IBM Quantum Composer which is a graphical programming tool. Also utilizing the Quantum circuit as well as HDL i.e., Verilog by Xilinx ISE Design Suite version 14.7 for visualizing the simulation graph with implementing the XOR, AND, OR and NAND gates also actually NAND gate is not found the universal gate in quantum, so trying to build the NAND gate which can also perform the reversible nature with simulating using the Verilog code for the desired result i.e. NAND output.
An Area Efficient and High Speed Reversible Multiplier Using NS GateIJERA Editor
In digital computer system a major problem has been found that the Power dissipation which leads to bring some research on the methods to decrease this Area efficient, high speed. This is the main cause to give birth to reversible computing systems for digital computers and designs. Reversible computing is the path to future computing technologies, which all happen to use reversible logic. In addition, reversible computing will become mandatory because of the necessity to decrease power consumption. Reversible logic circuits have the same number of inputs and outputs, and have one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states. Consequently, a computation is reversible, if it is always possible to uniquely recover the input, given the output. Each gate can be made reversible by adding some additional input and output wires if necessary. The main aim of this reversible computing is to lower the power dissipation, area efficient and high speed and some other advantages like security of data and prevention of errors etc... Reversible logic has so many applications low power CMOS, nanotechnology, DNA computing and quantum computing. There are two primary design implementations in this study which are the major spotlights. The first one is reversible design gate and the second one is multiplier design using reversible gates. In this manuscript we have implemented a 8 * 8 reversible design called “NSG(Non linear Sign Flip)”. The total project is implemented in Xilinx 14.7 ISE with Spartan 3E family.
The document discusses the design of a new fault-tolerant scheme for quantum-dot cellular automata (QCA) logic circuits. It introduces a 2x2 array of four rotated quantum dot cells, called a complementary tile (CT), that can achieve 100% fault tolerance against single cell defects. A new majority voter logic gate called the reliable majority voter (RMV) is designed using the CT that outperforms existing QCA majority gates in terms of reliability. The document analyzes the polarization and functional characteristics of the RMV under different types of cell defects. It also develops an error probability model to quantify the reliability of the proposed RMV design.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
This document summarizes a research paper that proposes a power gating structure using sleep transistors to reduce subthreshold leakage in a reversible programmable logic array (RPLA). It begins by introducing the concept of reversible logic for reducing power dissipation at the gate level. However, physical implementation with CMOS technology still leads to leakage during inactive periods. The paper then discusses power gating and sleep transistors as a technique to reduce leakage. It proposes a design for an RPLA using reversible AND and OR arrays with sleep transistors in a footer configuration to switch between active and sleep modes. Simulation results show 40.8% energy savings compared to a conventional CMOS design.
This document describes an FPGA-based address generator for the deinterleaver used in WiMAX systems. It proposes algorithms to generate addresses for the deinterleaver that support different modulation schemes like QPSK, 16-QAM, and 64-QAM without using a floor function. The algorithms are implemented using VHDL on a Xilinx FPGA. Simulation results show the address generation for different modulation types matches the output of a MATLAB program. The FPGA implementation provides better performance and resource utilization than a conventional LUT-based approach.
Fpga based low power and high performance address generator for wimax deinter...eSAT Journals
Abstract
The main aim of this project is to generate the address generation circuitry of Deinterleaver used in the WiMAX transreceiver using
the Xilinx Field Programmable Gate Array(FPGA). The floor function associated with the implementation of FPGA is very difficult in
IEEE 802.16e standard. So we eliminate the requirement of floor function by using a simple mathematical algorithm. Some
modulations like QPSK, 16-QAM and 64-QAM along with its code rates make our approach to be novel and high efficient.
Keywords— Modulation circuits, Deinterleaver/Interleaver circuit, Wireless SYSTEMS
Area-Delay Efficient Binary Adders in QCAIJERA Editor
In this paper, a novel quantum-dot cellular automata (QCA) adder design is presented that decrease the number
of QCA cells compared to previously method designs. The proposed one-bit QCA adder is based on a new
algorithm that requires only three majority gates and two inverters for the QCA addition. A novel 128-bit adder
designed in QCA was implemented. It achieved speed performances higher than all the existing. QCA adders,
with an area requirement comparable with the low RCA and CFA established. The novel adder operates in the
RCA functional, but it could propagate a carry signal through a number of cascaded MGs significantly lower
than conventional RCA adders. In adding together, because of the adopted basic logic and layout strategy, the
number of clock cycles required for completing the explanation was limited. As transistors reduce in size more
and more of them can be accommodated in a single die, thus increasing chip computational capabilities.
However, transistors cannot find much smaller than their current size. The quantum-dot cellular automata
approach represents one of the possible solutions in overcome this physical limit, even though the design of
logic modules in QCA is not forever straightforward.
The CMOS faces challenges related to the increment in leakage-current to power-consumption. QCA is a promising alternative to overcome these challenges successfully. On the other hand, reversible logic plays a significant role in quantum-computing. Keeping this technique in mind, a conservative-reversible flip flops and counter are explored here which will bring QCA and reversible computing together in a singleplatform. In synthesizing, a reversible-conservative-quantum-cellular-automata (R-CQCA) is proposed. The proposed D, T, JK and dual-edge master-slave flip-flops advocate an improvement of 20%, 46.6%,
50%, and 36.66% respectively than its counterpart in quantum-cost. Further, the 100% fault-coverage
by stuck-fault is framed in R-CQCA, which can be useful for a tester to maintain data-integrity. Also, the R-CQCA layout is implemented in QCA, which achieve some parameters such as cell-complexity of 177, leakage-energy-dissipation of 0.1055 eV, and size of 0.24 mm2. Moreover, R-CQCA is better than FRG, RM, PPRG and MX-cqca regarding QCA-primitives are reported here.
Implementation of the Binary Multiplier on CPLD Using Reversible Logic GatesIOSRJECE
The document discusses the implementation of a binary multiplier on a CPLD using reversible logic gates. It begins by introducing reversible logic gates and describes common reversible gates like the Toffoli gate. It then proposes a novel 4x4 reversible gate called the TSG gate. The document outlines the design of a reversible binary multiplier architecture using these reversible gates. Specifically, it describes generating partial products in parallel using Fredkin gates and then merging them using reversible adders. Simulation results showing the design of a 4x4 bit reversible multiplier are also presented. In conclusion, the document discusses how this CPLD implementation of a reversible binary multiplier using novel TSG gates lays the foundation for more complex reversible systems with applications in quantum computing.
DESIGNING AN EFFICIENT APPROACH FOR JK AND T FLIP-FLOP WITH POWER DISSIPATION...VLSICS Design
QCA (Quantum Dot Cellular Automata) is an emerging and pioneer technology, which is a paradigm for
computing with interacting quantum dots. Many eminent researchers have well thought of eloquent work in
the existing areas of the sequential circuit. However, this paper proclaims three new approaches to design
JK and T flip-flop. Since flip-flops and memory design are the crucial building blocks of digital circuits,
therefore we concern the underlying principle of fundamental design of JK and T flip-flop and then work
out to model the new structure favorable with the forthcoming excellence required. This new concept
places elsewhere the need of using feedback path in flip flop design. Also two algorithms have been shown
for explanatory purpose. The proposed structure is able to establish the validity and genuineness than
earlier design. By using the proposed T flip-flop, a 2-bit and 3-bit counter is also designed in the paper.
The simulation result of the proposed design proves their vigorousness and correctness in the output.
Optimizing Data Encoding Technique For Dynamic Power Reduction In Network On ...IRJET Journal
This document summarizes a research paper that proposes three data encoding schemes to reduce dynamic power consumption in Network-on-Chip (NoC) systems. The schemes aim to minimize bit transitions on the data path by considering different transition types like odd, even and full. The schemes are evaluated by replacing the encoder in Low Density Parity Check (LDPC) coding with the proposed schemes. Simulation results show the three schemes reduce dynamic power compared to normal LDPC. Scheme 3 provides the most reduction by integrating even and odd inversion to minimize transitions between categories. The proposed techniques yield meaningful power savings for dynamic power reduction in NoCs.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, delay. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical. The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flip-flop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flip-flops and parts of their logic cones with PNAND cells is described. The resulting hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation. Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy delay product compared to conventional FPGA using well known FPGA modeling tool called VPR. Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flip-flops is described.
Review On 2:4 Decoder By Reversible Logic Gates For Low Power ConsumptionIRJET Journal
This document summarizes a research paper that proposes designing a 2:4 decoder using reversible logic gates to reduce power consumption. Reversible logic gates use minimal power by only employing buffers instead of traditional CMOS gates. The document provides background on reversible gates and decoders, reviews previous work on low-power decoder designs, and proposes a reversible gate-based 2:4 decoder design to reduce overall system power consumption compared to a standard CMOS implementation. Simulation results from other studies show reversible gate designs can achieve up to 26% power reduction for instruction decoding. The proposed design aims to lower delay and gate count while minimizing power.
Cost-effective architecture of decoder circuits and futuristic scope in the e...VIT-AP University
The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.
Regular clocking scheme based design of cost-efficient comparator in QCAnooriasukmaningtyas
Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.
This document presents a new mesh analytical method for symbolic simulation of linear RLC circuits in the frequency domain. The method formulates the circuit equations as a set of mesh equations that account for both the steady-state impedances of the circuit elements as well as the initialization effects of non-zero initial conditions in the capacitors and inductors. It derives the mesh equations for a simple three-node, three-mesh example circuit and shows that the circuit equations can be expressed in matrix form with impedance matrices representing the steady-state and initialization impedances. The method aims to provide a simple yet robust way to simulate transient responses of linear circuits symbolically in the frequency domain.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Report-Implementation of Quantum Gates using VerilogShashank Kumar
It was a project-based work in which I was guided to implement the quantum-based gates which would be equivalent to classical gates So, the project name was "FPGA Implementation of Digital Logic Design using Quantum Computing". Actually, it is to mitigate the problem, since in quantum any NAND based circuit is not shown universal as in the classical it was so tried by using the "IBM Quantum Composer" to make such circuit which would behave as the NAND gate and also reversible in nature as per the quantum physics says and simulated the circuitry using the "Verilog".
Design of Binary to BCD Code Converter using Area Optimized Quantum Dot Cellu...CSCJournals
The Integrated Circuit Technology (IC) is growing day to day to improve circuit performance and density for compact systems. A novel technology, Quantum dot Cellular Automata (QCA) was introduced to overcome the scaling limitations of CMOS technology. In order to bring a new paradigm of IC design in an efficient and optimized manner, a binary to BCD code converter is designed using QCA technology based area optimized adder. It is observed that the proposed binary to BCD code converter design gives better results in terms of the area and number of QCA cells. The results obtained by the proposed design shows that 61% of area reduced compared to boolean expression based design, this design is further optimized to reduce the QCA cell count by 45% with respect to the design in [1].
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of quantum gates using verilogShashank Kumar
Implementing the XOR, AND, OR gate in the quantum circuits and with the help of IBM Quantum Composer which is a graphical programming tool. Also utilizing the Quantum circuit as well as HDL i.e., Verilog by Xilinx ISE Design Suite version 14.7 for visualizing the simulation graph with implementing the XOR, AND, OR and NAND gates also actually NAND gate is not found the universal gate in quantum, so trying to build the NAND gate which can also perform the reversible nature with simulating using the Verilog code for the desired result i.e. NAND output.
An Area Efficient and High Speed Reversible Multiplier Using NS GateIJERA Editor
In digital computer system a major problem has been found that the Power dissipation which leads to bring some research on the methods to decrease this Area efficient, high speed. This is the main cause to give birth to reversible computing systems for digital computers and designs. Reversible computing is the path to future computing technologies, which all happen to use reversible logic. In addition, reversible computing will become mandatory because of the necessity to decrease power consumption. Reversible logic circuits have the same number of inputs and outputs, and have one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states. Consequently, a computation is reversible, if it is always possible to uniquely recover the input, given the output. Each gate can be made reversible by adding some additional input and output wires if necessary. The main aim of this reversible computing is to lower the power dissipation, area efficient and high speed and some other advantages like security of data and prevention of errors etc... Reversible logic has so many applications low power CMOS, nanotechnology, DNA computing and quantum computing. There are two primary design implementations in this study which are the major spotlights. The first one is reversible design gate and the second one is multiplier design using reversible gates. In this manuscript we have implemented a 8 * 8 reversible design called “NSG(Non linear Sign Flip)”. The total project is implemented in Xilinx 14.7 ISE with Spartan 3E family.
The document discusses the design of a new fault-tolerant scheme for quantum-dot cellular automata (QCA) logic circuits. It introduces a 2x2 array of four rotated quantum dot cells, called a complementary tile (CT), that can achieve 100% fault tolerance against single cell defects. A new majority voter logic gate called the reliable majority voter (RMV) is designed using the CT that outperforms existing QCA majority gates in terms of reliability. The document analyzes the polarization and functional characteristics of the RMV under different types of cell defects. It also develops an error probability model to quantify the reliability of the proposed RMV design.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
This document summarizes a research paper that proposes a power gating structure using sleep transistors to reduce subthreshold leakage in a reversible programmable logic array (RPLA). It begins by introducing the concept of reversible logic for reducing power dissipation at the gate level. However, physical implementation with CMOS technology still leads to leakage during inactive periods. The paper then discusses power gating and sleep transistors as a technique to reduce leakage. It proposes a design for an RPLA using reversible AND and OR arrays with sleep transistors in a footer configuration to switch between active and sleep modes. Simulation results show 40.8% energy savings compared to a conventional CMOS design.
This document describes an FPGA-based address generator for the deinterleaver used in WiMAX systems. It proposes algorithms to generate addresses for the deinterleaver that support different modulation schemes like QPSK, 16-QAM, and 64-QAM without using a floor function. The algorithms are implemented using VHDL on a Xilinx FPGA. Simulation results show the address generation for different modulation types matches the output of a MATLAB program. The FPGA implementation provides better performance and resource utilization than a conventional LUT-based approach.
Fpga based low power and high performance address generator for wimax deinter...eSAT Journals
Abstract
The main aim of this project is to generate the address generation circuitry of Deinterleaver used in the WiMAX transreceiver using
the Xilinx Field Programmable Gate Array(FPGA). The floor function associated with the implementation of FPGA is very difficult in
IEEE 802.16e standard. So we eliminate the requirement of floor function by using a simple mathematical algorithm. Some
modulations like QPSK, 16-QAM and 64-QAM along with its code rates make our approach to be novel and high efficient.
Keywords— Modulation circuits, Deinterleaver/Interleaver circuit, Wireless SYSTEMS
Area-Delay Efficient Binary Adders in QCAIJERA Editor
In this paper, a novel quantum-dot cellular automata (QCA) adder design is presented that decrease the number
of QCA cells compared to previously method designs. The proposed one-bit QCA adder is based on a new
algorithm that requires only three majority gates and two inverters for the QCA addition. A novel 128-bit adder
designed in QCA was implemented. It achieved speed performances higher than all the existing. QCA adders,
with an area requirement comparable with the low RCA and CFA established. The novel adder operates in the
RCA functional, but it could propagate a carry signal through a number of cascaded MGs significantly lower
than conventional RCA adders. In adding together, because of the adopted basic logic and layout strategy, the
number of clock cycles required for completing the explanation was limited. As transistors reduce in size more
and more of them can be accommodated in a single die, thus increasing chip computational capabilities.
However, transistors cannot find much smaller than their current size. The quantum-dot cellular automata
approach represents one of the possible solutions in overcome this physical limit, even though the design of
logic modules in QCA is not forever straightforward.
The CMOS faces challenges related to the increment in leakage-current to power-consumption. QCA is a promising alternative to overcome these challenges successfully. On the other hand, reversible logic plays a significant role in quantum-computing. Keeping this technique in mind, a conservative-reversible flip flops and counter are explored here which will bring QCA and reversible computing together in a singleplatform. In synthesizing, a reversible-conservative-quantum-cellular-automata (R-CQCA) is proposed. The proposed D, T, JK and dual-edge master-slave flip-flops advocate an improvement of 20%, 46.6%,
50%, and 36.66% respectively than its counterpart in quantum-cost. Further, the 100% fault-coverage
by stuck-fault is framed in R-CQCA, which can be useful for a tester to maintain data-integrity. Also, the R-CQCA layout is implemented in QCA, which achieve some parameters such as cell-complexity of 177, leakage-energy-dissipation of 0.1055 eV, and size of 0.24 mm2. Moreover, R-CQCA is better than FRG, RM, PPRG and MX-cqca regarding QCA-primitives are reported here.
Implementation of the Binary Multiplier on CPLD Using Reversible Logic GatesIOSRJECE
The document discusses the implementation of a binary multiplier on a CPLD using reversible logic gates. It begins by introducing reversible logic gates and describes common reversible gates like the Toffoli gate. It then proposes a novel 4x4 reversible gate called the TSG gate. The document outlines the design of a reversible binary multiplier architecture using these reversible gates. Specifically, it describes generating partial products in parallel using Fredkin gates and then merging them using reversible adders. Simulation results showing the design of a 4x4 bit reversible multiplier are also presented. In conclusion, the document discusses how this CPLD implementation of a reversible binary multiplier using novel TSG gates lays the foundation for more complex reversible systems with applications in quantum computing.
DESIGNING AN EFFICIENT APPROACH FOR JK AND T FLIP-FLOP WITH POWER DISSIPATION...VLSICS Design
QCA (Quantum Dot Cellular Automata) is an emerging and pioneer technology, which is a paradigm for
computing with interacting quantum dots. Many eminent researchers have well thought of eloquent work in
the existing areas of the sequential circuit. However, this paper proclaims three new approaches to design
JK and T flip-flop. Since flip-flops and memory design are the crucial building blocks of digital circuits,
therefore we concern the underlying principle of fundamental design of JK and T flip-flop and then work
out to model the new structure favorable with the forthcoming excellence required. This new concept
places elsewhere the need of using feedback path in flip flop design. Also two algorithms have been shown
for explanatory purpose. The proposed structure is able to establish the validity and genuineness than
earlier design. By using the proposed T flip-flop, a 2-bit and 3-bit counter is also designed in the paper.
The simulation result of the proposed design proves their vigorousness and correctness in the output.
Optimizing Data Encoding Technique For Dynamic Power Reduction In Network On ...IRJET Journal
This document summarizes a research paper that proposes three data encoding schemes to reduce dynamic power consumption in Network-on-Chip (NoC) systems. The schemes aim to minimize bit transitions on the data path by considering different transition types like odd, even and full. The schemes are evaluated by replacing the encoder in Low Density Parity Check (LDPC) coding with the proposed schemes. Simulation results show the three schemes reduce dynamic power compared to normal LDPC. Scheme 3 provides the most reduction by integrating even and odd inversion to minimize transitions between categories. The proposed techniques yield meaningful power savings for dynamic power reduction in NoCs.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, delay. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical. The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flip-flop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flip-flops and parts of their logic cones with PNAND cells is described. The resulting hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation. Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy delay product compared to conventional FPGA using well known FPGA modeling tool called VPR. Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flip-flops is described.
Review On 2:4 Decoder By Reversible Logic Gates For Low Power ConsumptionIRJET Journal
This document summarizes a research paper that proposes designing a 2:4 decoder using reversible logic gates to reduce power consumption. Reversible logic gates use minimal power by only employing buffers instead of traditional CMOS gates. The document provides background on reversible gates and decoders, reviews previous work on low-power decoder designs, and proposes a reversible gate-based 2:4 decoder design to reduce overall system power consumption compared to a standard CMOS implementation. Simulation results from other studies show reversible gate designs can achieve up to 26% power reduction for instruction decoding. The proposed design aims to lower delay and gate count while minimizing power.
Cost-effective architecture of decoder circuits and futuristic scope in the e...VIT-AP University
The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.
Regular clocking scheme based design of cost-efficient comparator in QCAnooriasukmaningtyas
Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
Implementation of Non-restoring Reversible Divider Using a Quantum-Dot Cellul...VIT-AP University
The document describes the design and implementation of a non-restoring reversible divider circuit using quantum-dot cellular automata (QCA). Key points:
1) A non-restoring divider circuit was designed using Feynman and Haghparast gates in a reversible logic approach to minimize quantum cost and garbage outputs.
2) The divider circuit was synthesized and implemented in QCADesigner, achieving a cell complexity of 269 and area of 0.54 μm2.
3) The proposed reversible divider design was shown to have lower quantum cost, fewer garbage outputs, and gates than previous non-reversible divider designs.
Presentation of a fault tolerance algorithm for design of quantum-dot cellul...IJECEIAES
A novel algorithm for working out the Kink energy of quantum-dot cellular automata (QCA) circuits and their fault tolerability is introduced. In this algorithm at first with determining the input values on a specified design, the calculation between cells makes use of Kink physical relations will be managed. Therefore, the polarization of any cell and consequently output cell will be set. Then by determining missed cell(s) on the discussed circuit, the polarization of output cell will be obtained and by comparing it with safe state or software simulation, its fault tolerability will be proved. The proposed algorithm was implemented on a novel and advance fault tolerance full adder whose performance has been demonstrated. This algorithm could be implemented on any QCA circuit. Noticeably higher speed of the algorithm than simulation and traditional manual methods, expandability of this algorithm for variable circuits, beyond of four-dot square of QCA circuits, and the investigation of several damaged cells instead just one and special cell are the advantages of algorithmic action.
A modular approach for testable conservative reversible multiplexer circuit f...VIT-AP University
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with
prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm,
which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing
framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative
reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters
in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count,
quantum cost and unit delay are optimal.
Efficient architecture for arithmetic designs using perpendicular NanoMagneti...VIT-AP University
As the process of scaling down continues at a rapid pace, there is a growing need for an alternative semiconductor device to replace CMOS. One of the alternatives that attracted a lot of attention is called nanomagnetic logic (NML). This is because NML delivers a high device density in addition to a non-volatility of stored information, beyond-CMOS technologies, and device work at room temperature. It is necessary to lower the circuit density and increase the speed of circuits like adders. Using emerging NML logic, we created a full-adder, and ripple carry adder (RCA) with a minimum area. As a result, the invented multilayer-based decimal design makes use of RCA, and full-adder, for innovative 3D topology. We used an NML framework built with perpendicular nanomagnetic (pNML) layers to simulate the characteristics of these devices. With the adder designs that have been offered the latency values are relatively low while performing exhaustive testing. Using pNML technology, a decimal adder has been constructed for the first time in the literature. In addition, simulations are carried out with the help of the Modelsim simulator. During the process of nanomagnetic designing consideration is given to both of these aspects as latency and area. To create an NML circuit, the tool MagCAD is employed. Results are better using the pNML environment-based full adder, RCA and decimal adder.
Abstract: A technology called Quantum Dot Cellular Automata (QCA) offers a far more effective computational
platform than CMOS. Through the polarization of electrons, digital information is represented. In comparison to
CMOS technology, it is more attractive because to its size, faster speed, feature, high degree of scalability, greater
switching frequency, and low power consumption. This paper suggests structures of basic logic gates in the QCA
technology. For the aim of verification, the produced circuits aresimulated, and their results are then compared
to those of their published counterparts. The comparison outcomes provide hope for adding the suggested
structures to the collection of QCA gates.
Novel conservative reversible error control circuits based on molecular QCAVIT-AP University
Quantum-dot cellular automata are a prominent part of the nanoscale regime. They
use a quantum cellular based architecture which enables rapid information process with high
device density. This paper targets the two kinds of novel error control circuits such as Hamming
code, parity generator and checker. To design the HG-PP (HG = Hamming gate, PP = parity
preserving), NG-PP (NG = new gate) are proposed for optimising the circuits. Based on the
proposed gates and a few existing gates, the Hamming code and parity generator and checker
circuits are constructed. The proposed gates have been framed and verified in QCA. The
simulation outcomes signify that their framed circuits are faultless. In addition to verification,
physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit
delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.
IRJET- A Novel Design of Flip Flop and its Application in Up CounterIRJET Journal
1) The document proposes a novel design of flip flops and a 4-bit up counter using Quantum-Dot Cellular Automata (QCA) technology. QCA is an emerging nanotechnology that could overcome scaling limitations of CMOS.
2) In QCA, logic states are represented by the position of electrons in quantum dots rather than voltage as in CMOS. Basic logic gates like inverters and majority gates are constructed using QCA cells.
3) The document designs various flip flops like SR, JK, D, and T flip flops in QCA and uses them to build a 4-bit up counter. Power consumption is shown to be lower for the QCA designs compared to
Design of Quantum Dot Cellular Automata Based Parity Generator and Checker wi...VIT-AP University
Quantum-dot Cellular Automata is an alternative to CMOS technology for the future digital designs. When compared to its CMOS counterpart, it has extremely low power consumption, as there is no current flow in cell. The methodology of parity generator and checker is based on the parity generation and matched it at the receiver end. By using the parity match bits, the error in circuit can be sensed. In this paper, novel parity generator and detector circuit are introduced. The circuit is designed in single layer, minimum clock and minimum latency, which is achieved in QCA framework. The proposed circuits are better than the existing in terms of clock cycle delay, cell complexity and clock cycle utilize. The simulation of presented cell structures have been verified using QCA designer tool. In addition, QCA Probabilistic (QCAPro) tool is used to calculate the minimum, maximum and average energy dissipation aspect in proposed QCA circuit. Appropriate comparison table and power analysis is shown to prove that our proposed circuit is cost effective.
Analysis on Fault Mapping of Reversible Gates with Extended Hardware Descript...VIT-AP University
Quantum-dot cellular automata is a modern computing paradigm, conceived in feature of nanometer
scale with high integration density, and significant low power. For the QCA technology, making these
high-density design means an increase in the complexity which in turn leads to growth in the number of faults. The defect model presented in this paper categorized into two types, which include single missing and additional cell considering for QCA fault. Proposed gates have been designed in the
QCA and verified. The proposed Fredkin gate design has been compared with an existing design,
and 43% and 70% improvement in cell count and area respectively are revealed. Also, the Toffoli
design in QCA which achieve some parameters such as cell complexity of 39, and the average fault tolerance of 53.5%. The polarization value for both single cells missing an addition cell missing has been studied to explain the logic signal strength effect physically. A QCA framework for the 3-input
Ex-OR, 2:1 multiplexer, Fredkin, and Toffoli gate for the fault problem in which reliability analysis based on Hardware description language for QCA devices (HDLQ) is discussed and verified on the fault pattern look-up table.
A parity generator is a circuit that generates redundant bits used for error detection
and is used when transmitting binary information. Previous parity generator circuits
based on quantum-dot cellular automata (QCA) are designed to reduce the area of the
circuit. Input cells of existing circuit are designed inside the circuit and the circuit’s
signal is not propagated properly due to the influence between adjacent wires. In
addition, existing circuits consume many clocks because the XOR gate, which is an
essential component of the parity generator circuit, consumes many clocks. In order to
solve this problem, we design a 3-bit odd parity generator circuit using QCA for fast
operation. The proposed circuit uses an XOR gate that can operate one clock faster
than the existing XOR gate to reduce the clock, and by extending this XOR gate, the
output value can be obtained faster than the conventional circuit. In the proposed
circuit, the result is verified through simulation and the performance is compared with
the existing circuit
Two Bit Arithmetic Logic Unit (ALU) in QCAidescitation
Quantum cellular automata (QCA) is a new
technology in nanometre scale (<18nm) to support nano
technology. QCA is very effective in terms of high space density
and power dissipation and will be playing a major role in the
development of the Quantum computer with low power
consumption and high speed. This paper describes the design
and layout of a 2-bit ALU based on quantum-dot cellular
automata (QCA) using the QCADesigner design tool. The
ALU design is based on combinational circuits which reduces
the required hard-ware complexity and allows for reasonable
simulation times. The paper aims to provide evidence that
QCA has potential applications in future Quantum computers,
provided that the underlying technology is made feasible.
Design has been made using certain combinational circuits
by using Majority gate, AND, OR, NOT, X-OR in QCA. 2 bit
ALU needs the design of Logical Extender, Arithmetic
Extender and the Full adder circuits using QCA. The QCA is
a novel tool to realize Nano level digital devices and study and
analyze their various parameters.
A Novel and Efficient Design for Squaring Units by Quantum-Dot Cellular AutomataVIT-AP University
Quantum cell automata (QCA) are the best possible alternative to the
conventional CMOS technology due to its low power consumption, less area and high-speed operation. This paper describes synthesizable QCA implementation of squaring. Vedic sutras used for squaring are defined over algorithm construction. Based on the concept of the Vedic sutra, this paper has carried out 2-bit square and
4-bit square, projective to affine logic gates construction. Importantly for miniaturization
of devices, the QCA based square is the operation on which the area of
circuits relies on. This means that significantly lower QCA parameters can be used in
the square than in other competitive square circuits such as Wallace, Dadda, serial parallel,
and Baugh-Wooley.
Adiabatic technique based low power synchronous counter designIJECEIAES
The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.
Designing of an Energy-Efficient Nanoelectronics Architecture for Binary Comp...VIT-AP University
Quantum-dot cellular automata is a nanoscale computation circuit design approach which computes bits via charges
among quantum-dot in the quantum cell of QCA. This technology has promises the feature of energy efficient and high
density in the era of high-speed nanotechnology. This article contributes a new nanoscale design of binary comparator
with less latency, area, and clock utilized. The proposed comparator architecture is robust and enjoys wire crossing
without any crossover, which needs only normal and rotated cells. All the simulation results and calculated parameters
are based on the QCADesigner tool. QCAPro tool based approach has been used to perform the energy dissipation
estimation of the new comparator architecture. A better primitives results as compared to state-of-art technology has
been achieved and good contribution in this area.
DESIGN OF MEDIAN FILTER IN QUANTUM-DOT CELLULAR AUTOMATA FOR IMAGE PROCESSING...VIT-AP University
This document summarizes a research paper that proposes a new design for a median filter using quantum-dot cellular automata (QCA). It uses a majority logic algorithm and one-hot encoding. For an input matrix of 9 numbers represented as 4-bit values, each column is processed independently by majority gates to determine the median value in 0.5 clock cycles. The proposed architecture scales to larger bit sizes while maintaining a constant delay of 0.5 clock cycles. Simulation results show the 1-bit median filter design occupies 0.05 μm2 and the proposed approach achieves better speed performance compared to other parameters as the bit size increases.
Investigating the Performance of NoC Using Hierarchical Routing ApproachIJERA Editor
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The impact of quantum computing has been widely recognised in the engineering domain. The age of quantum computing has arrived, and with it comes the ability to easily solve exponential problems. This book is written by me to meet current academic demands. The book is designed to address the most important aspects of the subject of Quantum Computing. The publication of the book "Quantum Computing" is the culmination of numerous years of research and teaching in academia. It is given in a way that is straightforward to comprehend. The undergraduates, and graduate students may all benefit from reading this book. We have given our very best effort to bring you accurate book material.
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A novel vedic divider based crypto-hardware for nanocomputing paradigm: An extended perspective
1. Int. J. Nano Dimens., 9 (4): 336-345, Autumn 2018
ORIGINAL ARTICLE
A novel vedic divider based crypto-hardware for nanocomputing
paradigm: An extended perspective
Bandan Kumar Bhoi 1
, Neeraj Kumar Misra 2,
*, Manoranjan Pradhan 1
1
Department of Electronics and Telecommunication, Veer Surendra Sai University of Technology, India
2
Bepartment of Electronics and Communication Engineering, Bharat Institute of Engineering and
Technology, Hyderabad, India
Received 12 March 2018; revised 11 May 2018; accepted 21 May 2018; available online 23 May 2018
* Corresponding Author Email: neeraj.misra@ietlucknow.ac.in
How to cite this article
Bhoi BK, Misra NK, Pradhan M. A novel vedic divider based crypto-hardware for nanocomputing paradigm: An extended
perspective. Int. J. Nano Dimens., 2018; 9 (4): 336-345.
Abstract
Restoring and non-restoring divider has become widely applicability in the era of digital computing
application due to its computation speed. In this paper, we have proposed the design of divider of different
architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the
replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight
embedded devices and the results obtained for this architecture by the analysis using the QCADesigner
tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
Keywords: Cryptography; Divider; Quantum Dot Cellular Automata; Symmetric Key; Vedic Sutra.
This work is licensed under the Creative Commons Attribution 4.0 International License.
To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.
INTRODUCTION
Advances to the integrated circuit in recent
sub-micron is more difficult due to the point of
miniaturization can present many challenges.
Quantum-dot automata (QCA) technology focus
on tackling the problem of short channel effect
and device density. QCA design provides a more
robust, fast computation to the MOS transistor
technology and gives a solution at the nanoscale
but also offers a new method for computation and
information transmission [1-4]. QCA circuits have
the major advantage of low power dissipation,
lightweight and faster speed of operation. QCA
based cryptographic circuits are suitable for
lightweight and energy efficient security solutions
for mobile and pervasive computing devices. Side
Channel Analysis (SCA) attacks based on power
analysis have become a significant threat to CMOS
based cryptographic circuits [5, 6]. This can be
minimized by using QCA based cryptographic
circuits because there is no current flow in QCA
circuits.
In this work, we develop an extended
perspective based divider for the application of
crypto-hardware. In this approach, the novel
divider is the Vedic framework adopted to
optimize the latency in each replica. We have also
implemented nanocomputing framework for the
physical realization of crypto-hardware.
The rest of the paper is organized as follows: in
section 2, we provide a brief background regarding
QCA technology. In section 3, we develop the
divider architecture. In section 4, the QCA
implementation of the proposed crypto hardware
is described. Section 5 deals with the result and
power consumption analysis of the proposed
designs with the earlier designs. The conclusion is
presented in section 6.
2. 337Int. J. Nano Dimens., 9 (4): 336-345, Autumn 2018
M. K. Hassanzadeh and S. A. Edalatpanah
RELATED WORK
Several studies have reported the design of many
cryptography circuits using QCA [7-12]. The work
in [7-10] primarily focuses on the Serpent block
cipher. A clocked logic is introduced for QCA based
cryptographic processors in [11]. Cryptography
is broadly classified into two main types. These
are symmetric key encryption technique and
asymmetric key encryption technique. The
authors in [12] have designed a asymmetric key
crypto hardware using QCA. To the best of our
knowledge, there are no prior works on QCA based
symmetric key crypto-hardware with encryption
and decryption blocks. Symmetric key cryptography
is faster than the Asymmetric cryptography, often
by 100 to 1000 times and requirement of storage
memory is less as compared to the Asymmetric
Key Cryptography [13]. This paper presents a
design of symmetric key encryption algorithm
using the division algorithm in QCA. However, to
date, only two implementations of divider circuits
using QCA have been proposed [14, 15], and
these are based on restoring and non-restoring
division methods. Because of the importance of
dividers as an essential arithmetic operation in
many computational and processor circuits. In this
paper investigates the implementation of a novel
QCA divider is proposed. This algorithm describes
a simple procedure for carrying out the division
using simple multiplications and subtractions.
Comparisons show that the new divider is more
efficient in terms of latency, complexity and area
compared to the previous designs based on
restoring and non-restoring architectures [14, 15].
All the proposed architectures are implemented in
the QCAD Designer tool [16], resulting in a decrease
in gate counts and the level in the QCA design.
QCA BACKGROUND
In this section, we show an overview of QCA
logic and established design approached synthesis
and target digital logic functions using cells
arrangements.
QCA computing logic
QCA was first introduced by Lent et al. in 1993.
QCA is a novel emerging technology in which logic
states are not stored as voltage levels, but rather
as the position of the individual electrons. A QCA
cell can be viewed as a set of four ‘dots’ that are
positioned at the corner of the square. A quantum
dot is a location of the cell in which a charge can
be localized. The cell contains two extra mobile
electrons that can quantum mechanically tunnel
between the dots. Due to Coulomb repulsion, in
the absence of external electrostatic perturbation,
the electrons are forced to the corner positions to
maximize their separation [17].
QCA operates by the Columbia interaction that
connects the state of one cell to the state of the
neighbours, unlike the conventional logic circuits
in which information is transferred by electrical
current. The two-polarization orientation encodes
the data, ‘1’ and ‘0’ in QCA. In the binary wire, a
signal propagates from the input to the output due
to the Columbia interactions between the cells.
Due to the presence of even and an odd number
of cell arrange by 45o
(rotated) cells form a buffer
and inverter as shown in Fig. 1b. The inverter is
configured by cell arrangement as shown in Fig. 1c.
The two basic logic gates in QCA are the majority
gate and the inverter. The logic function of majority
gate is M (A, B, C) = AB + AC + BC, where A, B
and C are three inputs. In a CMOS based system,
timing is controlled through a reference signal
(i.e., a clock) and is mostly required for sequential
circuits. However, timing in QCA is necessary for
both combinational and sequential circuits and is
accomplished by clocking in four distinct periodic
phases [18]. Clocking provides power gains in QCA
[19] as well as the control of the information flow
between the cells.
The shape of three-input and five-input majority
gate, inverter and polarization are drawn in Fig. 1d.
The electrostatic repulsion in between the electrons
of the primary input cells, the driver cell is polarized
and the majority gate performing, subsequently,
primary output is shown by the outer cell. Five-
input majority gate has fitting in a similar way to the
three-input majority gate to generate the Boolean
expression of OR, AND. In this way, all the digital
designs are based on the majority gate and inverter.
Four Clocking Mechanism: In QCA 4-clocking
is considered for information flow. Each group of
cells is considered by same clock zone. The picture
of a four clock is presented in Fig 1e. There is seen
a 900
phase-delay from previous clocking zone
to next clock as drawn in Fig. 1e. QCA clocking
provides signal energy-restoration and timing-
synchronization.
EXISTING DIVIDER ARCHITECTURE
The binary division operation is of immense
importance in the field of engineering science.
3. 338
M. K. Hassanzadeh and S. A. Edalatpanah
Int. J. Nano Dimens., 9 (4): 336-345, Autumn 2018
This paper presents a new division architecture
to perform binary number division. Authors in
[14, 15] implemented the non-restoring division
architecture in QCA which is the previous best
design in QCA. According to Ref. [15], an n-bit
divider is formed by n2
CAS cells. Thus, for a 4-bit
division architecture 16 CAS cells and for an 8-bit
division architecture 64 CAS cells are needed. A
single CAS cell consists of a one-bit full adder and a
two-input XOR gate. According to [14] [15], a one-
bit full adder is implemented by 3 majority gates,
2 inverters and an XOR gate are implemented by 3
majority gates, 2 inverters in QCA. So to implement
a 4 bit non restoring architecture 96 majority gates
and 64 inverters needed. Similarly for an 8-bit
non restoring division architecture 384 majority
(a)
(b)
(c)
(d)
Switch
Hold
Release
Relax
Relax Switch Hold
Release
Release Relax Switch Hold
Hold
Release Relax Switch
Time
Clock 0
Clock 1
Clock 2
Clock 3
Fig. 1 QCA Design (a) Even number of cell-based wire (b) Odd number of cell-based wire (c) Inverter (d)
3 and 5 input Majority, inverter, and possible polarization (e) Clocking
Fig. 1. QCA Design (a) Even number of cell-based wire (b) Odd
number of cell-based wire (c) Inverter (d) 3 and 5 input Majority,
inverter, and possible polarization (e) Clocking.
4. 339Int. J. Nano Dimens., 9 (4): 336-345, Autumn 2018
M. K. Hassanzadeh and S. A. Edalatpanah
gates and 256 inverters needed. The limitation
of non restoring division architecture is that for
a n-bit size divisor, 2n-bit size dividend is needed.
In majority applications for n bit processor
architecture, n-bit dividend and n-bit divisor are
needed for division operations. In this paper, we
designed a n-bit by n-bit division architecture
in QCA which consist of lesser majority gates
and inverters compared to n-bit non-restoring
division architecture [14, 15].
Proposed division architecture
This paper presents the architecture of a novel
division algorithm for binary numbers, which is
implemented in QCA. Fig. 2 shows two examples
in binary numbers to explain the above process.
The steps of an algorithm for binary numbers are
explained as follows:
i. Divide A(2) by B(2). Here quotient obtained is
‘Q’ and Remainder is ʽR’.
ii. Append the remainder R to the left of A (1) and
form RʽA (1)’ called C.
iii. Now multiply Q by B(1) called D and subtract
the results of this multiplication from value C
obtained in step 3.
iv. If the result of the subtraction is equal to or
greater than 0, then the result is the final
remainder.
v. If the result of the subtraction is less than 0,
then decrease the final quotient by 1 and
append B(2) to the left of A(1) to form new C.
vi. Multiply the updated quotient ‘Q’ with the
B(1) to form new D.
vii. Subtract D from C to get final Remainder and
updatedquotientofstep6isthefinalquotient‘Q’.
The mathematical modelling of this binary
division algorithm is explained below for n number
of bits. This model highlights the significant ease
of computations and operations. Block diagram of
the binary divider for a 4-by-4 bit is shown in Fig. 3.
Fig. 2 shows two examples in binary numbers to explain the above process. The steps of an
numbers are explained as follows:
i. Let the dividend be ‘A’ and divisor is ‘B’. Split ‘A’ and ‘B’ into two parts, each with equa
as B(1) and B(2) and ‘A’ be split as A(1) and A(2). Here B(1) is LSB part of B and B(2) is MSB par
is LSB part of A and A (2) is MSB part of A.
ii. Divide A(2) by B(2). Here quotient obtained is ‘Q’ and Remainder is ʽR’.
iii. Append the remainder R to the left of A (1) and form RʽA (1)’ called C.
iv. Now multiply Q by B(1) called D and subtract the results of this multiplication from valu
3.
v. If the result of the subtraction is equal to or greater than 0, then the result is the final
vi. If the result of the subtraction is less than 0, then decrease the final quotient by 1 and
left of A(1) to form new C.
vii. Multiply the updated quotient ‘Q’ with the B(1) to form new D.
viii. Subtract D from C to get final Remainder and updated quotient of step 6 is the final qu
The mathematical modelling of this binary division algorithm is explained below for n numbe
highlights the significant ease of computations and operations. Block diagram of the binary divi
shown in Fig. 3.
��� � � � �𝑛𝑛� 𝑖𝑖 � �
𝑛𝑛
2
� � � �
𝐴𝐴�𝑖𝑖�
𝐵𝐵�𝑖𝑖�
� 𝑅𝑅 � � � � �1�
��� � � � �𝑛𝑛� 𝑖𝑖 � �
�
�
� � � � �
����
����
� � 1 �2�
� � �𝐴𝐴�𝑖𝑖��
𝑅𝑅𝑅�
� � 𝑅𝑅1 � ����𝑖𝑖𝑛𝑛��� ��𝐴𝐴�𝑖𝑖��𝐵𝐵�𝑖𝑖� (3)
� � 𝐵𝐵�𝑖𝑖 � �� � �
����
����
� ���
𝑅𝑅 � � � �� 𝑅𝑅 � �𝑖𝑖𝑛𝑛�� 𝑅𝑅���𝑖𝑖𝑛𝑛��� ���
(1)
(2)
(3)
(4)
(5)
Hierarchical design
The proposed method is suitably modified for
QCA implementation using the block diagram
discussed shown in Fig. 3. This is a block diagram
for a simple 4-by-4 bit division that uses a 2-by-2
bit divider, a comparator, two 2 bit multiplier, two
4 bit subtraction blocks and a 2-bit decremented
block. Because it is a hierarchical structure, this
4-by-4 bit division block will form the first block of
the 8-by-8 bit division. The 8-by-8 bit division block
can be built in a similar manner. The advantage of
this method is that to carry an 8-by-8 bit division,
we will ultimately be using only one 2-by-2 bit
division block. Dividers for large word sizes can be
implemented simply by adding additional bit slices
in an array pattern. Thus, we find that the division
circuit can be designed without division.
Design of subcomponents
In this paper, a 4-by-4 bit divider and 8-by-
8 divider are implemented in QCA. The basic
components for a 4-by-4 bit divider are 2-by-2
bit divider, 2-bit multiplier, 4-bit subtractor, 2 bit
decremented block and a 4-bit comparator.
1 1/1 1 1
01 1 1
00 1 0
01 0 1
Remainder
Quotient
01
Example #1 Division
of 1111 by 1010
1 1/1 1 0
00 1 0
00 1 0
01 1 0
00 1 0
01 0 1
C
D
11
10
Remainder
Quotient
01/01
Here C<D, So
Subtraction is
negative, then
go to Step 6
Example #2 Division
of 1110 by 0101
(a) (b)
Figure 2. Division examples (a) 1111 by 1010 (b) 1110 by 0101
Fig. 2. Division examples (a) 1111 by 1010 (b) 1110 by 0101.
5. 340
M. K. Hassanzadeh and S. A. Edalatpanah
Int. J. Nano Dimens., 9 (4): 336-345, Autumn 2018
2-by-2 bit divider Block
Here 2-by-2 bit divider is designed using truth
table and K-map minimization. The corresponding
QCA schematic of the 2 by 2-bit divider circuit in
QCA is shown in Fig. 4. The Boolean expressions
derived for outputs are expressed as below.
R
Figure 3. Block diagram of 4-by-4 proposed binary divider.
3.3 Design of subcomponents
In this paper, a 4-by-4 bit divider and 8-by-8 divider are implemented in QCA. The basic
components for a 4-by-4 bit divider are 2-by-2 bit divider, 2-bit multiplier, 4-bit subtractor, 2 bit
decremented block and a 4-bit comparator.
3.3.1 2-by-2 bit divider Block
Here 2-by-2 bit divider is designed using truth table and K-map minimization. The
corresponding QCA schematic of the 2 by 2-bit divider circuit in QCA is shown in Figure 4. The
Boolean expressions derived for outputs are expressed as below.
Q1 = A1 B0 B1 (6)
Q0 = A0 B0 B1 + A1 B1 (A0 + B0) (7)
R1 = A1 B0 A0 B1 (8)
R0 = A0 B1 (A1 + B0) (9)
Two bit multiplier Block
In this paper, a straightforward binary multiplier
is used because 2-bit multiplication requires
simplerhardwarecomparedtoothermultiplication
algorithms. The algorithm is based on calculating
partial products, shifting them to the left and
then adding them together. A modified half adder
is used in this multiplication architecture. Fig. 5
shows the QCA schematic of half adder and the
multiplier for inputs A (i.e., A1
A0
) and B (i.e., B1
B0
).
The Boolean expression for this half adder is given
below.
2 bit divider
2 bit
multiplier
Rt ‘A(1)’
Comparator
4 bit subtraction
(R=C-D)
Decrement
Q=Q-1
C=B(2) ‘A(1)’
2 bit
multiplier
4 bit subtraction
(R=C-D)
A(2) B(2)
2 2
22
B(1)
Q Rt 2
A(1)
4 4
C<D
C=D C>D
R
B(1) 2 2
4
C
R
Figure 3. Block diagram of 4-by-4 proposed binary divider.
1A
1B
0
2A
2B
0
1A
1
1B
0
1
0
2B
0Q
M
M
M
M
M
M
1A
1B
0
2A
2B
0
1A
0
0
2B
M
M
M
M
M
1B
0
2A
1Q
2B
0
1R
0
M
M
M
0
2A
1B
0R
Figure 4. QCA schematic of 2-by-2 bit divider.
Fig. 3. Block diagram of 4-by-4 proposed binary divider.
Fig. 4. QCA schematic of 2-by-2 bit divider.
6. 341Int. J. Nano Dimens., 9 (4): 336-345, Autumn 2018
M. K. Hassanzadeh and S. A. Edalatpanah
(10)
(11)
In this paper, a straightforward binary multiplier is used because 2-bit multiplication requires
simpler hardware compared to other multiplication algorithms. The algorithm is based on
calculating partial products, shifting them to the left and then adding them together. A modified
half adder is used in this multiplication architecture. Figure 5 shows the QCA schematic of half
adder and the multiplier for inputs A (i.e., A1A0) and B (i.e., B1B0). The Boolean expression for
this half adder is given below.
Sum= (A + B).AB (10)
Carry= AB (11)
0
M
M
M
A
B
1
A
B
0
Sum
M
0A
0B
0
0P
M0B
0
1A
M
0A
1B
0
M
M
1
0
M
1A
1B
0
M
0
M
1
M0
M0
1P
2P
(a)
(b)
Carry
Figure 5. QCA Schematic (a) Half adder (b) Two-bit multiplier
Comparator Block
The comparator is a digital circuit that compares
two input numbers and generates three outputs.
For inputs A and B, then the outputs are A> B, A=B,
0
M
M
M
A
B
1
A
B
0
Sum
M
0A
0B
0
0P
M0B
0
1A
M
0A
1B
0
M
M
1
0
M
1A
1B
0
M
0
M
1
M0
M0
1P
2P
(a)
(b)
Carry
Figure 5. QCA Schematic (a) Half adder (b) Two-bit multiplier
T1
T4
C2
T1
A(3:2) B(3:2) A(1:0) B(1:0)
AeqB(3:0) AbigB(3:0)
BbigA(3:0)
M M
MM
01
)2K:1K(BbigA )2K:1K(AbigB
1ka 1kb 2ka 2kb
M M
)3K:1K(AbigB
)3K:1K(BbigA
)0:4K(BbigA )0:4K(AbigB
)0:1K(BbigA )0:1K(AbigB
M
)0:1K(BbigA
0
)0:1K(AbigB
)0:1K(AeqB
(a) (b) (c)
(d)
Figure 6. QCA schematic of 4 bit comparator [20] (a) T1 (b)T4 (c) C2 (d) Final comparator.
Fig. 5. QCA Schematic (a) Half adder (b) Two-bit multiplier.
Fig. 6. QCA schematic of 4 bit comparator [20] (a) T1 (b)T4 (c) C2 (d) Final comparator.
7. 342
M. K. Hassanzadeh and S. A. Edalatpanah
Int. J. Nano Dimens., 9 (4): 336-345, Autumn 2018
and A<B. In this paper for the 4-bit division, a 4-bit
comparator [20] is used for 8-bit division and the
8-bit comparator is used [20]. QCA schematic of
the 4-bit comparator [20] is shown in Fig. 6.
Four bit Subtractor Block
In this paper, 4-bit subtractor is used in the
final divider circuit. Because subtraction of
two operands is equal to the addition of one
operand with the 2’s complement of the other
operand, the 1-bit adder is the basic component
of the subtractor block. The block diagram of the
subtractor and the QCA schematic diagram of one
bit modified full adder [14] are shown in Fig. 7.
Two bit Decremented block
In this paper, a two-bit decremented block
is used that decreases the given two-bit input
number by 1. To implement this, 2-bit subtractor
is used.
M M
M
Carry
A CB
Sum
1 Bit Full
Adder
1 Bit Full
Adder
1 Bit Full
Adder
1 Bit Full
Adder
3A3B
C
3S
2B 2A 1A1B 0A0B
0S1S2S
(a)
(b)
Figure 7. (a) QCA schematic of Modified full adder [14] (b) Block diagram of 4-bit subtractor.Fig. 7. (a) QCA schematic of Modified full adder [14] (b) Block diagram of 4-bit subtractor.
4 bit divider
4 bit by 2 bit
multiplier
Rt ‘A(1)’
8 bit Subtractor
(C-D)
A(2) B(2)
4 4
24
B(1)
Q Rt 4
A(1)
D C
R
Reverse input
message
x
Input message
Proposed 8 bit
divider
‘r q’ as chipper
text
Z=qxk+r
Reverse message
‘z’
x
q r
z
Key
k
q r
DecryptionblockEncryptionblock
(a)
(b)
Figure 8. (a) 8-bit divider block diagram (b) Algorithm of proposed crypto-hardware.
Fig. 8. (a) 8-bit divider block diagram (b) Algorithm of proposed crypto-hardware.
8. 343Int. J. Nano Dimens., 9 (4): 336-345, Autumn 2018
M. K. Hassanzadeh and S. A. Edalatpanah
Proposed divider implementation
QCA layout of the proposed 4-bit divider is
implemented using the components described in
section 3.3. Other than these components four
extra 2-to-1 multiplexers and two number of two
input AND gates are used. Here the multiplexers
are used to select one 4-bit remainder from two
remaindervaluesasshowninFig.8oftheproposed
divider. Here select inputs of multiplexers are the
output of the comparator. Similarly AND gates
are used to select the final quotient which is the
output of decremented block. Using proposed
4-bit divider block a novel 8-by-8 bit divider is
designed and implemented. To design an 8-by-
8 bit divider steps 6 to 8 of section 3.1 are not
required. The block diagram is shown in Fig. 8.
This divider is further used to design the proposed
novel crypto-hardware.
PROPOSED CRYPTO-HARDWARE
This paper presents a design of symmetric
key cryptography architecture using division
algorithm. Here a novel encryption block and
a decryption block are designed using QCA
technology. Mathematically, cryptosystem is
defined as a 5-tuple (M, K, E, C, D), where M
is the set of characters used in plain texts, K is
the set of keys, C is the set of cipher texts, E: M
x K -> C is the set of enciphering functions, D:
C x K -> M is the set of deciphering functions.
The Keyspace K is the set of all possible keys.
A brute-force approach for key recovery is
called an Exhaustive Key Search. The number of
possible keys |K| must be large enough to make
an exhaustive key search attack infeasible. For
the secure transmission of data, we must design
functions E and D such that E and D are inverse
functions of each other. The E must not be easily
identifiable to a third party. In a symmetric
key cryptography, a single key is used for both
encryption and decryption. It can be either
stream ciphers or block ciphers. Stream ciphers
operate on a single bit at a time and implement
some form of feedback mechanism so that the
key is constantly changing, whereas in the block
cipher scheme, it encrypts one block of data at
a time using the same key on each block. This
paper describes a crypto-hardware based on a
block cipher scheme where input key is fixed.
But it can be suitably modified to a stream cipher
scheme by designing of a feedback mechanism
for a Key generation.
Algorithm of Proposed Crypto-Hardware
In this section, a more general algorithm is
presented using the division algorithm on a set
of positive integers. Given any positive integer x
and y, there exist unique positive Integers q and
r such that x = qy + r and 0 <r < y. The quotient
and remainder, which are unique integers are
the basic components used in division Algorithm
based crypto-hardware. The algorithm is shown
in Fig. 8b. This paper describes both encryption
and decryption blocks in QCA. The proposed
8-bit divider implements encryption block and
Decryption block is implemented by a 4-bit
multiplier and an 8-bit adder circuit. QCA layout of
proposed crypto-hardware is shown in Fig. 9.
Figure 9. QCA layout of Proposed Crypto-hardware.
Fig. 9. QCA layout of Proposed Crypto-hardware.
9. 344
M. K. Hassanzadeh and S. A. Edalatpanah
Int. J. Nano Dimens., 9 (4): 336-345, Autumn 2018
RESULT ANALYSIS
In this section, we presented the all the
subcomponents and the proposed divider in
QCADesigner v2.0.3 tool [16]. The simulation
was performed using the bistable approximation
engine [17]. The parameters of the simulation
are such as cell size of 18 nm, quantum dots in
the cell have a diameter of 5 nm, adjacent cells
are placed with a center to center distance of 20
nm, the number of samples is 12800, convergence
tolerance is 0.001, effective radius is 65 nm,
relative permittivity is 12.9, clock high is 9.8× 10-
22
, clock low is 3.8×10-23
, clock amplitude factor is
1, layer separation is 11.5, maximum iteration per
sample is 100 [20]. The proposed crypto-hardware
QCA layout is verified using exhaustive testing.
Case Study
In this section, we will discuss a case study to
verify the operation of the proposed cryptographic
architecture. In this case study, we shall illustrate
the encryption and decryption process for a string s.
Let s = “Wiley”. Write ASCII code in binary for each
character. The binary code for s will be “01010111
01101001 01101100 01100101 01111001”.
Encryption Process
Here proposed division algorithm is applied
to each character in binary code. Table 1 shows
the application of encryption process for k =
(01010101)b
.Thus,theencryptedtextyfor“Wiley”
is “0100000010010000010100110110000101000
1010100100101”. Here the length of plain text s is
40 and that of encrypted text is 50 bits long.
Decryption Process
Here encrypted text y will read from right to left.
For each of the 10-bit sequence, we take rightmost
2 bits as q and left most 8 bits as r. Then form z =
qk + r. This z is same as n. Then reversing digits
in z, we get original string x. Consider rightmost
10 bits from string y. It is (0100100101). Here r =
(01001001) and q = (10000), then w = q * k + r =
(10011110). Reversing digits of w, original binary
string (01111001) will be obtained, i.e., character
‘y’. In this way, the process will be applied to all the
group of 10 characters at a time to obtain original
string “Wiley”. Simulation result of the above case
study is shown in Fig. 10.
It is divided into two parts for a clear view of
the results because there is a delay of 203
4� clocks
Table 1. Encryption Process for the Characters in the String “Wiley”
Character Binary (x) n = Reverse (x) q r y= encrypted n (r`q’)
W 01010111 11101010 10 01000000 0100000010
i 01101001 10010110 01 01000001 0100000101
l 01101100 00110110 00 00110110 0011011000
e 01100101 10100110 01 01010001 0101000101
y 01111001 10011110 01 01001001 0100100101
Table 1. Encryption Process for the Characters in the String “Wiley”.
Figure 10. Simulation result of case study example.
Fig. 10. Simulation result of case study example.
Table 2. Brief review and comparison table of the proposed designs
Circuit Complexity Area Latency
4-bit non restoring divider [14] 5124 cells 9.99 µm2
151
4� clocks
4 bit non restoring divider [15] 6865 cells 10.95 µm2
471
4� clocks
4 bit proposed divider 4570 cells 9.92 µm2
141
4� clocks
8 bit proposed divider 7212 cells 13.42 µm2
171
2� clocks
Proposed crypto hardware 3485 cells 25.80 µm2
203
4� clocks
Table 2. Brief review and comparison table of the proposed designs.
10. 345Int. J. Nano Dimens., 9 (4): 336-345, Autumn 2018
M. K. Hassanzadeh and S. A. Edalatpanah
cycle between the inputs and outputs. Here, the
outputs obtained in the right-hand side part of
simulation results are the inputs of the left-hand
side part. Table 2 shows the cell complexity, area
and delay of proposed designs.
CONCLUSION
In this paper, we analyze Vedic divider in QCA as
an extended approach. We focus on submodules
comparator, and divider embedded into Vedic
divider architecture. We present the robust
computing strategy of possible crypto-hardware
implementation using single layer synthesis
approaches and under metrics to evaluate the
circuit. We show that crypto-hardware of divider
created using QCA cell and high speed against
throughput minimize, which has significant
benefits compared to all ASIC based crypto-
hardware circuits. As the design size increases, the
proposed design will show more improvements
compared to other designs in terms of area, and
latency. The proposed circuit can be modified to
any bit size by the proposed division algorithm for
advanced security level.
CONFLICT OF INTEREST
The authors declare that there are no conflicts
of interest regarding the publication of this
manuscript.
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