Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
A novel vedic divider based crypto-hardware for nanocomputing paradigm: An ex...VIT-AP University
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
Design of Binary to BCD Code Converter using Area Optimized Quantum Dot Cellu...CSCJournals
The Integrated Circuit Technology (IC) is growing day to day to improve circuit performance and density for compact systems. A novel technology, Quantum dot Cellular Automata (QCA) was introduced to overcome the scaling limitations of CMOS technology. In order to bring a new paradigm of IC design in an efficient and optimized manner, a binary to BCD code converter is designed using QCA technology based area optimized adder. It is observed that the proposed binary to BCD code converter design gives better results in terms of the area and number of QCA cells. The results obtained by the proposed design shows that 61% of area reduced compared to boolean expression based design, this design is further optimized to reduce the QCA cell count by 45% with respect to the design in [1].
Study and Performance Analysis of MOS Technology and Nanocomputing QCAVIT-AP University
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.
This document discusses a study that analyzes the implementation and performance of novel self-timed asynchronous logic circuits called NULL Convention Logic (NCL) that use a Return-To-Zero protocol. The study compares NCL threshold gates to conventional static CMOS gates through transistor-level simulations. The simulations show that NCL gates have lower power consumption and generate less noise than CMOS gates, though NCL gates have slightly increased delay. Overall, the study finds that NCL provides benefits like low power operation, reduced noise, and robustness compared to standard static CMOS logic.
IRJET - Analysis of Power Consumption in Glitch Free Dual Edge Triggered ...IRJET Journal
This document analyzes power consumption in a glitch-free dual edge triggered flip-flop circuit design. It discusses existing DET flip-flop designs that use C-element circuits or a combination of C-element and 2P-1N structures. The proposed design aims to reduce area, power consumption, and increase speed. It combines a 1P-2N structure with a C-element circuit to provide a glitch-free output and filter out glitches from prior logic stages, improving system efficiency while consuming less power. The design works accurately at low supply voltages and its operation and ability to avoid glitches are explained.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
The document discusses the design of a new fault-tolerant scheme for quantum-dot cellular automata (QCA) logic circuits. It introduces a 2x2 array of four rotated quantum dot cells, called a complementary tile (CT), that can achieve 100% fault tolerance against single cell defects. A new majority voter logic gate called the reliable majority voter (RMV) is designed using the CT that outperforms existing QCA majority gates in terms of reliability. The document analyzes the polarization and functional characteristics of the RMV under different types of cell defects. It also develops an error probability model to quantify the reliability of the proposed RMV design.
A NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCEcscpconf
In recent years, various chaos based modulation schemes were evolved, of which the CS-DCSK
modulation technique provides better BER performance and bandwidth efficiency, due to its
code domain approach. The QCSK modulation technique provides double benefit: higher data
rate with similar BER performance and same bandwidth occupation as DCSK. By combining
the advantage of code shifted differential chaos shift keying (CS-DCSK) and Quadrature chaos
shift keying (QCSK) scheme, a novel CS-QCSK modulation scheme called code shifted
Quadrature chaos shift keying is proposed. The noise performance of CS-QCSK is better to
most conventional modulation schemes and also provides an increased data transmission rates
with greatly improved robustness. Analytical expressions for the bit-error rates are derived for
both AWGN channel and Rayleigh multipath fading channel. The simulation result shows that
the proposed method outperforms classical chaotic modulation schemes in terms of bit error rate (BER).
A novel vedic divider based crypto-hardware for nanocomputing paradigm: An ex...VIT-AP University
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
Design of Binary to BCD Code Converter using Area Optimized Quantum Dot Cellu...CSCJournals
The Integrated Circuit Technology (IC) is growing day to day to improve circuit performance and density for compact systems. A novel technology, Quantum dot Cellular Automata (QCA) was introduced to overcome the scaling limitations of CMOS technology. In order to bring a new paradigm of IC design in an efficient and optimized manner, a binary to BCD code converter is designed using QCA technology based area optimized adder. It is observed that the proposed binary to BCD code converter design gives better results in terms of the area and number of QCA cells. The results obtained by the proposed design shows that 61% of area reduced compared to boolean expression based design, this design is further optimized to reduce the QCA cell count by 45% with respect to the design in [1].
Study and Performance Analysis of MOS Technology and Nanocomputing QCAVIT-AP University
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.
This document discusses a study that analyzes the implementation and performance of novel self-timed asynchronous logic circuits called NULL Convention Logic (NCL) that use a Return-To-Zero protocol. The study compares NCL threshold gates to conventional static CMOS gates through transistor-level simulations. The simulations show that NCL gates have lower power consumption and generate less noise than CMOS gates, though NCL gates have slightly increased delay. Overall, the study finds that NCL provides benefits like low power operation, reduced noise, and robustness compared to standard static CMOS logic.
IRJET - Analysis of Power Consumption in Glitch Free Dual Edge Triggered ...IRJET Journal
This document analyzes power consumption in a glitch-free dual edge triggered flip-flop circuit design. It discusses existing DET flip-flop designs that use C-element circuits or a combination of C-element and 2P-1N structures. The proposed design aims to reduce area, power consumption, and increase speed. It combines a 1P-2N structure with a C-element circuit to provide a glitch-free output and filter out glitches from prior logic stages, improving system efficiency while consuming less power. The design works accurately at low supply voltages and its operation and ability to avoid glitches are explained.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
The document discusses the design of a new fault-tolerant scheme for quantum-dot cellular automata (QCA) logic circuits. It introduces a 2x2 array of four rotated quantum dot cells, called a complementary tile (CT), that can achieve 100% fault tolerance against single cell defects. A new majority voter logic gate called the reliable majority voter (RMV) is designed using the CT that outperforms existing QCA majority gates in terms of reliability. The document analyzes the polarization and functional characteristics of the RMV under different types of cell defects. It also develops an error probability model to quantify the reliability of the proposed RMV design.
A NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCEcscpconf
In recent years, various chaos based modulation schemes were evolved, of which the CS-DCSK
modulation technique provides better BER performance and bandwidth efficiency, due to its
code domain approach. The QCSK modulation technique provides double benefit: higher data
rate with similar BER performance and same bandwidth occupation as DCSK. By combining
the advantage of code shifted differential chaos shift keying (CS-DCSK) and Quadrature chaos
shift keying (QCSK) scheme, a novel CS-QCSK modulation scheme called code shifted
Quadrature chaos shift keying is proposed. The noise performance of CS-QCSK is better to
most conventional modulation schemes and also provides an increased data transmission rates
with greatly improved robustness. Analytical expressions for the bit-error rates are derived for
both AWGN channel and Rayleigh multipath fading channel. The simulation result shows that
the proposed method outperforms classical chaotic modulation schemes in terms of bit error rate (BER).
Energy efficient and high speed domino logic circuitsIJERA Editor
Domino CMOS circuit family finds a wide variety of application in microprocessors due to low device count and high speed.In this paper, various conventional and proposed designs for low leakage and high speed wide fan-in domino circuits are reviewed. The techniques used in the paper reduces the total power dissipation and delay by 25% and 58% respectively as compared to the conventional footed domino logic circuit. Simulations are performed on tanner tool at 65nm technology for 16 input OR gate.
Design of magnetic dipole based 3D integration nano-circuits for future elect...VIT-AP University
Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectures have been designed using pNML in MagCAD tool, simulated with modelsim platform and correctness shown by simulation waveform. The correctness of these designs can be verified easily when Verilog code is generated from MagCAD tool. The performance of the proposed comparator towards default parameters shows the area of 2.4336 μm2 and critical path of 1.5E-7 sec. As a higher order, the realization of a 4-to-1 multiplexer in NML has also been included in this work.
This document describes an FPGA-based address generator for the deinterleaver used in WiMAX systems. It proposes algorithms to generate addresses for the deinterleaver that support different modulation schemes like QPSK, 16-QAM, and 64-QAM without using a floor function. The algorithms are implemented using VHDL on a Xilinx FPGA. Simulation results show the address generation for different modulation types matches the output of a MATLAB program. The FPGA implementation provides better performance and resource utilization than a conventional LUT-based approach.
Fpga based low power and high performance address generator for wimax deinter...eSAT Journals
Abstract
The main aim of this project is to generate the address generation circuitry of Deinterleaver used in the WiMAX transreceiver using
the Xilinx Field Programmable Gate Array(FPGA). The floor function associated with the implementation of FPGA is very difficult in
IEEE 802.16e standard. So we eliminate the requirement of floor function by using a simple mathematical algorithm. Some
modulations like QPSK, 16-QAM and 64-QAM along with its code rates make our approach to be novel and high efficient.
Keywords— Modulation circuits, Deinterleaver/Interleaver circuit, Wireless SYSTEMS
DESIGNING AN EFFICIENT APPROACH FOR JK AND T FLIP-FLOP WITH POWER DISSIPATION...VLSICS Design
QCA (Quantum Dot Cellular Automata) is an emerging and pioneer technology, which is a paradigm for
computing with interacting quantum dots. Many eminent researchers have well thought of eloquent work in
the existing areas of the sequential circuit. However, this paper proclaims three new approaches to design
JK and T flip-flop. Since flip-flops and memory design are the crucial building blocks of digital circuits,
therefore we concern the underlying principle of fundamental design of JK and T flip-flop and then work
out to model the new structure favorable with the forthcoming excellence required. This new concept
places elsewhere the need of using feedback path in flip flop design. Also two algorithms have been shown
for explanatory purpose. The proposed structure is able to establish the validity and genuineness than
earlier design. By using the proposed T flip-flop, a 2-bit and 3-bit counter is also designed in the paper.
The simulation result of the proposed design proves their vigorousness and correctness in the output.
MULTIUSER BER ANALYSIS OF CS-QCSK MODULATION SCHEME IN A CELLULAR SYSTEM ijwmn
In recent years, chaotic communication is a hot research topic and it suits better for the emerging wireless networks because of its excellent features. Different chaos based modulation schemes have evolved, of which the CS-DCSK modulation technique provides better BER performance and bandwidth
efficiency, due to its code domain approach. The QCSK modulation technique provides double benefit: higher data rate with similar BER performance and same bandwidth occupation as DCSK. By combining the advantage of code shifted differential chaos shift keying (CS-DCSK) and Quadrature chaos shift keying (QCSK) scheme, a novel modulation scheme called code shifted Quadrature chaos shift keying (CS-QCSK) is proposed and its suitability in a multiuser scenario is tested in this paper. The analytical expressions for the bit-error rate for Multi-user CS-QCSK scheme (MU-CS-QCSK) under Rayleigh
multipath fading channel is derived. The simulation result shows that, in multiuser scenario the proposed method outperforms classical chaotic modulation schemes in terms of bit error rate (BER).
Designing of an Energy-Efficient Nanoelectronics Architecture for Binary Comp...VIT-AP University
Quantum-dot cellular automata is a nanoscale computation circuit design approach which computes bits via charges
among quantum-dot in the quantum cell of QCA. This technology has promises the feature of energy efficient and high
density in the era of high-speed nanotechnology. This article contributes a new nanoscale design of binary comparator
with less latency, area, and clock utilized. The proposed comparator architecture is robust and enjoys wire crossing
without any crossover, which needs only normal and rotated cells. All the simulation results and calculated parameters
are based on the QCADesigner tool. QCAPro tool based approach has been used to perform the energy dissipation
estimation of the new comparator architecture. A better primitives results as compared to state-of-art technology has
been achieved and good contribution in this area.
An approach to Measure Transition Density of Binary Sequences for X-filling b...IJECEIAES
Switching activity and Transition density computation is an essential stage for dynamic power estimation and testing time reduction. The study of switching activity, transition densities and weighted switching activities of pseudo random binary sequences generated by Linear Feedback shift registers and Feed Forward shift registers plays a crucial role in design approaches of Built-In Self Test, cryptosystems, secure scan designs and other applications. This paper proposed an approach to find transition densities, which plays an important role in choosing of test pattern generator We have analyze conventional and proposed designs using our approache, This work also describes the testing time of benchmark circuits. The outcome of this paper is presented in the form of algorithm, theorems with proofs and analyses table which strongly support the same. The proposed algorithm reduces switching activity and testing time up to 51.56% and 84.61% respectively.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design High Performance Combinational Circuits Using Output Prediction Logic-...IOSRJECE
With the continuously increasing demand for low power & high speed VLSI circuits the brain storming among the scientists, inventors & researchers to find the techniques required to design such high performance circuits is also increasing day by day. In the answer to this search several design techniques have been found. Output prediction logic-OPL technique is one of such newly introduced techniques. OPL is a technique that can be applied to conventional CMOS logic families in order to obtain considerable speedups. Speedups of two to three times over static CMOS logic are demonstrated for a variety of combinational circuits. When applied to static CMOS the OPL retains the restoring nature of underlying logic family. In case of OPL applied to the pseudo NMOS & domino logic, the problem of excessive power dissipation is solved & speedups more than static CMOS logic is obtained
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
This document describes the design of quaternary logical circuits using voltage mode and current mode logic. It summarizes that quaternary voltage mode logic has 51.78% lower power consumption compared to binary, but requires 3 times more transistors. Quaternary current mode logic has lower area than voltage mode, but higher power consumption. Specifically, it presents the design of quaternary logic gates like inverters, MIN, MAX gates for both modes. Comparative analysis shows voltage mode has lower power while current mode has lower area.
A Fault-tolerant Switch for Next Generation Computer NetworksIDES Editor
In this paper, the architecture of a Multi-plane
Parallel Deflection-Routed Circular Banyan (PDCB) network
based switching fabric is introduced. The PDCB network has
a cyclic, regular, self-routing, simple architecture and fairly
good performance. Its Performance is improved due to
reduction in blocking by two-dimensional path-multiplicity of
the proposed architecture. It consists of 4X4 Switching
Elements.
The proposed switch is shown to be fault-tolerant. A simple
analytical model based on Markov chain to evaluate the
performance of proposed switch under uniform traffic
condition has also been presented in this paper. The
performance parameters studied are Normalized Throughput
and Normalized Delay. Simulation study of the switch is also
performed to validate the model proposed.
Embedded fuzzy controller for water level control IJECEIAES
This article presents the design of a fuzzy controller embedded in a microcontroller aimed at implementing a low-cost, modular process control system. The fuzzy system's construction is based on a classical proportional and derivative controller, where inputs of error and its derivate depend on the difference between the desired setpoint and the actual level; the goal is to control the water level of coupled tanks. The process is oriented to control based on the knowledge that facilitates the adjustment of the output variable without complex mathematical modeling. In different response tests of the fuzzy controller, a maximum over-impulse greater than 8% or a steady-state error greater than 2.1% was not evidenced when varying the setpoint.
A COMPARATIVE STUDY OF ULTRA-LOW VOLTAGE DIGITAL CIRCUIT DESIGNVLSICS Design
Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which, however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delayinsensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.
Iaetsd low power flip flops for vlsi applicationsIaetsd Iaetsd
The document discusses low power flip flops for use in digitally controlled delay lines (DCDLs). It first describes issues with conventional NAND-based DCDLs, such as glitches that occur when the control code changes. It then proposes using a Low Power Forced Stack Clocked Pass Transistor flip-flop (LP-FSCPTFF) as the driving circuit in the DCDL. This flip-flop architecture consumes less power and has lower delay than dual edge triggered flip flops used conventionally. Simulation results show the proposed DCDL using LP-FSCPTFF reduces power consumption by up to 90% compared to other efficient flip-flop designs. The low power DCD
The document describes a proposed LP-HS logic style and its application in designing an ultra low power high speed multiplier accumulator (MAC) unit for digital signal processing applications. The LP-HS logic is derived from an existing constant delay logic style to reduce power and delay. A MAC unit is designed using both the constant delay logic and proposed LP-HS logic. Simulation results in 45nm, 32nm, 22nm, and 16nm CMOS technologies show the LP-HS logic MAC unit achieves up to 94% reduction in power delay product compared to the constant delay logic MAC unit. Therefore, the proposed LP-HS logic is concluded to be better suited for high performance, low power MAC unit design.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
Growing demand for clean and green power has increased penetration of renewable energy sources into microgrid. Based on the demand supply, microgrid can be operated in grid connected mode and islanded mode. Intermittent nature of renewable energy sources such as solar and wind has lead to number of control challenges in both modes of operation. Especially islanded microgrid throws power quality issues such as sag, swell, harmonics and flicker. Since medical equipments, semiconductor factory automations are very sensitive to voltage variations and therefore voltage sag in an islanded microgrid is of key significance. This paper proposes a half cycle discrete transformation (HCDT) technique for fast detection of voltage sag in an islanded microgrid and thereby provides fast control action using dynamic voltage restorer (DVR) to safe guard the voltage sensitive equipments in an islanded microgrid. The detailed analysis of simulation results has clearly demonstrated the effectiveness of proposed method detects the voltage sag in 0.04 sec and there by improves the voltage profile of islanded microgrid.
A modular approach for testable conservative reversible multiplexer circuit f...VIT-AP University
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with
prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm,
which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing
framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative
reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters
in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count,
quantum cost and unit delay are optimal.
Cost-effective architecture of decoder circuits and futuristic scope in the e...VIT-AP University
The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.
Energy efficient and high speed domino logic circuitsIJERA Editor
Domino CMOS circuit family finds a wide variety of application in microprocessors due to low device count and high speed.In this paper, various conventional and proposed designs for low leakage and high speed wide fan-in domino circuits are reviewed. The techniques used in the paper reduces the total power dissipation and delay by 25% and 58% respectively as compared to the conventional footed domino logic circuit. Simulations are performed on tanner tool at 65nm technology for 16 input OR gate.
Design of magnetic dipole based 3D integration nano-circuits for future elect...VIT-AP University
Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectures have been designed using pNML in MagCAD tool, simulated with modelsim platform and correctness shown by simulation waveform. The correctness of these designs can be verified easily when Verilog code is generated from MagCAD tool. The performance of the proposed comparator towards default parameters shows the area of 2.4336 μm2 and critical path of 1.5E-7 sec. As a higher order, the realization of a 4-to-1 multiplexer in NML has also been included in this work.
This document describes an FPGA-based address generator for the deinterleaver used in WiMAX systems. It proposes algorithms to generate addresses for the deinterleaver that support different modulation schemes like QPSK, 16-QAM, and 64-QAM without using a floor function. The algorithms are implemented using VHDL on a Xilinx FPGA. Simulation results show the address generation for different modulation types matches the output of a MATLAB program. The FPGA implementation provides better performance and resource utilization than a conventional LUT-based approach.
Fpga based low power and high performance address generator for wimax deinter...eSAT Journals
Abstract
The main aim of this project is to generate the address generation circuitry of Deinterleaver used in the WiMAX transreceiver using
the Xilinx Field Programmable Gate Array(FPGA). The floor function associated with the implementation of FPGA is very difficult in
IEEE 802.16e standard. So we eliminate the requirement of floor function by using a simple mathematical algorithm. Some
modulations like QPSK, 16-QAM and 64-QAM along with its code rates make our approach to be novel and high efficient.
Keywords— Modulation circuits, Deinterleaver/Interleaver circuit, Wireless SYSTEMS
DESIGNING AN EFFICIENT APPROACH FOR JK AND T FLIP-FLOP WITH POWER DISSIPATION...VLSICS Design
QCA (Quantum Dot Cellular Automata) is an emerging and pioneer technology, which is a paradigm for
computing with interacting quantum dots. Many eminent researchers have well thought of eloquent work in
the existing areas of the sequential circuit. However, this paper proclaims three new approaches to design
JK and T flip-flop. Since flip-flops and memory design are the crucial building blocks of digital circuits,
therefore we concern the underlying principle of fundamental design of JK and T flip-flop and then work
out to model the new structure favorable with the forthcoming excellence required. This new concept
places elsewhere the need of using feedback path in flip flop design. Also two algorithms have been shown
for explanatory purpose. The proposed structure is able to establish the validity and genuineness than
earlier design. By using the proposed T flip-flop, a 2-bit and 3-bit counter is also designed in the paper.
The simulation result of the proposed design proves their vigorousness and correctness in the output.
MULTIUSER BER ANALYSIS OF CS-QCSK MODULATION SCHEME IN A CELLULAR SYSTEM ijwmn
In recent years, chaotic communication is a hot research topic and it suits better for the emerging wireless networks because of its excellent features. Different chaos based modulation schemes have evolved, of which the CS-DCSK modulation technique provides better BER performance and bandwidth
efficiency, due to its code domain approach. The QCSK modulation technique provides double benefit: higher data rate with similar BER performance and same bandwidth occupation as DCSK. By combining the advantage of code shifted differential chaos shift keying (CS-DCSK) and Quadrature chaos shift keying (QCSK) scheme, a novel modulation scheme called code shifted Quadrature chaos shift keying (CS-QCSK) is proposed and its suitability in a multiuser scenario is tested in this paper. The analytical expressions for the bit-error rate for Multi-user CS-QCSK scheme (MU-CS-QCSK) under Rayleigh
multipath fading channel is derived. The simulation result shows that, in multiuser scenario the proposed method outperforms classical chaotic modulation schemes in terms of bit error rate (BER).
Designing of an Energy-Efficient Nanoelectronics Architecture for Binary Comp...VIT-AP University
Quantum-dot cellular automata is a nanoscale computation circuit design approach which computes bits via charges
among quantum-dot in the quantum cell of QCA. This technology has promises the feature of energy efficient and high
density in the era of high-speed nanotechnology. This article contributes a new nanoscale design of binary comparator
with less latency, area, and clock utilized. The proposed comparator architecture is robust and enjoys wire crossing
without any crossover, which needs only normal and rotated cells. All the simulation results and calculated parameters
are based on the QCADesigner tool. QCAPro tool based approach has been used to perform the energy dissipation
estimation of the new comparator architecture. A better primitives results as compared to state-of-art technology has
been achieved and good contribution in this area.
An approach to Measure Transition Density of Binary Sequences for X-filling b...IJECEIAES
Switching activity and Transition density computation is an essential stage for dynamic power estimation and testing time reduction. The study of switching activity, transition densities and weighted switching activities of pseudo random binary sequences generated by Linear Feedback shift registers and Feed Forward shift registers plays a crucial role in design approaches of Built-In Self Test, cryptosystems, secure scan designs and other applications. This paper proposed an approach to find transition densities, which plays an important role in choosing of test pattern generator We have analyze conventional and proposed designs using our approache, This work also describes the testing time of benchmark circuits. The outcome of this paper is presented in the form of algorithm, theorems with proofs and analyses table which strongly support the same. The proposed algorithm reduces switching activity and testing time up to 51.56% and 84.61% respectively.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design High Performance Combinational Circuits Using Output Prediction Logic-...IOSRJECE
With the continuously increasing demand for low power & high speed VLSI circuits the brain storming among the scientists, inventors & researchers to find the techniques required to design such high performance circuits is also increasing day by day. In the answer to this search several design techniques have been found. Output prediction logic-OPL technique is one of such newly introduced techniques. OPL is a technique that can be applied to conventional CMOS logic families in order to obtain considerable speedups. Speedups of two to three times over static CMOS logic are demonstrated for a variety of combinational circuits. When applied to static CMOS the OPL retains the restoring nature of underlying logic family. In case of OPL applied to the pseudo NMOS & domino logic, the problem of excessive power dissipation is solved & speedups more than static CMOS logic is obtained
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
This document describes the design of quaternary logical circuits using voltage mode and current mode logic. It summarizes that quaternary voltage mode logic has 51.78% lower power consumption compared to binary, but requires 3 times more transistors. Quaternary current mode logic has lower area than voltage mode, but higher power consumption. Specifically, it presents the design of quaternary logic gates like inverters, MIN, MAX gates for both modes. Comparative analysis shows voltage mode has lower power while current mode has lower area.
A Fault-tolerant Switch for Next Generation Computer NetworksIDES Editor
In this paper, the architecture of a Multi-plane
Parallel Deflection-Routed Circular Banyan (PDCB) network
based switching fabric is introduced. The PDCB network has
a cyclic, regular, self-routing, simple architecture and fairly
good performance. Its Performance is improved due to
reduction in blocking by two-dimensional path-multiplicity of
the proposed architecture. It consists of 4X4 Switching
Elements.
The proposed switch is shown to be fault-tolerant. A simple
analytical model based on Markov chain to evaluate the
performance of proposed switch under uniform traffic
condition has also been presented in this paper. The
performance parameters studied are Normalized Throughput
and Normalized Delay. Simulation study of the switch is also
performed to validate the model proposed.
Embedded fuzzy controller for water level control IJECEIAES
This article presents the design of a fuzzy controller embedded in a microcontroller aimed at implementing a low-cost, modular process control system. The fuzzy system's construction is based on a classical proportional and derivative controller, where inputs of error and its derivate depend on the difference between the desired setpoint and the actual level; the goal is to control the water level of coupled tanks. The process is oriented to control based on the knowledge that facilitates the adjustment of the output variable without complex mathematical modeling. In different response tests of the fuzzy controller, a maximum over-impulse greater than 8% or a steady-state error greater than 2.1% was not evidenced when varying the setpoint.
A COMPARATIVE STUDY OF ULTRA-LOW VOLTAGE DIGITAL CIRCUIT DESIGNVLSICS Design
Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which, however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delayinsensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.
Iaetsd low power flip flops for vlsi applicationsIaetsd Iaetsd
The document discusses low power flip flops for use in digitally controlled delay lines (DCDLs). It first describes issues with conventional NAND-based DCDLs, such as glitches that occur when the control code changes. It then proposes using a Low Power Forced Stack Clocked Pass Transistor flip-flop (LP-FSCPTFF) as the driving circuit in the DCDL. This flip-flop architecture consumes less power and has lower delay than dual edge triggered flip flops used conventionally. Simulation results show the proposed DCDL using LP-FSCPTFF reduces power consumption by up to 90% compared to other efficient flip-flop designs. The low power DCD
The document describes a proposed LP-HS logic style and its application in designing an ultra low power high speed multiplier accumulator (MAC) unit for digital signal processing applications. The LP-HS logic is derived from an existing constant delay logic style to reduce power and delay. A MAC unit is designed using both the constant delay logic and proposed LP-HS logic. Simulation results in 45nm, 32nm, 22nm, and 16nm CMOS technologies show the LP-HS logic MAC unit achieves up to 94% reduction in power delay product compared to the constant delay logic MAC unit. Therefore, the proposed LP-HS logic is concluded to be better suited for high performance, low power MAC unit design.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
Growing demand for clean and green power has increased penetration of renewable energy sources into microgrid. Based on the demand supply, microgrid can be operated in grid connected mode and islanded mode. Intermittent nature of renewable energy sources such as solar and wind has lead to number of control challenges in both modes of operation. Especially islanded microgrid throws power quality issues such as sag, swell, harmonics and flicker. Since medical equipments, semiconductor factory automations are very sensitive to voltage variations and therefore voltage sag in an islanded microgrid is of key significance. This paper proposes a half cycle discrete transformation (HCDT) technique for fast detection of voltage sag in an islanded microgrid and thereby provides fast control action using dynamic voltage restorer (DVR) to safe guard the voltage sensitive equipments in an islanded microgrid. The detailed analysis of simulation results has clearly demonstrated the effectiveness of proposed method detects the voltage sag in 0.04 sec and there by improves the voltage profile of islanded microgrid.
A modular approach for testable conservative reversible multiplexer circuit f...VIT-AP University
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with
prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm,
which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing
framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative
reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters
in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count,
quantum cost and unit delay are optimal.
Cost-effective architecture of decoder circuits and futuristic scope in the e...VIT-AP University
The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.
Analysis on Fault Mapping of Reversible Gates with Extended Hardware Descript...VIT-AP University
Quantum-dot cellular automata is a modern computing paradigm, conceived in feature of nanometer
scale with high integration density, and significant low power. For the QCA technology, making these
high-density design means an increase in the complexity which in turn leads to growth in the number of faults. The defect model presented in this paper categorized into two types, which include single missing and additional cell considering for QCA fault. Proposed gates have been designed in the
QCA and verified. The proposed Fredkin gate design has been compared with an existing design,
and 43% and 70% improvement in cell count and area respectively are revealed. Also, the Toffoli
design in QCA which achieve some parameters such as cell complexity of 39, and the average fault tolerance of 53.5%. The polarization value for both single cells missing an addition cell missing has been studied to explain the logic signal strength effect physically. A QCA framework for the 3-input
Ex-OR, 2:1 multiplexer, Fredkin, and Toffoli gate for the fault problem in which reliability analysis based on Hardware description language for QCA devices (HDLQ) is discussed and verified on the fault pattern look-up table.
Implementation of Non-restoring Reversible Divider Using a Quantum-Dot Cellul...VIT-AP University
The document describes the design and implementation of a non-restoring reversible divider circuit using quantum-dot cellular automata (QCA). Key points:
1) A non-restoring divider circuit was designed using Feynman and Haghparast gates in a reversible logic approach to minimize quantum cost and garbage outputs.
2) The divider circuit was synthesized and implemented in QCADesigner, achieving a cell complexity of 269 and area of 0.54 μm2.
3) The proposed reversible divider design was shown to have lower quantum cost, fewer garbage outputs, and gates than previous non-reversible divider designs.
Approach to design a high performance fault-tolerant reversible ALUVIT-AP University
In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular
automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to
optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design
focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.
IRJET- A Novel Design of Flip Flop and its Application in Up CounterIRJET Journal
1) The document proposes a novel design of flip flops and a 4-bit up counter using Quantum-Dot Cellular Automata (QCA) technology. QCA is an emerging nanotechnology that could overcome scaling limitations of CMOS.
2) In QCA, logic states are represented by the position of electrons in quantum dots rather than voltage as in CMOS. Basic logic gates like inverters and majority gates are constructed using QCA cells.
3) The document designs various flip flops like SR, JK, D, and T flip flops in QCA and uses them to build a 4-bit up counter. Power consumption is shown to be lower for the QCA designs compared to
Design of Quantum Dot Cellular Automata Based Parity Generator and Checker wi...VIT-AP University
Quantum-dot Cellular Automata is an alternative to CMOS technology for the future digital designs. When compared to its CMOS counterpart, it has extremely low power consumption, as there is no current flow in cell. The methodology of parity generator and checker is based on the parity generation and matched it at the receiver end. By using the parity match bits, the error in circuit can be sensed. In this paper, novel parity generator and detector circuit are introduced. The circuit is designed in single layer, minimum clock and minimum latency, which is achieved in QCA framework. The proposed circuits are better than the existing in terms of clock cycle delay, cell complexity and clock cycle utilize. The simulation of presented cell structures have been verified using QCA designer tool. In addition, QCA Probabilistic (QCAPro) tool is used to calculate the minimum, maximum and average energy dissipation aspect in proposed QCA circuit. Appropriate comparison table and power analysis is shown to prove that our proposed circuit is cost effective.
Regular clocking scheme based design of cost-efficient comparator in QCAnooriasukmaningtyas
Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.
Two Bit Arithmetic Logic Unit (ALU) in QCAidescitation
Quantum cellular automata (QCA) is a new
technology in nanometre scale (<18nm) to support nano
technology. QCA is very effective in terms of high space density
and power dissipation and will be playing a major role in the
development of the Quantum computer with low power
consumption and high speed. This paper describes the design
and layout of a 2-bit ALU based on quantum-dot cellular
automata (QCA) using the QCADesigner design tool. The
ALU design is based on combinational circuits which reduces
the required hard-ware complexity and allows for reasonable
simulation times. The paper aims to provide evidence that
QCA has potential applications in future Quantum computers,
provided that the underlying technology is made feasible.
Design has been made using certain combinational circuits
by using Majority gate, AND, OR, NOT, X-OR in QCA. 2 bit
ALU needs the design of Logical Extender, Arithmetic
Extender and the Full adder circuits using QCA. The QCA is
a novel tool to realize Nano level digital devices and study and
analyze their various parameters.
Presentation of a fault tolerance algorithm for design of quantum-dot cellul...IJECEIAES
A novel algorithm for working out the Kink energy of quantum-dot cellular automata (QCA) circuits and their fault tolerability is introduced. In this algorithm at first with determining the input values on a specified design, the calculation between cells makes use of Kink physical relations will be managed. Therefore, the polarization of any cell and consequently output cell will be set. Then by determining missed cell(s) on the discussed circuit, the polarization of output cell will be obtained and by comparing it with safe state or software simulation, its fault tolerability will be proved. The proposed algorithm was implemented on a novel and advance fault tolerance full adder whose performance has been demonstrated. This algorithm could be implemented on any QCA circuit. Noticeably higher speed of the algorithm than simulation and traditional manual methods, expandability of this algorithm for variable circuits, beyond of four-dot square of QCA circuits, and the investigation of several damaged cells instead just one and special cell are the advantages of algorithmic action.
Abstract: A technology called Quantum Dot Cellular Automata (QCA) offers a far more effective computational
platform than CMOS. Through the polarization of electrons, digital information is represented. In comparison to
CMOS technology, it is more attractive because to its size, faster speed, feature, high degree of scalability, greater
switching frequency, and low power consumption. This paper suggests structures of basic logic gates in the QCA
technology. For the aim of verification, the produced circuits aresimulated, and their results are then compared
to those of their published counterparts. The comparison outcomes provide hope for adding the suggested
structures to the collection of QCA gates.
A parity generator is a circuit that generates redundant bits used for error detection
and is used when transmitting binary information. Previous parity generator circuits
based on quantum-dot cellular automata (QCA) are designed to reduce the area of the
circuit. Input cells of existing circuit are designed inside the circuit and the circuit’s
signal is not propagated properly due to the influence between adjacent wires. In
addition, existing circuits consume many clocks because the XOR gate, which is an
essential component of the parity generator circuit, consumes many clocks. In order to
solve this problem, we design a 3-bit odd parity generator circuit using QCA for fast
operation. The proposed circuit uses an XOR gate that can operate one clock faster
than the existing XOR gate to reduce the clock, and by extending this XOR gate, the
output value can be obtained faster than the conventional circuit. In the proposed
circuit, the result is verified through simulation and the performance is compared with
the existing circuit
A Novel and Efficient Design for Squaring Units by Quantum-Dot Cellular AutomataVIT-AP University
Quantum cell automata (QCA) are the best possible alternative to the
conventional CMOS technology due to its low power consumption, less area and high-speed operation. This paper describes synthesizable QCA implementation of squaring. Vedic sutras used for squaring are defined over algorithm construction. Based on the concept of the Vedic sutra, this paper has carried out 2-bit square and
4-bit square, projective to affine logic gates construction. Importantly for miniaturization
of devices, the QCA based square is the operation on which the area of
circuits relies on. This means that significantly lower QCA parameters can be used in
the square than in other competitive square circuits such as Wallace, Dadda, serial parallel,
and Baugh-Wooley.
An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full AdderVIT-AP University
Moving towards micrometre scale to nanometre scale device shrinks down emerging nanometre technology such as quantum-dot cellular automata as a nesting
success. The introduced architecture is robust where the explicit design of full adder
and full subtraction uses for Ex-OR design. A new architecture of Ex-OR based on one majority gate is proposed, which its most optimized architecture and its placement of cells from the novel design. The analysis based on simulation showed that the
introduced Ex-OR and full adder makes only 11 and 46 cells count, respectively. In
proposed Ex-OR design, first output is received with no any latency which can be a
suitable design for implementation of the high-speed full adder design. In addition,
power estimation results are obtained after simulation of proposed designs in QCAPro
tool. Therefore, the novel designs improve the energy dissipation parameters such as mean leakage energy dissipation, mean switching energy dissipation and total energy dissipation 75, 11.28 and 82.19% in comparison with the most robust design in existing.
DEFECT ANALYSIS OF QUANTUM-DOT CELLULAR AUTOMATA COMBINATIONAL CIRCUIT USING ...IAEME Publication
CMOS technology has achieved the device dimension in the nanometer range. Beyond this CMOS technology is the QCA (Quantum-dot Cellular Automata). Due to nanoscale defects may occur in this technology so in the consequences of it the faults will occur. This paper presents the defect analysis of QCA basic devices like Majority Voter (MV), inverter. The defect analysis and its effects on the output of combinational circuit using Hardware Description Language for QCA (HDLQ) is presented in this paper.
The CMOS faces challenges related to the increment in leakage-current to power-consumption. QCA is a promising alternative to overcome these challenges successfully. On the other hand, reversible logic plays a significant role in quantum-computing. Keeping this technique in mind, a conservative-reversible flip flops and counter are explored here which will bring QCA and reversible computing together in a singleplatform. In synthesizing, a reversible-conservative-quantum-cellular-automata (R-CQCA) is proposed. The proposed D, T, JK and dual-edge master-slave flip-flops advocate an improvement of 20%, 46.6%,
50%, and 36.66% respectively than its counterpart in quantum-cost. Further, the 100% fault-coverage
by stuck-fault is framed in R-CQCA, which can be useful for a tester to maintain data-integrity. Also, the R-CQCA layout is implemented in QCA, which achieve some parameters such as cell-complexity of 177, leakage-energy-dissipation of 0.1055 eV, and size of 0.24 mm2. Moreover, R-CQCA is better than FRG, RM, PPRG and MX-cqca regarding QCA-primitives are reported here.
Design and Development of 4-Bit Adder Programmable QCA Design using ALU Techn...IRJET Journal
This document discusses the design and development of a 4-bit adder using quantum-dot cellular automata (QCA) and an arithmetic logic unit (ALU) technique. QCA is a nano-technology that can be used to build digital circuits with lower power consumption compared to CMOS. The author proposes using ALU techniques with QCA cells to implement a 4-bit adder circuit. This includes using reversible logic and arithmetic units, multiplexers, and cascading 1-bit adders. Simulations show that a 4-bit adder implemented with QCA cells using an ALU technique has advantages like lower area and transistor count with no propagation delay compared to traditional CMOS designs.
Neural Network Modeling for Simulation of Error Optimized QCA Adder CircuitIRJET Journal
This document proposes a Hopfield neural network model (PNN) to design an error-optimized quantum-dot cellular automata (QCA) adder circuit. The PNN model analyzes how the polarization at the output of a single-bit full adder can help build larger, more complex QCA adder circuits. It also identifies the most robust and reliable single-bit full adder design. The PNN model measures the efficiency and accuracy of polarization at each output of the adder circuit. It demonstrates the PNN model's ability to design a reliable and robust single-bit full adder circuit with optimized error and cost compared to other simulation techniques.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...IRJET Journal
This document describes the design and implementation of a low power 16-bit carry-lookahead adder using two-phase clocked adiabatic static CMOS (2PASCL) logic. 2PASCL circuits can recover energy stored at output nodes during state transitions, providing power savings over conventional CMOS. The authors designed inverters, NAND, NOR, XOR gates and 4, 8, 16-bit carry-lookahead adders using 2PASCL logic in Cadence. Simulation results showed the 2PASCL designs consumed less power than equivalent static CMOS designs. Layouts were also produced for the 4, 8, 16-bit adders. Power analysis confirmed the 2PASCL adders achieved significant
Similar to Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Environment (20)
The impact of quantum computing has been widely recognised in the engineering domain. The age of quantum computing has arrived, and with it comes the ability to easily solve exponential problems. This book is written by me to meet current academic demands. The book is designed to address the most important aspects of the subject of Quantum Computing. The publication of the book "Quantum Computing" is the culmination of numerous years of research and teaching in academia. It is given in a way that is straightforward to comprehend. The undergraduates, and graduate students may all benefit from reading this book. We have given our very best effort to bring you accurate book material.
The book explains the fundamentals of this topic in simple, straightforward language. The most efficient approach to go through this book is to grasp the underlying fundamental as well as mathematical concepts. The chapters are meant to stand on their own. This book is not intended to be theoretical; rather, it will serve to familiarise you with the fundamental of quantum computing, like applications, multiple-qubit systems, quantum state transformations, quantum gates and quantum circuits, tools for quantum computing, bell states, quantum Parallelism, quantum Algorithms: Shor’s Algorithm, Grover’s Algorithm, Quantum Hardware and software, Quantum Cryptography and Security, Quantum Error Rates and Quantum Noise, Quantum Fourier Transform, Quantum Machine Learning and so on.
The model questions and multiple-choice questions that are provided at the end of the book have been chosen to improve readers' understanding, as well as their performance in exams and key employment.
We warmly welcome and would be very appreciative of any comments or recommendations, that will help us enhance the overall quality of the book.
Dr. Neeraj Kumar Misra is an Associate Professor who teaches Information Theory and Coding. Some of his qualifications and accomplishments include: a Ph.D from VIT-AP University under a TEQIP-II fellowship, a postgraduate diploma in artificial intelligence and machine learning from NIT Warangle, three granted international patents, over 9 years of teaching and industry experience, 14 publications in SCI journals, and 325 citations on Google Scholar with an h-index of 11. He is a professional member of several organizations and serves on the editorial boards of multiple journals.
Efficient architecture for arithmetic designs using perpendicular NanoMagneti...VIT-AP University
As the process of scaling down continues at a rapid pace, there is a growing need for an alternative semiconductor device to replace CMOS. One of the alternatives that attracted a lot of attention is called nanomagnetic logic (NML). This is because NML delivers a high device density in addition to a non-volatility of stored information, beyond-CMOS technologies, and device work at room temperature. It is necessary to lower the circuit density and increase the speed of circuits like adders. Using emerging NML logic, we created a full-adder, and ripple carry adder (RCA) with a minimum area. As a result, the invented multilayer-based decimal design makes use of RCA, and full-adder, for innovative 3D topology. We used an NML framework built with perpendicular nanomagnetic (pNML) layers to simulate the characteristics of these devices. With the adder designs that have been offered the latency values are relatively low while performing exhaustive testing. Using pNML technology, a decimal adder has been constructed for the first time in the literature. In addition, simulations are carried out with the help of the Modelsim simulator. During the process of nanomagnetic designing consideration is given to both of these aspects as latency and area. To create an NML circuit, the tool MagCAD is employed. Results are better using the pNML environment-based full adder, RCA and decimal adder.
An in-depth study of the electrical characterization of supercapacitors for r...VIT-AP University
The Energy Storage System (ESS) is geared toward sophisticated systems with increased operating time for a variety of real-time applications such as an electric vehicle, a WSN (Wireless Sensor Network), a Capa bus, and so
on. Its primary focus is on supplying these kinds of systems with additional capacity in recent development, and
this will continue to be its primary focus. Because of their exceptionally high specific power, rapid charging, and
low ESR (Effective Series Resistance), electric double-layer (EDLC) capacitors or supercapacitors are encouraged
for use because they can be integrated more easily with battery technology that can be used in electric vehicles
and other electronic devices. The supercapacitor calls for a precise and accurate characterization in order to
facilitate the development of improved applications and more effective energy storage devices and technologies.
In this article, we studied various supercapacitor electrode components, electrolytic solutions, analogous circuit
models, electrical energy storage properties, and some real-time supercapacitor applications in the automotive,
manufacturing, construction, and consumer electronics industries. In addition, we have discussed on hybrid
material that was just recently developed with the goal of enhancing the conductivity and effectiveness of supercapacitors. Aside from this, we have discussed about the behaviour of supercapacitors in terms of how their behaviour is dependent on current and voltage with detailed analysis.
Agenda
1. Algorithm of Reading Scientific Research Article
2. Importance of ORCID ID
3. Benefit of ORCiD
4. Process of Connecting Scopus database to ORCiD iD
5. Registration of ORCiD iD Account
6. Scopus Database connected to ORCiD iD
7. BibTeX Entry to add all the publication at the same time in ORCiD iD
8. Process of importing BibTex into ORCiD Database
9. Using Bibtex include all the research article in one time
How to Calculate the H-index and Effective Response of ReviewerVIT-AP University
The document provides information on calculating the H-index and responding effectively to reviewer comments. It discusses that the H-index measures both the productivity and citation impact of a scientist's publications. The H-index is based on the scientist's most cited papers and the number of citations they received. The document also provides common phrases to use in responding to reviewer comments and thanks the reviewers for their feedback to strengthen the manuscript. Useful research tools and links are also listed.
Dr. Neeraj Misra presented on the importance of obtaining an ORCID ID. An ORCID ID is a unique identifier that helps link researchers to their work activities and publications. It helps distinguish researchers from others with similar names and allows researchers to add all of their publications at once to their profile. Obtaining an ORCID ID only takes a few minutes and helps give proper attribution and credit for research works.
Writing and Good Abstract to Improve Your Article QualityVIT-AP University
This document provides an overview of a presentation on writing good abstracts to improve article quality. The presentation covers topics like journal ranking, using Mendeley software, how to structure an article, how editors review papers, calculating citation metrics like cite score and h-index, and maintaining research profiles and accounts. Useful research tools and links are also listed. The presentation aims to provide guidance on writing strong abstracts and improving the overall quality of research publications.
Fundamental of Electrical and Electronics Engineering.pdfVIT-AP University
The document provides an introduction to Dr. Neeraj Kumar Misra, an Associate Professor in the Department of SENSE at VIT-AP University. It lists his qualifications including a Ph.D, publications, awards, projects completed, and professional memberships. It also outlines the content to be covered in the course on Fundamentals of Electrical and Electronics Engineering including topics like electric current, Ohm's law, circuit theory, and component symbols.
Content Addressable Memory Design in 3D pNML for Energy-Aware Sustainable Com...VIT-AP University
As the semiconductor industry strives for downsizing and high speed, it is confronted with
increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and lowpower
consumption. We introduced an optimal design of content addressable memory (CAM)
memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation
is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach
and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the ¯rst time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts.
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...VIT-AP University
For design methodology of CRC or cyclic redundancy check is very used technique for error checking and shows the transmission reliability we are using the HDLC block. HDLC block is very useful in data communication these block operated in data link layer. For design methodology of CRC is to generate the CRC polynomial using XOR’s gate and shift register these polynomial are implement on software Xilinx Plan Ahead 13.1 and verify for simulation result for random testing of CRC bit on receiver side same result are obtained to show that it is more reliable.
Sensor Energy Optimization Using Fuzzy Logic in Wireless Sensor NetworkingVIT-AP University
Wireless sensor networks is challenging in that it requires an enormous breadth of knowledge from an enormous variety of disciplines. A lot of study has been done to minimize the energy used in routing and number of protocols has been developed. These protocols can be classified as - Hierarchical, data centric, location based and Network flow protocols. In this paper, we are particularly focusing on hierarchical protocols. In such types of protocols, the energy efficient clusters are formed with a hierarchy of cluster heads. Each cluster has its representative cluster head which is responsible for collecting and aggregating the data from its respective cluster and then transmitting this data to the Base Station either directly or through the hierarchy of other cluster heads. Fuzzy logic has been successfully applied in various areas including communication and has shown promising results. However, the potentials of fuzzy logic in wireless sensor networks still need to be explored. Optimization of wireless sensor networks involve various tradeoffs, for example, lower transmission power vs. longer transmission duration, multi-hop vs. direct communication, computation vs. communication etc. Fuzzy logic is well suited for application having conflicting requirements. Moreover, in WSN, as the energy metrics vary widely with the type of sensor node implementation platform, using fuzzy logic has the advantage of being easily adaptable to such changes.
Novel conservative reversible error control circuits based on molecular QCAVIT-AP University
Quantum-dot cellular automata are a prominent part of the nanoscale regime. They
use a quantum cellular based architecture which enables rapid information process with high
device density. This paper targets the two kinds of novel error control circuits such as Hamming
code, parity generator and checker. To design the HG-PP (HG = Hamming gate, PP = parity
preserving), NG-PP (NG = new gate) are proposed for optimising the circuits. Based on the
proposed gates and a few existing gates, the Hamming code and parity generator and checker
circuits are constructed. The proposed gates have been framed and verified in QCA. The
simulation outcomes signify that their framed circuits are faultless. In addition to verification,
physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit
delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.
A Redundant Adder Architecture in Ternary Quantum-Dot Cellular AutomataVIT-AP University
Now researchers are moving toward emerging technologies to replace the
conventional CMOS technology. Quantum-dot cellular automata (QCA) are one of
them for high-performance computing circuits. Ternary QCA is one of the finest
research areas in this domain for replacement of binary logic. In this paper, we
proposed a new redundant adder architecture using Ternary QCA technology. Our proposed architecture has 233 numbers of cells with an area of 0.35 μm2. All the proposed ternary logic layouts are implemented in TQCA designer tool.
Concept and Algorithm of Quantum Computing During Pandemic Situation of COVID-19VIT-AP University
We are observing in this pandemic situation of COVID-19 the world in
very challenging and to solve this complex problem in quick time. Today, we are facing a difficult complex problem such as Coronavirus. This Coronavirus affects human life. Quantum computing is the only support that can give us quick results by processing the Coronavirus compound at high computation speed. Whatever present circuits in VLSI domain, we cannot perform the high-speed computation and not tackle the complex case as present COVID-19. In this article, we have been discussed about quantumcomputing era during the pandemic situation ofCOVID-19. Further, this paper presents fundamental about quantum properties such as superpo-
sition, entanglement, and quantum programming tools such as Qiskit (IBM), pyQuil
(Google), ProjectQ (ETH), Revkit, and RCvewier + . We have presented quantum
circuit and its decomposed circuit of such gates as Toffoli, Fredkin, Peres, and new
fault tolerance. In addition, we proposed algorithm as transforming cascade to the
quantumcircuitwhich is extended for verification based.All these concepts presented here will be very useful to researcher, academician, and industry person to tackle this
pandemic situation of COVID-19.
A Novel Parity Preserving Reversible Binary-to-BCD Code Converter with Testab...VIT-AP University
The reversible logic circuit is popular due to its quantum gates involved
where quantum gates are reversible and noted down feature of no information loss.
In this paper, parity preserving reversible binary-to-BCD code converter is
designed, and effect of reversible metrics is analyzed such as gate count, ancilla
input, garbage output, and quantum cost. This design can build blocks of basic
existing parity preserving reversible gates. The building blocks of the code converter
reversible circuit constructed on Toffoli gate based as well as elemental gate
based such as CNOT, C-V, and C-V+ gates. In addition, qubit transition analysis of
the quantum circuit in the regime of quantum computing has been presented. The heuristic approach has been developed in quantum circuit construction and the
optimized quantum cost for the circuit of binary-to-BCD code converter. Logic functions validate the development of quantum circuit. Moving the testability aim
are figured in the quantum logic circuit testing such as single missing gate and single missing control point fault.
Novel Robust Design for Reversible Code Converters and Binary Incrementer wit...VIT-AP University
This work, we employ computing around quantum-dot automata to
construct the architecture of the reversible code converters and binary incrementer. The code converter and binary incrementer are made up of Feynman gate and Peres
gate, respectively. We have presented the robust design of Ex-OR in QCA, which is used for the construction of code converters and binary incrementer. The layouts of proposed circuits were made using the primary elements such as majority gate, inverter, and binary wire. A novel binary-to-gray converter design offers 59% cell count reduction and 36% area reduction in primitives improvement from the
benchmark designs. Being pipeline of PG gate to construct the 1-bit, 2-bit, and 3-bit
binary incrementer, we can use this robust layout in the QCA implementation of binary incrementer. By the comparative result, it is visualized that the binary incrementer such as 1-bit, 2-bit, and 3-bit achieved 60.82, 60.72, and 64.79% improvement regarding cell count from the counterpart.
DESIGN OF MEDIAN FILTER IN QUANTUM-DOT CELLULAR AUTOMATA FOR IMAGE PROCESSING...VIT-AP University
This document summarizes a research paper that proposes a new design for a median filter using quantum-dot cellular automata (QCA). It uses a majority logic algorithm and one-hot encoding. For an input matrix of 9 numbers represented as 4-bit values, each column is processed independently by majority gates to determine the median value in 0.5 clock cycles. The proposed architecture scales to larger bit sizes while maintaining a constant delay of 0.5 clock cycles. Simulation results show the 1-bit median filter design occupies 0.05 μm2 and the proposed approach achieves better speed performance compared to other parameters as the bit size increases.
Low Power LC-Quadrature VCO with Superior Phase Noise Performance in 0.13 μmR...VIT-AP University
The presented work intends to encounter the challenge of optimizing frequency tracking
in the C-band WLAN spectrum, with a tuning range and phase noise (PN)
performance. A Quadrature Voltage Controlled Oscillator (QVCO) design in 130 nm
CMOS technology has been presented to cover the most sought WLAN/WiFi spectrum
of modern wireless systems, employing the current reuse technique and an
on-chip inductor implementation. To provide better compensation of LC losses at
reduced power dissipation, a cross-coupled structure combining NMOS and PMOS
has been used.We have run an extensive simulation using the industry-standard ADS
(Keysight technology) platform. The simulation study attributed to the superior phase
noise performance of − 160 dBc/Hz at 1 MHz (near f max) at a power dissipation
of 6.52 mW from 1.2 V supply. With the moderate voltage tuning range, the entire
desired frequency span of 5.400–5.495 GHz was obtained with a fairly high resolution
of 2.375 MHz/1 mV, which allows serving a larger crowd for this spectrum. A
fairly moderate VCO gain along with the obtained phase noise and power dissipation
provides a well-established Figure of Merit (FOM) of − 187 dB. Finally, a comparison
study in terms of power dissipation, phase noise, tuning range, voltage tuning,
and Kvco is performed to demonstrate that the provided work is considerably more
significant than traditional efforts.
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
Build the Next Generation of Apps with the Einstein 1 Platform.
Rejoignez Philippe Ozil pour une session de workshops qui vous guidera à travers les détails de la plateforme Einstein 1, l'importance des données pour la création d'applications d'intelligence artificielle et les différents outils et technologies que Salesforce propose pour vous apporter tous les bénéfices de l'IA.
Null Bangalore | Pentesters Approach to AWS IAMDivyanshu
#Abstract:
- Learn more about the real-world methods for auditing AWS IAM (Identity and Access Management) as a pentester. So let us proceed with a brief discussion of IAM as well as some typical misconfigurations and their potential exploits in order to reinforce the understanding of IAM security best practices.
- Gain actionable insights into AWS IAM policies and roles, using hands on approach.
#Prerequisites:
- Basic understanding of AWS services and architecture
- Familiarity with cloud security concepts
- Experience using the AWS Management Console or AWS CLI.
- For hands on lab create account on [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
# Scenario Covered:
- Basics of IAM in AWS
- Implementing IAM Policies with Least Privilege to Manage S3 Bucket
- Objective: Create an S3 bucket with least privilege IAM policy and validate access.
- Steps:
- Create S3 bucket.
- Attach least privilege policy to IAM user.
- Validate access.
- Exploiting IAM PassRole Misconfiguration
-Allows a user to pass a specific IAM role to an AWS service (ec2), typically used for service access delegation. Then exploit PassRole Misconfiguration granting unauthorized access to sensitive resources.
- Objective: Demonstrate how a PassRole misconfiguration can grant unauthorized access.
- Steps:
- Allow user to pass IAM role to EC2.
- Exploit misconfiguration for unauthorized access.
- Access sensitive resources.
- Exploiting IAM AssumeRole Misconfiguration with Overly Permissive Role
- An overly permissive IAM role configuration can lead to privilege escalation by creating a role with administrative privileges and allow a user to assume this role.
- Objective: Show how overly permissive IAM roles can lead to privilege escalation.
- Steps:
- Create role with administrative privileges.
- Allow user to assume the role.
- Perform administrative actions.
- Differentiation between PassRole vs AssumeRole
Try at [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
VARIABLE FREQUENCY DRIVE. VFDs are widely used in industrial applications for...PIMR BHOPAL
Variable frequency drive .A Variable Frequency Drive (VFD) is an electronic device used to control the speed and torque of an electric motor by varying the frequency and voltage of its power supply. VFDs are widely used in industrial applications for motor control, providing significant energy savings and precise motor operation.
Generative AI Use cases applications solutions and implementation.pdfmahaffeycheryld
Generative AI solutions encompass a range of capabilities from content creation to complex problem-solving across industries. Implementing generative AI involves identifying specific business needs, developing tailored AI models using techniques like GANs and VAEs, and integrating these models into existing workflows. Data quality and continuous model refinement are crucial for effective implementation. Businesses must also consider ethical implications and ensure transparency in AI decision-making. Generative AI's implementation aims to enhance efficiency, creativity, and innovation by leveraging autonomous generation and sophisticated learning algorithms to meet diverse business challenges.
https://www.leewayhertz.com/generative-ai-use-cases-and-applications/
Design and optimization of ion propulsion dronebjmsejournal
Electric propulsion technology is widely used in many kinds of vehicles in recent years, and aircrafts are no exception. Technically, UAVs are electrically propelled but tend to produce a significant amount of noise and vibrations. Ion propulsion technology for drones is a potential solution to this problem. Ion propulsion technology is proven to be feasible in the earth’s atmosphere. The study presented in this article shows the design of EHD thrusters and power supply for ion propulsion drones along with performance optimization of high-voltage power supply for endurance in earth’s atmosphere.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Digital Twins Computer Networking Paper Presentation.pptxaryanpankaj78
A Digital Twin in computer networking is a virtual representation of a physical network, used to simulate, analyze, and optimize network performance and reliability. It leverages real-time data to enhance network management, predict issues, and improve decision-making processes.
Redefining brain tumor segmentation: a cutting-edge convolutional neural netw...IJECEIAES
Medical image analysis has witnessed significant advancements with deep learning techniques. In the domain of brain tumor segmentation, the ability to
precisely delineate tumor boundaries from magnetic resonance imaging (MRI)
scans holds profound implications for diagnosis. This study presents an ensemble convolutional neural network (CNN) with transfer learning, integrating
the state-of-the-art Deeplabv3+ architecture with the ResNet18 backbone. The
model is rigorously trained and evaluated, exhibiting remarkable performance
metrics, including an impressive global accuracy of 99.286%, a high-class accuracy of 82.191%, a mean intersection over union (IoU) of 79.900%, a weighted
IoU of 98.620%, and a Boundary F1 (BF) score of 83.303%. Notably, a detailed comparative analysis with existing methods showcases the superiority of
our proposed model. These findings underscore the model’s competence in precise brain tumor localization, underscoring its potential to revolutionize medical
image analysis and enhance healthcare outcomes. This research paves the way
for future exploration and optimization of advanced CNN models in medical
imaging, emphasizing addressing false positives and resource efficiency.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Mechanical Engineering on AAI Summer Training Report-003.pdf
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Environment
1. International Journal of Nanoelectronics and Materials
Volume 12, No. 2, Apr 2019 [205-220]
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in
QCA Environment
Bandan Bhoi1, Neeraj Kumar Misra2*, Lafifa Jamal3 and Manoranjan Pradhan4
1, 4Department of Electronics and Telecommunication Engineering, Veer Surendra Sai University of
Technology, Burla, India.
2Department of Electronics and Communication Engineering, Bharat Institute of Engineering and
Technology, Hyderabad, India.
3Department of Robotics and Mechatronics Engineering, University of Dhaka, Dhaka, Bangladesh.
Received 3 April 2018, Revised 23 December 2018, Accepted 31 December 2018
ABSTRACT
Recently, Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an
enormous benefit over CMOS based logic circuit. As a promising technology for
Nanoelectronics computing, reversible-QCA has gained more and more attention from
researchers around the world. In this paper, a reversible authenticator circuit based on
QCA was implemented. This article presents a Nano-authenticator circuit to verify the
authenticated and unauthenticated inputs. The proposed QCA designs have been
implemented in a different manner from existing designs, which are primarily based on a
coplanar design approach. The efficiency of QCA design has been investigated based on
parameters such as cell count, area, and latency. Furthermore, missing an additional cell
defect of the reversible authenticator has been analyzed, and covers the fault tolerance of
60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA
environment achieves 76.35% area, 12.5% cell count and 95.55% average energy
dissipation improvement as compared to the existing layout. Moreover, the new reversible
authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison
with the previous state-of-art design.
Keywords: Reversible Authentication, Quantum Computing, Minimal, Cellular
Automata, Low Cost.
1. INTRODUCTION
Quantum-dot Cellular Automata (QCA) is a nanoscale-based computing paradigm which does
not use transistors. QCA circuits are high speed, high-density circuits which consume lower
power compared to Complementary Metal-Oxide-Semiconductor (CMOS) logic circuits [1].
CMOS has reached its short channel effect and scaling due to Quantum Mechanical Effect (QME)
[2]. Increase in energy dissipation of the CMOS circuit is driven by size and materials. Many
Nanocircuits based on QCA has been synthesized for low power and high density [3]. The
physical implementation of QCA was first proposed in 1993 and fabricated in 1997 [4]. Energy
dissipation is an important factor for the development of digital logic circuit [5].
Nowadays, using advance Nanodevices, the circuits dissipate very low energy. However, as the
density of devices increases exponentially, the energy dissipation will play an important role in
the next decades. Quantum technology has diverse applications in the domain of
Nanoelectronics. Information processing in which there is no loss of data is known as reversible
* Corresponding Author: neeraj.mishra3@gmail.com
2. Bandan Bhoi, et al. / Low-Cost Synthesis Approach for Reversible Authenticator…
206
computing and the logic gates that execute such task are called quantum logic gates [6].
Reversible and quantum computing are linked to each other because, in quantum technology, all
computation must be reversible [7]. Quantum logic information is made of qubit or quantum bit.
Digital circuit is constructed from logic gates, whereas quantum computing design is
constructed from elemental quantum gates (Controlled-V, Controlled-V+, and CNOT) [8].
This paper aims to synthesis low-cost reversible authenticator based solely on the Feynman
Gate (FG). The achievement is based on the comparison of the extracted results with existing
works. The achievement of this work is to consider both quantum circuit and physical
foreground implementation of authenticator circuit in QCA. Thus, the proposed authenticator
layout in QCA improves cost and area, which eventually improves the system reliability of the
latest Nanoelectronics devices. While less amount of work for circuit reliability analysis such as
a missing cell, additional cell and cell displacement based defect have been available in the
literature, there is a lack of robust architecture on their parameters such as complexity, area,
and latency. Quantum-dot Cellular Automata Probabilistic (QCAPro) tool is a robust tool which
estimates the energy dissipation of QCA Design. In this work, the QCAPro tool was used to
calculate the energy estimation results for the proposed reversible authentication circuit. In
addition, this study also focuses on understanding the reliability concern in QCA with focus on
missing cell defect, additional cell defect, and displacement.
Following are the achievements of the proposed work:
A low-cost reversible authentication circuit in QCA environment for Nanocomputing
application was designed.
The correct fault pattern of reversible authenticator circuit based on the single and
additional missing cell defects in QCA architecture was estimated.
The energy dissipation parameters of reversible authenticator circuit were estimated.
The displacement tolerance of reversible authenticator in QCA for loosely and tightly
coupled cells was analyzed.
The displacement tolerance based analysis of loosely coupled cell up to 1nm in the QCA
authenticator circuit was applied.
The cell position success rate of authenticator circuit for tightly coupled cell up to 4.8nm
was estimated.
The rest of the paper is arranged as follows. In Section 2, we review the preliminary related to
this paper. Section 3, deals with the related work. In Section 4, we implement the Feynman gate
in QCA. Framework for authentication matching process is explained in Section 5. Fault
detection in authenticator circuit is discussed in Section 6. Energy dissipation is calculated in
Section 7. Section 8 deals with the performance parameter analysis. Finally, we conclude the
work in Section 9.
2. PRELIMINARIES
Some of the terminologies related to reversible logic and QCA computing are presented in this
section. All the terminologies have been reviewed in [9-12].
2.1 Reversible Computing
Definition 2.1: Boolean operation is reversible if every output logic patterns uniquely map to
an input logic patterns and vice versa.
3. International Journal of Nanoelectronics and Materials
Volume 12, No. 2, Apr 2019 [205-220]
207
Definition 2.2: A reversible network consists of reversible gates and each reversible gate based
on Controlled V, Controlled V+, and Controlled NOT. The numbers of elemental quantum gates
utilized in the quantum circuit are used for calculation of the quantum cost.
Definition2.3: A non-reversible Boolean operation F: {0,1}p {1,1}q, can also be formed by
reversible with the addition of input lines noted as constant input/ ancilla inputs.
Definition2.4: Toffoli Gate (TG) has three inputs and three outputs. First and second bits are
known as control bits that are unchanged by the quantum wire. The third bit is mapped to the
control gate. It changes the qubit, if the control bits are fixed to 1, else the qubits are unchanged.
Example 2.1: Toffoli gate: A 3×3 TG is also CCNOT gate. This gate passes the first two inputs in
the output side. In Figure 1, dot is a control point and Ex-OR is a control gate if all the control
points are set to 1, then control gate changes the bits.
Example 2.2: Reversible 3×3 Toffoli gate output is P=A, Q=B, and R=(ABC). It can generate
NAND, OR, AND and NOR on the output node. Reversible Peres gate outputs are P=A, Q= (AB)
and R=(ABC). It can generate AND, NOR, XOR, and NOT. The quantum representation of
cascaded reversible Toffoli Gate and Peres Gate is shown in Figure 1
Control
Target
Control
Target
Target
Control
Control
TG PG
Figure 1. Quantum circuit of TG and PG.
2.2 QCA Computing
The VLSI strategy for circuit design is utilized for CMOS technology. These technologies suffer
from high leakage current, limitation of feature size, and scaling limitation [10]. The
experimental set-up view of QCA cell is shown in Figure 2a. The QCA technology is one of the
newer logic computing with low energy dissipation and high speed. QCA cell is composed of 4
dots with 2 electrons. Two possible polarization states are used, such as P=+1 and P=-1, for
binary 1 and binary 0 respectively, for storing information in the cell (In Figure 2b). Majority
gate, fan-out, and inverter design in QCA are depicted in Figures 2c, 2d, and 2e, respectively.
QCA design requires a clocking to flow and control the data [11]. The appropriate electric field is
required to change the potential barriers [12]. Clock zones activate the data flow computation in
a sequential manner [13]. All clocks zones are specified by Switch, Hold, Release and Relax,
which is shown in Figure 3. The rotated cells concept in QCA technology is more stable. The
advantage of using rotated cells is that wire crossing is possible in the same layer, which
requires less area and is more reliable. The rotated and non-rotated cells based wires can cross
each other without affecting their logic values in the same plane. If there are no rotated cells in
the QCA design, then the crossing of wires can be done using only rotated cells in multilayer.
This multilayer crossing leads to more area and less reliability of the design.
(a) (b)
Electrometer
Input
A= 1
Input
C= 1
Input
B= 1
Polarization = -1
(Binary 0)
Polarization = +1
(Binary 1)
1
23
4
ElectronQuantum-dot
Tunnel Junction
(a) (b)
Electrometer
Input
A= 1
Input
C= 1
Input
B= 1
Polarization = -1
(Binary 0)
Polarization = +1
(Binary 1)
1
23
4
ElectronQuantum-dot
Tunnel Junction
(a) (b)
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(c) (d)
(e)
Figure 2. QCA basic: (a) Experimental view of QCA (b) Polarization value in QCA cell (c) Majority gate (d)
Fan-out (e) Inverter.
Clock 0
Clock 1
Clock 2
Clock 3
Time
Signal Propagation
Figure 3. QCA Clocking mechanism.
2.3 QCA Defect
QCA defect has attracted considerable attention in current research for Nanoscale based testing,
because of the high possibility of the presence of defects in Nanoscale. These defects are tackled
by a testing engineer, which may occur in the chemical synthesis phase. The defect tolerance
value usually indicates the reliability percentage of QCA design. Defects can be categorized as
cell misalignment, cell displacement, cell missing, extra cell and rotated cells [14]. Some of the
QCA defects are described below:
Cell misalignment and displacement-based defect: Each cell in right place structures is
shown in Figure 4 (a). Figure 4 (b) and 4 (c) show the QCA defects for the cell incorrectly placed
in the position. From the illustration in Figure 4 (b) and 4 (c), it can be said that adjacent cell’s
distance wrongly placed, the design shows the incorrect logic function.
Cell missing based defect: In Figure 4 (d) cell missing defect have been shown. This kind of
defect can be illustrated as when the particular cell position is missing.
Extra cell-based defect: Extra cell makes the design denser because a considerable space is
required to place the cell. Also, the functionality of the design is incorrect since the extra cell is
randomly found. Figure 4 (e) shows the extra cell model structure.
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Drive cell rotated based defect: In Figure 4 (f), the drive cell is rotated. The model structure is
incorrectly conFigured, with drive, and cell rotated. Then, the design results in incorrect
functionality.
d d
Cell
missing
Cell
displacement
Cell
misaligment Extra cell
Extra cell
Drive cell
rotated
(a) (b) (c) (d) (e) (f)
Each cell in
right place
Figure 4. QCA fault (a) no fault in majority gate (b) cell displacement fault (c) cell misalignment fault (d)
cell missing fault (e) extra cell fault (f) drive cell rotated fault.
3. RELATED WORK
Due to the advancement in Nanoelectronics technology, high-speed Nanoelectronics circuits are
becoming more popular [15]. Parameters of reversible-QCA such as garbage output, quantum
cost, complexity, area, and latency are used for optimization of the circuits [16]. However, their
testing of Nanocircuit is still a major concern [17]. Missing cell defect, additional cell defect, and
displacement cell defect are common faults in QCA terminology. In order to increase the circuit
reliability, testing is performed in the proposed authenticator circuit. The authors in [18] have
designed data path selector using multiplexer and demultiplexer as an innovative way of path
selector. In addition, the design has been implemented in QCA. Three modules such as
demultiplexer, crossbar, and parallel-to-serial converter implement the structure of Nano-
router [19]. In this work, the proposed design was realized by QCA technology using a four-
clock zone scheme.
The existing work in [20] has presented reversible authentication using Fredkin gate. In [20]
the quantum cost for authentication using Fredkin and NOT gate have mentioned [6]. In [21], a
reversible fingerprint authenticator QCA design was implemented to verify the authentication
results. However, no testability features for authentication originated from the state-of-art
technology. The existing QCA layout of authenticator requires more cell count, latency and area.
By considering all these issues, the proposed design has been optimized in a more efficient way
by novel architecture and testability feature. The design, presented in this work, have been
implemented by Feynman Gate (FG), which results in low QCA primitives such as area, cell
count, and latency. The proposed QCA architecture of authenticator circuit has a less cell count,
area, and latency than existing approach while providing the same circuit functionality.
4. REVERSIBLE FEYNMAN GATE (FG)
A
B BAQ
AP
Figure 5. Quantum circuit of FG.
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(a) (b)
Figure 6. FG: (a) Cell layout (b) Simulation result.
In the synthesize of the authenticator, the FG was utilized as the building block. It maps bijective
maps of inputs to outputs as (A, B) to . The quantum circuit of the FG is shown in
Figure 5. The FG in QCA layout uses eleven cell count and obtained the output Q after 0.5 clock
cycle delay. Figure 6 presents the layout and simulation results of FG. Bistable-approximation
simulation engine was selected to simulate the FG layout result presents in Figure 6b. To
measure the effectiveness of layout in QCA, the existing layout in [20, 21] was considered. Table
1 presents the comparative results based on QCA primitives such as number of the inverters,
number of majority gates, cell count, area and latency. The proposed authentication circuit in
QCA only uses two clock zones. The QCA layout consumes only 11 cells, 0.0174µm2 area, and 0.5
latency. Table 1 shows the comparative results based on the proposed design and existing
designs.
Table 1 New cell layout of utilizing gate in authentication against prior cell layout
Cell layout Majority Inverter Complexity Cell area Total Area
(µm2)
Latency
Proposed 1 1 11 0.0035 0.0174 0.5
[20] 3 2 37 0.0148 0.0352 0.75
[21] 6 2 88 0.035 0.098 0.75
% improvement w.r.to [20] 50% 70.27% 76.35% 50.56% 33.33%
% improvement w.r.to [21] 50% 87.5% 90% 82.24% 33.33%
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5. THE FRAMEWORK OF PROPOSED AUTHENTICATOR
Acquisition of
input
MatchingData base
Decision
Authenticated/
Unauthenticated
inputs
Figure 7. Block diagram of a typical authenticated verification system.
Authenticator matching is a system that determines the acquisition of inputs with a store input
accumulated in the database [21]. A complete block diagram of the authenticator matching
system is shown in Figure 7. In the authenticator matching system, the database is obtained in
the user collection phase. After that, the matching process takes place through the acquisition of
inputs. Such inputs must be processed in a matching block. After the processing of the inputs,
the decision block will be utilized with the template database. Finally, a result is obtained with
the logic bits to ensure the authenticity of the inputs.
5.1 Proposed Design and Simulation Results
(a) (b)
Figure 8. Working of authentication process: (a) authenticated inputs (b) unauthenticated inputs.
The proposed circuit is based on the reversible logic gates. Reversible FG and NOT gates are
utilized for the authentication circuit. Reversible FG is used and inputs are assigned to find the
authenticated output. The complete block diagram of this authentication approach is presented
in Figure 8.
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212
A
B
AP
BAQ
NOTCNOT
Figure 9. Synthesis of authenticator circuit with FG and NOT gate.
For the synthesis of the authenticator circuit, FG and NOT gates are utilized. The building block
of the authenticator circuit based on FG and NOT gate is shown in Figure 9. The output of the
authenticator logic circuit is obtained by the second output. It is analyzed that this circuit
requires an only two quantum cost.
(a) (b)
Figure 10. Authenticator Output: (a) Cell layout of authenticator circuit (b) Simulation result of the
authenticator circuit based on inputs A(00011011) and B(00011011).
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Stored
data
Input
data
If A=B authenticated output
If Aǂ B unauthenticated output
Q
Decision
output
unauthenticated output
(a) (b)
Figure 11. Unauthenticator Output: (a) Cell layout of authenticator circuit (b) Simulation result of the
unauthenticated circuit based on inputs A(11011011) and B(00100100).
Authenticator based on reversible gates has been implemented in QCA by using one inverter
(INV 1) and proposed Feynman gate in Figure 10(a). The authenticator design consists of 12
cells covering the footprint area of 0.12µm2. Simulation setting of the Bistable engine was used
to simulate the authenticator design. The authenticator circuit based on input A(00011011) and
stored data B(00011011) is shown in Figure 10(b). The other input A(11011011) and stored
data B(00100100) generate the unauthenticated output in a binary form as shown in Figure
11(a) and 11(b). The Q output is used to present the unauthenticated output. The two examples
are pointed in random cases and the test outputs represent the authenticated and
unauthenticated logic of the QCA design based on the FG and inverter gate. Authenticated and
unauthenticated inputs for the proposed circuits were analyzed, and the inputs patterns in two
cases were considered. The first case takes the input A as 11011011 and matches the stored
data B i.e. 11011011. In simulation result, Q output is 11111111. If there is no ‘0’ bit in Q, then A
is authenticated input. Figure 10(b) shows the results under inputs 11011011 and stored data
00100100. This QCA level circuit is presented in Figure 11(a). The unauthenticated outputs are
presented by simulation results of Figure 11(b). In simulation result, Q is 00000000. If any bit is
‘0’ in Q value then input A is considered as unauthenticated. In this case, A is unauthenticated
input.
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6. DEFECT ANALYSIS OF THE PROPOSED AUTHENTICATOR QCA LAYOUT
6.1 Missing and Additional Cell Defects in Proposed QCA Architecture
Figure 12. Cell deposition defects of reversible authentication circuit.
The missing and additional cell defects of faulty FG are depicted in Figure 12 where all cells are
numbered according to the coordinates. Missing cell defects are possible for all 12 numbers of
cells for the proposed QCA authenticated circuit. Similarly, 12 numbers of additional cell defects
are possible in the proposed layout. The functionality of the circuit is verified in presence of all
possible missing and additional cell defects in QCA Designer tool. The results are summarized in
Table 2 and Table 3. In both tables, the first column specifies the input test vectors for A and B.
On the other hand, only Q output is considered for fault tolerance analysis because it is the
decision output of the proposed layout of the authenticator. In Table 2, the value of Q is
specified for all possible missing cell faults from column no. 2 to 12. Similarly, in Table 3, Q
outputs are given for all additional cell-based defects. In both tables, the last column indicates
the correct patterns out of total patterns in presence of faults. The average correct patterns for
missing cell defects are 60.41%, whereas it is 75% for additional cell defects. The average fault
tolerance value is 67.70% (i.e. (60.41% + 75%) / 2) in presence of these defects. Therefore,
under single missing cell and additional cell defects, the probability of having the correct
decision output for the proposed authenticator is 67.70%.
Table 2 Fault tolerant analysis of missing cell defects
A
B
(1,2) (1,4) (1,5) (1,6) (2,2) (2,3) (2,4) (2,5) (3,1) (3,4) (4,1) (5,2) correct
patterns
0
0
0 1 1 1 0 1 1 1 0 1 0 0 7/12 =
58.33%
0
1
0 1 0 0 0 1 1 1 0 1 0 0 7/12 =
58.33%
1
0
0 1 0 0 1 1 1 1 0 1 0 0 6/12 = 50%
1
1
1 1 1 1 1 1 1 1 0 1 0 0 9/12= 75%
Avg. =60.41%
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Table 3 Fault tolerant analysis of additional cell defects
A
B
(1,1) (1,3) (2,1) (2,6) (3,2) (3,3) (3,5) (4,2) (4,3) (4,4) (5,1) (5,3) correct
patterns
0
0
1 1 0 1 0 1 1 0 1 1 0 1 8/12 = 75%
0
1
0 1 0 0 0 1 0 1 0 0 1 0 8/12 = 75%
1
0
0 1 0 0 0 1 0 1 0 0 1 0 8/12 = 75%
1
1
1 1 0 1 0 1 1 0 1 1 0 1 8/12= 75%
Avg. =75%
6.2 Displacement Tolerance for the Proposed Authenticator
Figure 13. Representation of Authenticator layout with nodes.
Besides missing cells and additional cells, the relative position of cells or cells displacement also
has some impact on the structure. Therefore, the fault tolerance of the displacement of cells
from its original position plays a vital role in the fabrication of error-free circuits. For the
analysis of displacement behaviour, the layout is described by using nodes as shown in Figure
13. The cells shown in the Figure are divided into two categories based on the connection with
the driver cell, i.e. loosely and tightly coupled cells. A cell is called loosely coupled if it is
connected to one or two cells, similarly if a cell is connected to more than two numbers of cells
is known as tightly coupled. The tightly coupled cells have a greater influence on the circuit than
do loosely coupled cells. The maximum displacement of the cells in all directions beyond which
the circuit will not perform correctly is reported in Table 4. In Table 4, displacement fault-
tolerance is measured for Q output. The average value of cell displacement fault-tolerance of
loosely coupled cells is 1nm. This value is 4.8nm for tightly coupled cells.
Table 4 Displacement tolerance of cells of the authenticator
Cell position Success rate
(nm)
Loosely coupled cell
3 A 2 5 7 8 B Q Avg.
0.8nm 1.6nm 0nm 0.3nm 0.2nm 1.3nm 0.2nm 3.6nm 1nm
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Cell position Success rate
(nm)
Tightly coupled cell
1 4 6 Avg.
14nm 0.5nm 0nm 4.8nm
7. ENERGY DISSIPATION ANALYSIS IN DIFFERENT TUNNELING LEVELS OF ENERGY
In order to measure the energy dissipation of new authentication circuits, QCAPro tool was used
to estimate the energy dissipations parameters. The energy dissipations parameters and the
thermal map were obtained by QCAPro tool after the successful simulation of QCA design. The
energy dissipation parameters are obtained for selection of energy level at a temperature of 2K,
as presented in Table 5. Further, the extracted parameters such as Avg. Switching Energy diss.,
Avg. Energy diss. of circuit, Avg. Leakage Energy diss. at three levels of tunnelling energy such as
0.5Ek, 1Ek, and 1.5Ek of the proposed design and existing designs are presented in Table 5. As
per the Table 5, it is shown that the newly authentication design dissipate 80.32% less Avg.
Switching Energy diss., 75.80% Avg. Energy diss. of the circuit, and 63.32% Avg. Leakage Energy
diss. at 0.5Ek. It is proved that we have attained an optimal value of power dissipation. It
ensures that the proposed design achieves the low lost Nanocircuits feature.
(a) (b)
Figure 14. Power dissipation map for the existing QCA architecture with 0.5Ek(a) Authentication circuit
#1 in [20] (b) Authentication circuit #2 in [21].
Figure 15. Power dissipation map for the proposed QCA authentication with 0.5Ek.
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Table 5 Energy dissipation analysis of authentication circuit in different tunneling levels of energy
Design
Avg Switching Energy
diss. (meV)
Avg Energy diss. (meV)
Avg Leakage Energy diss.
(meV)
0.5Ek 1Ek 1.5Ek 0.5Ek 1Ek 1.5Ek 0.5Ek 1Ek 1.5Ek
Proposed
0.0055
5
0.0046
0
0.0038
5
0.0105
3
0.0167
1
0.0234
6
0.0049
8
0.0121
1
0.0196
1
[20]
0.0282
1
0.0238
6
0.0199
6
0.0417
9
0.0614
0
0.0842
1
0.0135
8
0.0375
4
0.0642
6
[21]
0.1258
5
0.1108
6
0.0960
3
0.1503
3
0.1857
9
0.2310
9
0.0244
8
0.0749
3
0.1350
6
%
Improveme
nt w.r.to
[20]
80.32 80.72 80.71 75.80 72.78 72.14 63.32 67.74 69.22
%
Improveme
nt w.r.to
[21]
95.55 95.85 95.99 92.99 91.10 89.88 79.65 83.79 85.48
In the dissipation map of existing authentication circuit in [20, 21], the lighter cells dissipate
less energy and darker cells dissipate higher energy, which is shown in Figures. 14 and 15.
These thermal maps were obtained after the simulation of QCA design by the QCAPro tool. The
energy dissipation parameters of the existing QCA authentication [20, 21] and proposed circuit
in with 0.5Ek is shown in Table 5. The power dissipation map of the proposed authentication is
measured in standard tunnelling energy levels at 0.5Ek. According to Figure 15, it is observed
that the presented authentication thermal have fewer darker cells (3 cells out of 12) to ensure
less energy dissipation.
8. PERFORMANCE PARAMETER COMPARISON
Performance comparison is a key parameter to check the synthesis of the circuit. The
implemented design in [20] requires six quantum cost. Existing design based on Fredkin and
inverter gate introduces delay as per the counting of the quantum gate in the quantum circuit.
According to the comparison Table 6, the new design for the authenticator circuit utilizes FG,
which has less cell count, area, and latency as compared to the state-of-art designs. The
proposed design of reversible authentication in QCA framework benefits from a low cost related
to QCA. It is worth studying that low latency corresponds to less cell count and crossover. The
comparison of the new and prior circuit can be evaluated easily with the support of
performance analysis of authenticator circuit in Table 6. From Table 6, it is clear that the
proposed design latency, total area, cell area are 33.33%, 74.61%, and 88.48% respectively, as
compared to the existing design in [20, 21]. Therefore, after comparing all the existing designs
in [20, 21], it is noticeable that the performance of proposed authenticator QCA layout with a
feature in QCA primitives gives the cost-efficient approach. To determine the overall
performance of the authenticator designs, the Cost=Latency2× Total area is also shown in Table
6 below.
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Table 6 Performance comparison analysis of the authenticated circuit
9. CONCLUSION
The important application of authenticator circuit is the information security. In this article, the
robust architecture of reversible authenticator was proposed for QCA environment. Total area,
latency and cost analysis of new architecture and state-of-art circuits, introduced in this paper,
demonstrate that our methodology achieves superior results as far as latency, total area, cell
area, and cost are concerned. The article has also presented methods such as missing cell
defects, and additional cell defects into a testable Nano-authentication circuit and
experimentally presented 60.41% and 75% correct patters. Moreover, the displacement
tolerance of the proposed authenticator in QCA was analyzed and found that the tightly coupled
cells have a greater influence on the circuit compared to the loosely coupled. The robustness of
proposed authenticator circuit in QCA was examined in terms of missing cell defect, additional
cell defect, and displacement defect. The proposed Feynman-gate-based synthesis of the
authentication circuit consume 75.80% less avg. switching energy dissipation., and 63.32% avg.
energy dissipation, compared to its state-of-art designs counterpart. The future direction of this
work is to work with the HDL approach for fault testing, which will cover maximum fault
tolerance capability based on software simulation and synthesis method [1, 22].
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(Clock
cycle
delay)
Total
area in
µm2
Cell
area in
µm2
Area
usage
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% Improvement
w.r.to [21]
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