Now researchers are moving toward emerging technologies to replace the
conventional CMOS technology. Quantum-dot cellular automata (QCA) are one of
them for high-performance computing circuits. Ternary QCA is one of the finest
research areas in this domain for replacement of binary logic. In this paper, we
proposed a new redundant adder architecture using Ternary QCA technology. Our proposed architecture has 233 numbers of cells with an area of 0.35 μm2. All the proposed ternary logic layouts are implemented in TQCA designer tool.
An Efficient Construction of Online Testable Circuits using Reversible Logic ...ijsrd.com
The vital for many safety critical applications is the testable fault tolerant system. Due to its less heat dissipating characteristics, the reversible logic gaining interest in the recent times. Any Boolean logic function can be implemented using reversible gates. The credential part of the paper proposes a technique to convert any reversible logic gate to a testable gate that is also reversible. The resultant reversible testable gate can detect online any single bit errors that include Single Stuck Faults and Single Event Upsets S. Karp et.al. The proposed technique is illustrated using an example that converts a reversible decoder circuit to an online testable reversible decoder circuit.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
In this paper, we propose a new technique for implementing a low power high speed multiplier based on Sleepy Stack Technique and consisting of
minimum number of transistors. Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). An 4 bit x 4 bit
multiplier has also been implemented using the design of only using basic combinational circuits and its performance has been analyzed and
compared with similar multipliers designed with peer combinational design available in literature. The explored method of implementation achieves
a high speed low power design for the multiplier. Simulated results indicate the superior performance of the proposed technique over conventional
CMOS multiplier. Detailed comparison of simulated results for the conventional and present method of implementation is presented.
An Efficient Construction of Online Testable Circuits using Reversible Logic ...ijsrd.com
The vital for many safety critical applications is the testable fault tolerant system. Due to its less heat dissipating characteristics, the reversible logic gaining interest in the recent times. Any Boolean logic function can be implemented using reversible gates. The credential part of the paper proposes a technique to convert any reversible logic gate to a testable gate that is also reversible. The resultant reversible testable gate can detect online any single bit errors that include Single Stuck Faults and Single Event Upsets S. Karp et.al. The proposed technique is illustrated using an example that converts a reversible decoder circuit to an online testable reversible decoder circuit.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
In this paper, we propose a new technique for implementing a low power high speed multiplier based on Sleepy Stack Technique and consisting of
minimum number of transistors. Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). An 4 bit x 4 bit
multiplier has also been implemented using the design of only using basic combinational circuits and its performance has been analyzed and
compared with similar multipliers designed with peer combinational design available in literature. The explored method of implementation achieves
a high speed low power design for the multiplier. Simulated results indicate the superior performance of the proposed technique over conventional
CMOS multiplier. Detailed comparison of simulated results for the conventional and present method of implementation is presented.
Digital Electronics Most Essential and Frequently Asked Interview Questionsiottrainingts
It is a very important and a common subject for electrical, electronics & Instrumentation Engineering student. It deals with the theory & practical knowledge of digital system and how they are implemented in various digital instruments.
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
Design and Simulation of a Modified Architecture of Carry Save AdderCSCJournals
This paper presents a technology-independent design and simulation of a modified architecture of the Carry-Save Adder. This architecture is shown to produce the result of the addition fast and by requiring a minimum number of logic gates. Binary addition is carried out by a series of XOR, AND and Shift-left operations. These operations are terminated with a completion signal indicating that the result of the addition is obtained. Because the number of shift operations carried out varies from 0 to n for n-bit addends, a behavioral model was developed in which all the possible addends having 2- to 15-bits were applied. A mathematical model was deducted from the data and used to predict the average number of shift required for standard binary numbers such as 32, 64 or 128-bits. 4-bit prototypes of this adder were designed and simulated in both synchronous and asynchronous modes of operation.
In digital logic and computing, a counter is a device which stores the number of times a particular event or process has occurred, often in relationship to a clock signal. CMOS devices are designed for high noise immunity and low static power consumption. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET to not conduct, while a low voltage on the gate causes the reverse. This arrangement greatly reduces power consumption and heat generation .Finally we proposed counter using SRAM model, provides the best resolution, high output current and good output-input current linearity.
LOW POWER-AREA GDI & PTL TECHNIQUES BASED FULL ADDER DESIGNScscpconf
Full adder circuit is functional building block of micro processors, digital signal processors or any ALUs. In this paper leakage power is reduced by using less number of transistors with the techniques like GDI (Gate Diffusion Input) and PTL (Pass Transistor Logic) techniques. In this paper 3 designs have been proposed of low power 1 bit full adder circuit with 10Transistors ( using PTL multiplexer) , 8 Transistor
(by using NMOS and PMOS PTL devices), 12Transistors (6Transistors to generate carry using GDI technique and 6Transistors to generate sum using tri state inverters).
These circuits consume less power with maximum of 73% power saving com-pare to conventional 28T design. The proposed circuit exploits the advantage of GDI technique and
pass transistor logic, and sum is generated by tri state inverter logic in all designs. The entire simulations have been done on 180nm single n-well CMOS bulk technology, in virtuoso platform of cadence tool with the supply voltage 1.8V and frequency of 100MHz.
Low power area gdi & ptl techniques based full adder designscsandit
Full adder circuit is functional building block of micro processors, digital signal processors or
any ALUs. In this paper leakage power is reduced by using less number of transistors with the
techniques like GDI (Gate Diffusion Input) and PTL (Pass Transistor Logic) techniques. In this
paper 3 designs have been proposed of low power 1 bit full adder circuit with 10Transistors
( using PTL multiplexer) , 8 Transistor
(by using NMOS and PMOS PTL devices), 12Transistors (6Transistors to generate carry using
GDI technique and 6Transistors to generate sum using tri state inverters).
These circuits consume less power with maximum of 73% power saving com-pare to
conventional 28T design. The proposed circuit exploits the advantage of GDI technique and
pass transistor logic, and sum is generated by tri state inverter logic in all designs.
The entire simulations have been done on 180nm single n-well CMOS bulk technology, in
virtuoso platform of cadence tool with the supply voltage 1.8V and frequency of 100MHz.
DESIGN AND IMPLEMENTATION OF BIT TRANSITION COUNTERcsijjournal
In today’s VLSI system design, power consumption is gaining more attention as compared to performance and area. This is due to battery life in portable devices and operating frequency of the design. Power consumption
mainly consists of static power, dynamic power, leakage power and short circuit power. Dynamic power is dominant among all which depends on many factors viz. power supply, load capacitance and frequency. Switching
activity also affects dynamic power consumption of bus which is determined by calculating the number of bit transitions on bus. The purpose of this paper is to design a bit transition counter which can be used to calculate the
switching activity of the circuit nodes. The novel feature is that it can be inserted at any node of the circuit, thus helpful for calculating power consumption of bus.
Design of Complex Adders and Parity Generators Using Reversible GatesIJLT EMAS
This paper shows efficient design of an odd and even parity generator, a 4-bit ripple carry adder, and a 2-bit carry look ahead adder using reversible gates. Number of reversible gates used, garbage output, and percentage usage of outputs in implementing each combinational circuit is derived. The CLA used 10 reversible gates with 14 garbage outputs, with 50% percentage performance usage.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
The impact of quantum computing has been widely recognised in the engineering domain. The age of quantum computing has arrived, and with it comes the ability to easily solve exponential problems. This book is written by me to meet current academic demands. The book is designed to address the most important aspects of the subject of Quantum Computing. The publication of the book "Quantum Computing" is the culmination of numerous years of research and teaching in academia. It is given in a way that is straightforward to comprehend. The undergraduates, and graduate students may all benefit from reading this book. We have given our very best effort to bring you accurate book material.
The book explains the fundamentals of this topic in simple, straightforward language. The most efficient approach to go through this book is to grasp the underlying fundamental as well as mathematical concepts. The chapters are meant to stand on their own. This book is not intended to be theoretical; rather, it will serve to familiarise you with the fundamental of quantum computing, like applications, multiple-qubit systems, quantum state transformations, quantum gates and quantum circuits, tools for quantum computing, bell states, quantum Parallelism, quantum Algorithms: Shor’s Algorithm, Grover’s Algorithm, Quantum Hardware and software, Quantum Cryptography and Security, Quantum Error Rates and Quantum Noise, Quantum Fourier Transform, Quantum Machine Learning and so on.
The model questions and multiple-choice questions that are provided at the end of the book have been chosen to improve readers' understanding, as well as their performance in exams and key employment.
We warmly welcome and would be very appreciative of any comments or recommendations, that will help us enhance the overall quality of the book.
Cost-effective architecture of decoder circuits and futuristic scope in the e...VIT-AP University
The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.
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Digital Electronics Most Essential and Frequently Asked Interview Questionsiottrainingts
It is a very important and a common subject for electrical, electronics & Instrumentation Engineering student. It deals with the theory & practical knowledge of digital system and how they are implemented in various digital instruments.
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
Design and Simulation of a Modified Architecture of Carry Save AdderCSCJournals
This paper presents a technology-independent design and simulation of a modified architecture of the Carry-Save Adder. This architecture is shown to produce the result of the addition fast and by requiring a minimum number of logic gates. Binary addition is carried out by a series of XOR, AND and Shift-left operations. These operations are terminated with a completion signal indicating that the result of the addition is obtained. Because the number of shift operations carried out varies from 0 to n for n-bit addends, a behavioral model was developed in which all the possible addends having 2- to 15-bits were applied. A mathematical model was deducted from the data and used to predict the average number of shift required for standard binary numbers such as 32, 64 or 128-bits. 4-bit prototypes of this adder were designed and simulated in both synchronous and asynchronous modes of operation.
In digital logic and computing, a counter is a device which stores the number of times a particular event or process has occurred, often in relationship to a clock signal. CMOS devices are designed for high noise immunity and low static power consumption. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET to not conduct, while a low voltage on the gate causes the reverse. This arrangement greatly reduces power consumption and heat generation .Finally we proposed counter using SRAM model, provides the best resolution, high output current and good output-input current linearity.
LOW POWER-AREA GDI & PTL TECHNIQUES BASED FULL ADDER DESIGNScscpconf
Full adder circuit is functional building block of micro processors, digital signal processors or any ALUs. In this paper leakage power is reduced by using less number of transistors with the techniques like GDI (Gate Diffusion Input) and PTL (Pass Transistor Logic) techniques. In this paper 3 designs have been proposed of low power 1 bit full adder circuit with 10Transistors ( using PTL multiplexer) , 8 Transistor
(by using NMOS and PMOS PTL devices), 12Transistors (6Transistors to generate carry using GDI technique and 6Transistors to generate sum using tri state inverters).
These circuits consume less power with maximum of 73% power saving com-pare to conventional 28T design. The proposed circuit exploits the advantage of GDI technique and
pass transistor logic, and sum is generated by tri state inverter logic in all designs. The entire simulations have been done on 180nm single n-well CMOS bulk technology, in virtuoso platform of cadence tool with the supply voltage 1.8V and frequency of 100MHz.
Low power area gdi & ptl techniques based full adder designscsandit
Full adder circuit is functional building block of micro processors, digital signal processors or
any ALUs. In this paper leakage power is reduced by using less number of transistors with the
techniques like GDI (Gate Diffusion Input) and PTL (Pass Transistor Logic) techniques. In this
paper 3 designs have been proposed of low power 1 bit full adder circuit with 10Transistors
( using PTL multiplexer) , 8 Transistor
(by using NMOS and PMOS PTL devices), 12Transistors (6Transistors to generate carry using
GDI technique and 6Transistors to generate sum using tri state inverters).
These circuits consume less power with maximum of 73% power saving com-pare to
conventional 28T design. The proposed circuit exploits the advantage of GDI technique and
pass transistor logic, and sum is generated by tri state inverter logic in all designs.
The entire simulations have been done on 180nm single n-well CMOS bulk technology, in
virtuoso platform of cadence tool with the supply voltage 1.8V and frequency of 100MHz.
DESIGN AND IMPLEMENTATION OF BIT TRANSITION COUNTERcsijjournal
In today’s VLSI system design, power consumption is gaining more attention as compared to performance and area. This is due to battery life in portable devices and operating frequency of the design. Power consumption
mainly consists of static power, dynamic power, leakage power and short circuit power. Dynamic power is dominant among all which depends on many factors viz. power supply, load capacitance and frequency. Switching
activity also affects dynamic power consumption of bus which is determined by calculating the number of bit transitions on bus. The purpose of this paper is to design a bit transition counter which can be used to calculate the
switching activity of the circuit nodes. The novel feature is that it can be inserted at any node of the circuit, thus helpful for calculating power consumption of bus.
Design of Complex Adders and Parity Generators Using Reversible GatesIJLT EMAS
This paper shows efficient design of an odd and even parity generator, a 4-bit ripple carry adder, and a 2-bit carry look ahead adder using reversible gates. Number of reversible gates used, garbage output, and percentage usage of outputs in implementing each combinational circuit is derived. The CLA used 10 reversible gates with 14 garbage outputs, with 50% percentage performance usage.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
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The impact of quantum computing has been widely recognised in the engineering domain. The age of quantum computing has arrived, and with it comes the ability to easily solve exponential problems. This book is written by me to meet current academic demands. The book is designed to address the most important aspects of the subject of Quantum Computing. The publication of the book "Quantum Computing" is the culmination of numerous years of research and teaching in academia. It is given in a way that is straightforward to comprehend. The undergraduates, and graduate students may all benefit from reading this book. We have given our very best effort to bring you accurate book material.
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The model questions and multiple-choice questions that are provided at the end of the book have been chosen to improve readers' understanding, as well as their performance in exams and key employment.
We warmly welcome and would be very appreciative of any comments or recommendations, that will help us enhance the overall quality of the book.
Cost-effective architecture of decoder circuits and futuristic scope in the e...VIT-AP University
The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.
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Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
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circuits relies on. This means that significantly lower QCA parameters can be used in
the square than in other competitive square circuits such as Wallace, Dadda, serial parallel,
and Baugh-Wooley.
Implementation of Non-restoring Reversible Divider Using a Quantum-Dot Cellul...VIT-AP University
The CMOS-based integrated circuit may scale down to nanometer range. The primary challenge is to further downscale the device and high-energy dissipation. Reversible logic does not dissipate energy and no information loss. In this
way, the state-of-the-art technology such as QCA was forced toward high-speed
computing with negligible energy dissipation in the physical foreground. This work
targets the design of non-restoring reversible divider circuit and its implementation in QCA. We have utilized few 2 × 2 FG and 4 × 4 HNG gates as the block construction and also show the QCA implementation having cost-efficient approach. Further, the divider circuit has synthesized with FG and HNG gates
and QCA implementation. This divider circuit inherits many benefits such as fewer
garbage outputs, reduce quantum cost are achieved, and also reduced QCA primitives
can be improved by using efficient QCA layout scheme. Simulation investigations have been verified by QCA Designer. The proposed non-restoring divider also compares the reversible metrics results with some of other existing works.
An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full AdderVIT-AP University
Moving towards micrometre scale to nanometre scale device shrinks down emerging nanometre technology such as quantum-dot cellular automata as a nesting
success. The introduced architecture is robust where the explicit design of full adder
and full subtraction uses for Ex-OR design. A new architecture of Ex-OR based on one majority gate is proposed, which its most optimized architecture and its placement of cells from the novel design. The analysis based on simulation showed that the
introduced Ex-OR and full adder makes only 11 and 46 cells count, respectively. In
proposed Ex-OR design, first output is received with no any latency which can be a
suitable design for implementation of the high-speed full adder design. In addition,
power estimation results are obtained after simulation of proposed designs in QCAPro
tool. Therefore, the novel designs improve the energy dissipation parameters such as mean leakage energy dissipation, mean switching energy dissipation and total energy dissipation 75, 11.28 and 82.19% in comparison with the most robust design in existing.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
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About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
2. 376 B. K. Bhoi et al.
ternary logic. Further, this gate is extended to AND and OR gate in ternary logic.
In the model [5], the pipelining technique is used to design majority gates, inverter,
corner wire, and fan out, which successfully solved the issues of elementary Ternary
QCAs.
Here, we are proposing a technique ‘The redundant binary adder by using ternary
QCA’ whose objective is to both increase in speed and minimize in power consump-
tion. A redundant binary representation allows addition without using a typical carry
so that the arithmetic operations are faster. The ternary logic is recently being con-
sidered to be an efficient technique due to its competitive advantages over binary
logic [6–10]. This adder can be used in the complicated digital circuits which will
be beneficial for the VLSI industry.
The remaining part of this paper is arranged in the following manner. Section 2
describes the basic idea and operating principle of Ternary QCA. Section 3 shows
the ternary implementation and simulation result of the proposed full-adder circuit.
Finally, the paper is concluded in Sect. 4.
2 Background of Ternary QCA
A balanced ternary logic is a type of multivalued logic system in which there are
three values, i.e., true, false, unknown (+1, 0, −1). Ternary logic has more advantages
over binary logic which uses only two values, i.e., true, and false. In Ternary QCA,
there are eight quantum-dots are present in each cell, and two mobile electrons
are tunneled between the quantum-dots. QCA do not operate by the transport of
electrons like the transistors but it operates by adjusting the electrons in a small area
of only a few square nanometers. There are four types of polarization possible in the
quantum-dot cells, i.e., −45° (−1), +45 (+1), 0° (0), 90° (0).The four different types
of polarizations have shown in Fig. 1.
Ternary gates are the basic elements used to implement the various digital circuits
based on Ternary QCA. Here, ternary wires and different types of ternary inverters
are explained [11].
A ternary wire can be created by a number of quantum-dot cells placing in a row.
When +1(+45◦
) or −1(−45◦
) is given to the input of the wire, the output value will
be the input value and the value of every cell will be identical to the input value. When
0(0◦
or 90◦
) is given to the input, the output value will be the input value but the
Fig. 1 Polarization in Ternary QCA cells
3. A Redundant Adder Architecture in Ternary Quantum-Dot … 377
value of every consecutive cell will change from 0◦
to 90◦
and 90◦
to 0◦
. Three types
of ternary inverters are proposed here, i.e., standard ternary inverter (STI), positive
ternary inverter (PTI), and negative ternary inverter (NTI). Positive ternary inverter
(PTI) is a type of ternary inverter in which when the input is given as +1, output will
be inverted to −1 and when the input is given as −1, output will be inverted to +1
and when the input is 0, output will be +1. Negative ternary inverter (NTI) is a type
of ternary inverter in which when the input is given as +1, it will be inverted to −1
and when the input is given as −1, it will be inverted to +1 and when the input is 0,
the output will be −1. Standard ternary inverter (STI) is a type of inverter in which
when the input is given as +1, the output will be −1 and when input is given as −1,
output will be +1 and when input is 0, output will be 0.
The figures and truth tables for the three types of inverter are shown in Fig. 2. In
all type of inverters, when input will be +1, output will be −1 and when input will
be −1, output will be +1. The only difference between these three ternary inverters
is that when the input has the value ‘0,’ the output of STI has the value ‘0’ and the
output of PTI has the value ‘+1’ and the output of NTI has the value ‘−1.’
Min gate is a majority gate in which one of the three inputs is fixed as −1. Output
of the min gate will be depending upon the majority inputs. Max gate is a majority
gate in which one of the three inputs is fixed as +1. Output of the max gate will be
depending upon the majority inputs. Ternary min/max gate is a type of majority gate.
As a majority gate has three inputs, the min/max gate has also three inputs. But
one of the three inputs of a min gate has a fixed value of ‘−1’ whereas the max gate
has a fixed value of ‘+1.’ So, output will depend upon majority of its inputs. The
truth tables and layout diagrams for min & max gates are given in Fig. 3. If one of
its inputs of a min gate is ‘0’ then it is called as clamp-down gate. Similarly, if one
of its inputs of a max gate is ‘0’ then it is called as clamp-up gate. When output of a
min gate is given to the input of a standard inverter, ‘antimin’ gate is formed whereas
when output of a max gate is given to the input of a standard inverter, ‘antimax’ gate
is formed [10, 11].
Fig. 2 Inverters a STI b PTI c NTI
4. 378 B. K. Bhoi et al.
Fig. 3 a Min gate b Max gate
A ternary decoder has a single input and multiple outputs. It is used to design
various complicated circuits like adders. A ternary decoder can be created by using
three different types of inverters and a min gate. Truth table and Ternary QCA layout
of a 1 input and 3 output decoder are detailed in Fig. 4. A ternary increment and
decrement gate can be implemented by using a decoder, two clamps-down gates,
and two antimax gates. Right shifting occurs in ternary increment gate whereas left
shift occurs in decrement gate. The truth table and layout diagrams for the increment
and decrement gate are given in Fig. 5 [11].
Fig. 4 Ternary decoder layout and truth table
5. A Redundant Adder Architecture in Ternary Quantum-Dot … 379
Fig. 5 Ternary increment and decrement layout and truth Table
3 Proposed Redundant Adder
Redundant binary adders (RBA) are faster than traditional binary adders because
here, carry is not propagated to next stages. In addition, RBA takes a constant time
because each digit of the result can be calculated independently of one another.
It means each digit of the result can be calculated in parallel. The truth table of
redundant adder is shown in Table 1.
The below figure indicates how carry can be eliminated by adding two numbers
A and B. A and B have length of n digits and represented by (An−1 An−2,…,A1 A0)
and (Bn−1 Bn−2,…,B1 B0). Here, Sn−2 and Cn−2 are sum and carry result after adding
An−2 and Bn−2. Similarly, other sum and carry terms are shown in Fig. 6a. Here, X
is the final result after adding sum and carry in redundant number system.
Let assume, A = 101̄1 and B = 11̄10. The below figure explains the addition
operation. Here, after adding 101̄1 (decimal = 7) and 11̄10 (decimal = 6), the final
result is 101̄01 (decimal = 13) as shown in Fig. 6b. In redundant adder, sum and carry
functions are added in order to get carry-free addition. So, sum and carry function
will be calculated by using a ternary half adder. Then, the sum and carry function of
Table 1 Truth table of redundant adder
A B Sum Carry
−1 −1 0 −1
−1 0 −1 0
−1 +1 0 0
0 −1 −1 0
0 0 0 0
0 +1 +1 0
+1 −1 0 0
+1 0 +1 0
+1 +1 0 +1
6. 380 B. K. Bhoi et al.
Fig. 6 Redundant number
system a n-bit b 4-bit
example
the half adder will be given to the inputs of another half adder. Output of the second
half adder will be the sum function of redundant binary adder.
A ternary half adder comprises a sum and a carry. Sum output can be found
by using a decoder, an increment, a decrement, three min, and two max gates. All
these components can be implemented by using the ternary gates. The gate level
implementation of the sum output is given Fig. 7. A decoder can be implemented
by using a min gate and three different types of inverters, i.e., standard ternary
inverter (STI), positive ternary inverter (PTI), and negative ternary inverter (NTI).
An increment and decrement can be implemented by using a decoder, two clamps-
down gates (clamp-down gate is a min gate where one input is ‘0’), and two antimax
gates (antimax gate is a max gate where output is given to a standard inverter).
One of the two inputs of the half adder (A) is given to a decoder which has three
outputs. Another input (B) is given to the increment and decrement blocks. The three
outputs of the decoder are given to the one of the inputs of each min gate. Output of
the decrement is given to the input of first min gate. B is given to another input of
second min gate and output of the increment is given to another input of third min
gate. Then, outputs of the three min gate are given to a max gate. Output of the max
gate will be the sum output. The block diagram for the ternary half adder which has
been implemented by using ternary gates is shown below. The decoder consists of
one PTI, one STI, and one NTI along with a STI and a min gate. One of the inputs of
half adder (A1) is given to PTI then output of the PTI (P1) is given to a STI. Output
of the STI (K1) is one of the outputs of decoder. A1 is given to NTI whose output
(Q1) which is another output of decoder and is inverted by a STI which output is R1.
Then, P1 and R1 are given as the inputs of a min gate whose output (J1) is another
output of the decoder. So, three outputs of the first decoder are given as J1, K1 and
Q1.
The increment and decrement consist of a PTI, a STI, and a NTI along with a STI,
a min gate, two clamps-down gates and two antimax gates (max gate with inverter).
The second input of half adder (B1) is given to PTI which output (M1) is given to a
STI. Output of this STI is V1. B is given as the input of NTI and its output (N1) is
inverted by a STI. This inverted output (O1) and output of the PTI (M1) are given as
the inputs of min gate whose output is U1. V1 is given to a clamp-down gate whose
output is F1. Then, F1 and U1 are given to an antimax gate (max gate with a STI)
whose output will be G1. B1 is given to a NTI whose output is given to a clamp-down
gate. Output of the clamp-down gate is given to an antimax gate whose output is H1.
Then, one of the three outputs of the decoder (J1) and input B1 is given to a min gate
7. A Redundant Adder Architecture in Ternary Quantum-Dot … 381
NT1
PT1 MIN
ST1 ST1
1
A
1
A 1
Q
1
P
1
R
1
J
1
K
NT1
PT1 MIN
ST1 ST1 Clamp Down
Clamp Down
Max
Max
ST1
ST1
1
U
1
V
1
F
1
E
1
G
1
H
1
B
1
M
1
B 1
N 1
O
1
U
1
V
Min
Min
Max
Min
Max
1
B
1
J
1
G
1
Q
1
H
1
K
1
X
1
Y 1
W
1
Z
1
S
NT1
NT1
Clamp Down
Clamp Down
Min
Max
Max
1
A
1
B
1
A
1
B
3
M
3
N
3
Q
3
R
3
P
1
T
1
C
PT1
NT1 ST1
Min
ST1
2
J
2
K
1
S
1
S
2
P
2
Q 2
R
NT1
PT1 MIN
ST1 ST1 Clamp Down
Clamp Down
Max
Max
ST1
ST1
1
M
1
N
2
G
2
H
2
U
2
V
2
F
2
E
2
U
1
C
1
C
2
O
2
V
Min
Min
Min
Max
Max
1
C
2
J
2
G
2
Q
2
H
2
K
2
X
2
Y
2
W
2
Z
2
S
Fig. 7 Block diagram of redundant full adder
8. 382 B. K. Bhoi et al.
whose output will be X1. Q1 and G1 are given to a min gate whose output will be
Y1. K1 and H1 will be given to a min gate whose output will be Z1. X1 and Y1 are
given to a max gate whose output will be W1. W1 and Z1 are given to another max
gate whose output will be the sum function S1.
The carry function comprises two NTI gates, two clamps down, one min gate,
and two max gates. The input A1 is given to a NTI whose output M2 is given to a
clamp-down gate. Output of the clamp-down gate is P3. Another input of the half
adder B2 is given to a NTI whose output N2 is given to a clamp-down gate. Output
of the clamp-down gate is Q2. A1 and B1 are given to a min gate whose output is R3.
R3 and Q3 are given to a max gate whose output is T1. Then, P3 & T1 are given to
another max gate whose output is the carry function C2. The two outputs S1 and C1
are given to another sum function of a half adder where S1 and C1 are added and the
Sum function of the redundant binary adder can be obtained.
Let take an example by taking A1 = + 1, B1 =+1
P1 = −1, Q1 = −1, R1 = 1, J1 = −1, K1 = 1
M1 = −1, N1 = −1, O1 = 1,U1 = −1, V1 = 1, E1 = −1, F1 = 0,
G1 = 0, H1 = −1
X1 = −1, Y1 = −1, Z1 = −1, W1 = −1, S1 = −1
M1 = −1, N1 = −1, P1 = −1, Q1 = −1, R1 = −1, T1 = 1, C1 = 1
P2 = 1, Q2 = 1, R2 = −1, J2 = −1, K2 = −1
C1 = 1, M2 = −1, N2 = −1, O2 = 1,U2 = −1, V2 = 1, E2 = −1, F2 = 0,
G2 = 0, H2 = −1
X2 = −1, Y2 = 0, Z2 = −1, W2 = 0, S2 = 0
In the above example, we have seen that by giving A = +1 and B = +1, the sum
output will be 0 and the carry output will be 1 which is the outputs of redundant
binary adder. In this way, all the inputs can be tested in the circuit.
In TQCA, layout of Fig. 8 has total 95 numbers of Ternary QCA cell for the first
stage sum output. In TQCA, layout of Fig. 8b has total 43 numbers of cells for carry
output. In TQCA, layout of Fig. 8c is same as earlier Fig. 8a, which is the layout of
final sum output. This layout has also 95 numbers of cells. Here, total layout area
is 0.35 µm2
. The total number of cells is (95 + 43 + 95) = 233. In this layout, the
delay of output is after four clock cycles. Therefore, the cost of the proposed ternary
redundant adder is = Area × Delay × Cell complexity = 0.35 µm2
× 4 × 233 =
326. All the proposed layouts are implemented in TQCA designer software tool [12].
9. A Redundant Adder Architecture in Ternary Quantum-Dot … 383
Fig. 8 Redundant adder in Ternary QCA a First stage sum S1 b Carry C1 c Final sum S2 d Final
sum simulation result
10. 384 B. K. Bhoi et al.
4 Conclusion
Miniaturization and speed have become an arising focus area in emerging nano-
electronics domain, which motivate nanoelectronics domain interest nowadays for
compact and high-computation speed circuit design. While noticeable in state-of-
the-art technology for an adder has been reported in QCA, there is less amount
of work on ternary-based adder. This article has presented advancement in ternary
logic-based adders to improve the computation speed. Simulation results of these
adders are correctly verified in comparison with truth table. Ternary QCA approach
can be applied to the proposed architecture such as adder, decoder, and binary incre-
ment and decrement for efficiently. Therefore, these assure the new architectures a
potential candidate for miniaturization of nanocircuit design.
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