This is a classroom presentation for the basic concepts of HDL, using Verilog as the programming language. Module 2 deals with simulation and synthesis in Verilog.
Novel Tree Structure Based Conservative Reversible Binary Coded Decimal Adder...VIT-AP University
Reversible logic has been recognized as one of the most promising technique for the realization of the quantum circuit. In this paper, a cost effective conservative, reversible binary coded decimal
(BCD) adder is proposed for the quantum logic circuit. Towards the realization of BCD adder, few novel gates, such as Half-Adder/Subtraction (HAS-PP), Full-Adder/Subtraction (FAS-PP) and Overflow-detection (OD-PP) based on parity preserving logic are synthesized which incurs 7, 10 and
13 quantum cost respectively. Coupling these gates a novel tree-based methodology is proposed to
implement the required BCD Adder. Also, the BCD adder design has been optimized to achieve the optimum value of quantum cost. In addition, the proposed BCD circuit is extended to n-bit adder using replica based techniques. Experimental result establishes the novelty of the proposed logic,
which outperforms the conventional circuits in terms of logic synthesis and testability. The limitation
of detecting the missing gate and missing control point of the quantum circuit of overflow detection
is finally tackled this work by the proposed OD-PP with the application of the minimum test vector. In addition, reversible circuits of control inputs based testable master-slave D-FF is intended. The noted work on the testable sequential circuit presented here is to develop circuit using minimum test vectors and can find diverse application in the testing paradigm
Novel Tree Structure Based Conservative Reversible Binary Coded Decimal Adder...VIT-AP University
Reversible logic has been recognized as one of the most promising technique for the realization of the quantum circuit. In this paper, a cost effective conservative, reversible binary coded decimal
(BCD) adder is proposed for the quantum logic circuit. Towards the realization of BCD adder, few novel gates, such as Half-Adder/Subtraction (HAS-PP), Full-Adder/Subtraction (FAS-PP) and Overflow-detection (OD-PP) based on parity preserving logic are synthesized which incurs 7, 10 and
13 quantum cost respectively. Coupling these gates a novel tree-based methodology is proposed to
implement the required BCD Adder. Also, the BCD adder design has been optimized to achieve the optimum value of quantum cost. In addition, the proposed BCD circuit is extended to n-bit adder using replica based techniques. Experimental result establishes the novelty of the proposed logic,
which outperforms the conventional circuits in terms of logic synthesis and testability. The limitation
of detecting the missing gate and missing control point of the quantum circuit of overflow detection
is finally tackled this work by the proposed OD-PP with the application of the minimum test vector. In addition, reversible circuits of control inputs based testable master-slave D-FF is intended. The noted work on the testable sequential circuit presented here is to develop circuit using minimum test vectors and can find diverse application in the testing paradigm
Vhdl code and project report of arithmetic and logic unitNikhil Sahu
The main objective of project is to design and verify different operations of Arithmetic and Logical Unit (ALU). We have designed an 8 bit ALU which accepts two 8 bits numbers and the code corresponding to the operation which it has to perform from the user. The ALU performs the desired operation and generates the result accordingly. The different operations that we dealt with, are arithmetical, logical and relational. Arithmetic operations include arithmetic addition, subtraction, multiplication and division. Logical operations include AND, OR, NAND, XOR, NOT and NOR. These take two binary inputs and result in output logically operated. The operations like the greater than, less than, equal to, exponential etc are also included. To implement ALU, the coding was written in VHDL . The waveforms were obtained successfully. After the coding was done, the synthesis of the code was performed using Xilinx-ISE. Synthesis translates VHDL code into netlist (a textual description). Thereafter, the simulation was done to verify the synthesized code.
Yaser Khalifa introduces you to VHDL (VHSIC Hardware Description Language), a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
Software modernization often involves complex code transformations that convert legacy code to new architectures or platforms, while preserving the semantics of the original programs. We present the lessons learnt from an industrial software modernization project of considerable size. This includes collecting requirements for a code-to-model transformation, designing and implementing the transformation algorithm, and then validating correctness of this transformation for the code-base at hand. Our transformation is implemented in the TXL rewriting language and assumes specifically structured C++ code as input, which it translates to a declarative configuration model. The correctness criterion for the transformation is that the produced model admits the same configurations as the input code. The transformation converts C++ functions specifying around a thousand configuration parameters. We verify the correctness for each run individually, using translation validation and symbolic execution. The technique is formally specified and is applicable automatically for most of the code-base.
FPGA training session generic package and funtions of VHDL by Digitronix NepalKrishna Gaihre
Understanding Generic, Package and Functions in VHDL , Creating a package in VHDL, Creating Functions in VHDL is introduced in this presentation. This Training is Conducted by Digitronix Nepal. Digitronix Nepal is working on FPGA, ASIC and VLSI Design and Verification.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
Vhdl code and project report of arithmetic and logic unitNikhil Sahu
The main objective of project is to design and verify different operations of Arithmetic and Logical Unit (ALU). We have designed an 8 bit ALU which accepts two 8 bits numbers and the code corresponding to the operation which it has to perform from the user. The ALU performs the desired operation and generates the result accordingly. The different operations that we dealt with, are arithmetical, logical and relational. Arithmetic operations include arithmetic addition, subtraction, multiplication and division. Logical operations include AND, OR, NAND, XOR, NOT and NOR. These take two binary inputs and result in output logically operated. The operations like the greater than, less than, equal to, exponential etc are also included. To implement ALU, the coding was written in VHDL . The waveforms were obtained successfully. After the coding was done, the synthesis of the code was performed using Xilinx-ISE. Synthesis translates VHDL code into netlist (a textual description). Thereafter, the simulation was done to verify the synthesized code.
Yaser Khalifa introduces you to VHDL (VHSIC Hardware Description Language), a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
Software modernization often involves complex code transformations that convert legacy code to new architectures or platforms, while preserving the semantics of the original programs. We present the lessons learnt from an industrial software modernization project of considerable size. This includes collecting requirements for a code-to-model transformation, designing and implementing the transformation algorithm, and then validating correctness of this transformation for the code-base at hand. Our transformation is implemented in the TXL rewriting language and assumes specifically structured C++ code as input, which it translates to a declarative configuration model. The correctness criterion for the transformation is that the produced model admits the same configurations as the input code. The transformation converts C++ functions specifying around a thousand configuration parameters. We verify the correctness for each run individually, using translation validation and symbolic execution. The technique is formally specified and is applicable automatically for most of the code-base.
FPGA training session generic package and funtions of VHDL by Digitronix NepalKrishna Gaihre
Understanding Generic, Package and Functions in VHDL , Creating a package in VHDL, Creating Functions in VHDL is introduced in this presentation. This Training is Conducted by Digitronix Nepal. Digitronix Nepal is working on FPGA, ASIC and VLSI Design and Verification.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
International Journal of Computational Engineering Research (IJCER) ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology
Design and implementation of synchronous 4 bit up counter using 180 nm cmos p...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...iosrjce
Field Programmable Gate Arrays (FPGA) are increasingly being used to design high- end
computationally intense microprocessors capable of handling both fixed and floating- point mathematical
operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking
significant area. Over the years, the VLSI community has developed many floating-point adder algorithms
mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating
point adder with minimum time. Floating point numbers are used in various applications such as medical
imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the
performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL.
This paper discusses in detail the best possible FPGA implementation will act as an important design resource.
The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area,
and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.
Introduction to Verilog HDL. This class notes present basic HDL structures, data types, operators, and expressions in Verilog. It also describes three typical modeling style for HDL design; behavioral, dataflow, and structural.
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...Silicon Mentor
Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. This paper deals with the comparison of various arithmetic modules and the implementation of optimized floating point ALU. For more info download this file or visit us at:
http://www.siliconmentor.com/
An approach to Measure Transition Density of Binary Sequences for X-filling b...IJECEIAES
Switching activity and Transition density computation is an essential stage for dynamic power estimation and testing time reduction. The study of switching activity, transition densities and weighted switching activities of pseudo random binary sequences generated by Linear Feedback shift registers and Feed Forward shift registers plays a crucial role in design approaches of Built-In Self Test, cryptosystems, secure scan designs and other applications. This paper proposed an approach to find transition densities, which plays an important role in choosing of test pattern generator We have analyze conventional and proposed designs using our approache, This work also describes the testing time of benchmark circuits. The outcome of this paper is presented in the form of algorithm, theorems with proofs and analyses table which strongly support the same. The proposed algorithm reduces switching activity and testing time up to 51.56% and 84.61% respectively.
This is a classroom presentation for the basic concepts of HDL, using Verilog as the programming language. Module 3 deals with programmable logic devices.
This is a slideshow depicting the importance of guru in the spiritual life. And in addition, about the practice of Gaayathree manthra and its specialties.
This is a slide-show containing the names of all the literary works written by Adi Shankaracharya. The last slide contains the summary of his greatest contributions.
An introduction to the practice of Ashtangayoga, with some prerequisites and attitudinal changes, concluding with some valid health tips and lifestyle changes.
Preparation to yogic breathing as well as some popular methods of yogic breathing (pranayama) are mentioned here, along with some additional health tips.
These slides are with less text and more pictures, with each slide sequentially related to the next one in an intuitive way, and hence the viewer should follow his/her intuitive skills in order to comprehend the flow. The truth is one, ultimately.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Democratizing Fuzzing at Scale by Abhishek Aryaabh.arya
Presented at NUS: Fuzzing and Software Security Summer School 2024
This keynote talks about the democratization of fuzzing at scale, highlighting the collaboration between open source communities, academia, and industry to advance the field of fuzzing. It delves into the history of fuzzing, the development of scalable fuzzing platforms, and the empowerment of community-driven research. The talk will further discuss recent advancements leveraging AI/ML and offer insights into the future evolution of the fuzzing landscape.
Event Management System Vb Net Project Report.pdfKamal Acharya
In present era, the scopes of information technology growing with a very fast .We do not see any are untouched from this industry. The scope of information technology has become wider includes: Business and industry. Household Business, Communication, Education, Entertainment, Science, Medicine, Engineering, Distance Learning, Weather Forecasting. Carrier Searching and so on.
My project named “Event Management System” is software that store and maintained all events coordinated in college. It also helpful to print related reports. My project will help to record the events coordinated by faculties with their Name, Event subject, date & details in an efficient & effective ways.
In my system we have to make a system by which a user can record all events coordinated by a particular faculty. In our proposed system some more featured are added which differs it from the existing system such as security.
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Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
TECHNICAL TRAINING MANUAL GENERAL FAMILIARIZATION COURSEDuvanRamosGarzon1
AIRCRAFT GENERAL
The Single Aisle is the most advanced family aircraft in service today, with fly-by-wire flight controls.
The A318, A319, A320 and A321 are twin-engine subsonic medium range aircraft.
The family offers a choice of engines
Automobile Management System Project Report.pdfKamal Acharya
The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
When a customer search for a automobile, if the automobile is available, they will be taken to a page that shows the details of the automobile including automobile name, automobile ID, quantity, price etc. “Automobile Management System” is useful for maintaining automobiles, customers effectively and hence helps for establishing good relation between customer and automobile organization. It contains various customized modules for effectively maintaining automobiles and stock information accurately and safely.
When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
Also when the user tries to sale items which are not in stock, the system will prompt the user that the stock is not enough. Customers of this system can search for a automobile; can purchase a automobile easily by selecting fast. On the other hand the stock of automobiles can be maintained perfectly by the automobile shop manager overcoming the drawbacks of existing system.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
1. SYSTEM DESIGN USING HDL (ECE43)
#
Digital system design using Verilog,
Charles Roth, Lizy Kurian John,
Byeong Kil Lee,
1st Edition, 2016, Cengage Learning
1 2.1, 2.2, 2.3 - 2.8, 2.11, 2.13 - 2.15
2 2.9, 2.10, 2.12, 2.16 - 2.19, 8.1, 8.2
3 3.1 - 3.4, 5.1, 5.2.1, 5.3
4 4.1 - 4.5, 4.8, 4.6, 4.7, 4.9, 4.11
5 6.1 - 6.5, 6.7 - 6.12
SIMULATION
AND SYNTHESIS
2. 01/02/2019 2Aravinda K., Dept. of E&C, NHCE, Bengaluru
Delays in Verilog
Inertial delay Transport delay
Input pulse, that is
shorter than the delay
of the assignment, does
not get propagated to
the output.
propagation
delay of the gate
delay due to
the wire
Input pulse gets
transmitted to the
output, after the
assigned delay is
added to it’s value.
Net delay
updation of
the net’s value
When the net takes
the value from the
driver, the value on
the wire changes,
after a delay.
3. 01/02/2019 3Aravinda K., Dept. of E&C, NHCE, Bengaluru
Delayed assignment
= transport delay
Delayed evaluation
= inertial delay
Illegal assignment
RHS of the statement
LHS of the statement
4. 01/02/2019 4Aravinda K., Dept. of E&C, NHCE, Bengaluru
Net delay gets added to the RHS after
the inertial delay, because, the inertial
delay is from the driver of the net.
C1 rejects pulses that are less than 30 ns.
C2 rejects pulses that are less than 20 ns.
D rejects pulses that are less than 7 ns.
E rejects pulses that are less than 3 ns.
5. 01/02/2019 5Aravinda K., Dept. of E&C, NHCE, Bengaluru
Compilation, simulation and synthesis
Compilation: Checking of syntax and semantic rules (e.g., presence of
semicolon, operation in between the signals of same type)
Elaboration: Instantiation of modules (e.g., creation of driver for each
signal, memory allocation for signals, interconnections among the ports)
Simulation: Initialization of values for the signals, and then, the
verification of the functionality of the modules
6. 01/02/2019 6Aravinda K., Dept. of E&C, NHCE, Bengaluru
A design consists of connected threads of execution, called as
processes.
The processes include modules, assignment statements,
procedural blocks, system tasks etc.
A change in a signal is referred to as an “event”, and Verilog uses
event-driven simulation.
During simulation, each change in the value of a net or a
variable is called as “update event”.
When an “update event” is executed, all the processes that are
sensitive to that event, are evaluated.
As events occur at different times, they are kept on an “event
queue”, ordered by the “simulation time”.
The processing of all active events is called a “simulation cycle”.
7. 01/02/2019 7Aravinda K., Dept. of E&C, NHCE, Bengaluru
Name Contents of the region Example
Active event
region
events that occur in the current
simulation time (some events in this
region, will be moved to the other
regions, as per the event schedule)
continuous assignments
Inactive event
region
events that shall be processed after all
the active events are processed
blocking assignments
without delay
Non-blocking
assign update
region
events that are assigned to the current
simulation time, after all the active
and inactive events are processed
non-blocking
assignments without
delay
Monitor
event region
events that shall be processed after all
the active, inactive and non-blocking
assign update events are processed
$monitor, $strobe
Future event
region
events that occur at some future
simulation time
blocking as well as non-
blocking assignments
with delay
The Verilog event queue is segmented into five different regions
8. 01/02/2019 8Aravinda K., Dept. of E&C, NHCE, Bengaluru
Events are added to the
event queue in the source
code order.
In this example, in the first
module, the variable “a” will
be assigned “0” after 5 ns,
and “1” after another 5 ns.
In the second module, the
two “always” blocks are
concurrent, and hence there
is no ordering.
If a module contains more than
one process, all processes
execute concurrently.
9. 01/02/2019 9Aravinda K., Dept. of E&C, NHCE, Bengaluru
If “initial” block is not specified, the
variables would hold the value “x”.
“always” statement waits until a signal
on the sensitivity list changes.
During an event, when no time delay is
specified, Δ delay comes into picture.
In this code, as the “x” value of ‘B’
changes to “0”, the first “always” gets
processed, and the value of ‘A’ changes
to “1” after the Δ delay.
The second “always” also gets processed
at the same time, and the value of ‘B’
changes to “1” after 10 ns.
10. 01/02/2019 10Aravinda K., Dept. of E&C, NHCE, Bengaluru
For synthesis, it is not necessary
to perform simulation.
The output of synthesis is the
“netlist”, which is a list of the
required components and their
interconnections.
The netlist can be utilized to
implement the digital system,
by programming CPLD or FPGA.
11. 01/02/2019 11Aravinda K., Dept. of E&C, NHCE, Bengaluru
Simple Synthesis Examples
Issues
1. The delay of 5 ns will not be present in
the hardware, as “#5” does not get
synthesized. If a delay has to be
modeled, then counter has to be
included in the code.
2. As ‘B’ is not present in the sensitivity
list, the synthesized hardware will not
produce any output whenever the
value of ‘B’ changes. Thus, simulated
output will be different from that of
the synthesizer.
Remedy
Check for synthesizer warnings of
missing signals in the sensitivity list.
Example - 1
Verilog code
Synthesized hardware
12. 01/02/2019 12Aravinda K., Dept. of E&C, NHCE, Bengaluru
Example - 2Verilog code
Synthesized hardware
Block diagram
Internal circuitry
1. The values of ‘C’ and ‘G’ need to be
retained after the positive edge of
the clock. Therefore, flip-flops are
required for both ‘C’ and ‘G’.
2. A change in the value of ‘C’ from
statement-1 will not be considered
during the execution of statement-2.
13. 01/02/2019 13Aravinda K., Dept. of E&C, NHCE, Bengaluru
Example - 3
If “clock” is omitted in the
sensitivity list of an “always”
statement, the synthesizer
may produce latches instead
of flip-flops. Hence, to reduce
the number of flip-flops, it is
better not to put the signal
assignments in a clocked
“always” statement.
Example - 4
The synthesizer will create
an empty blcok diagram, as
the output ‘D’ is not at all
assigned in the code. The
synthesizer will give the
following warnings:
15. 01/02/2019 15Aravinda K., Dept. of E&C, NHCE, Bengaluru
Declaration of constants in Verilog
There are three methods to define constant values: i) using the
compiler directive `define, ii) using the keyword parameter, iii) using
the keyword localparam.
Note: Constants defined using parameter can be changed during
module instantiation. For the constants which should not be changed,
localparam is used to define them.
i) `define constant_name constant_value
e.g., `define wordsize 16
reg [1: `wordsize] data;
Here, data is declared to be a reg of width wordsize.
ii) parameter constant_name = constant_value;
e.g., parameter msb = 15;
parameter [31:0] decim = 1’b1;
iii) localparam constant_name = constant_value;
e.g., localparameter pi = 3.1416;
16. 01/02/2019 16Aravinda K., Dept. of E&C, NHCE, Bengaluru
Usage of arrays in Verilog
Digital VLSI circuits consist of repeated use of similar structures,
and hence arrays can be utilized to model such structures, along with
the required array bounds.
Declaration
reg [0:7] regA; // an 8-bit register.
reg regB [0:7]; // an array of eight 1-bit registers.
wire wire_arrayA [5:0]; // an array of six wires.
integer intA [1:64]; // an array of sixty four integers.
reg [7:0] regC [15:0]; // an array of sixteen 8-bit registers.
Initialization
regA = 8’b10010110; // 8-bit register’s contents.
regC[15] = 8’b10100101; // 16th register’s 8-bit contents.
.
.
.
regC[0] = 8’b10010110; // 1st register’s 8-bit contents.
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Matrices
Matrices can be declared as multidimensional arrays. A matrix of
size (4X3) with 8-bit elements is declared and initialized as follows –
reg [7:0] matrixA [0:3][0:2] = {{4, 2, 9},
{1, 3, 4},
{8, 6, 7},
{5, 9, 2}};
The array element referenced as matrixA[2][1] implies the element
that is in 3rd row and 2nd column, and it contains the value 6.
The arrays, along with the parameters, can be used to construct
look-up tables (LUT), which can be used to create combinational
circuits using ROM or LUT.
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Input
(LUT Address)
Output
(LUT Data)
0000 00001
0001 00010
0010 00100
0011 00111
0100 01000
0101 01011
0110 01101
0111 01110
1000 10000
1001 10011
1010 10101
1011 10110
1100 11001
1101 11010
1110 11100
1111 11111
Example: odd parity representation for 4-bit numbers
Verilog code for the example
module parity_gen(X,Y);
input [3:0] X;
output [4:0] Y;
wire paritybit;
parameter [0:15] onebit = {1’b1, 1’b0, 1’b0, 1’b1,
1’b0, 1’b1, 1’b1, 1’b0, 1’b0, 1’b1, 1’b1, 1’b0, 1’b1,
1’b0, 1’b0, 1’b1};
assign paritybit = onebit[X];
assign Y = {X, paritybit};
Endmodule
As the first 4 bits of the output are
identical to the input, it is not necessary to
store all the 5-bit 16 numbers in the LUT.
Therefore, only the 16 parity bits can be
stored, and the particular parity bit can be
concatenated with the respective input bit.
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Usage of loops in Verilog
A system, in which an activity is happening in a repetitive fashion,
can be represented by means of a loop.
The loop statements are sequential in nature. In Verilog, the keywords
“forever”, “for”, “while” and “repeat” are used for the same.
There can be an infinite loop, as follows:
begin
clk = 1’b0;
forever #10 clk = ~clk;
end
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Testing a Verilog Model
A test bench is a separate Verilog code, which provides input
combinations, to test a Verilog model.
In other words, the test bench is used during simulation, to provide
stimuli to the system or circuit under test.
The test bench module does not have external inputs and outputs, and
hence the port list in the module declaration, will be empty.
Example: 4-bit adder
An exhaustive test of this adder
requires 512 tests (16 numbers of
Addend X 16 numbers of Augend
X 2 values of Carry-in).
Design Under Test
Test bench (Top module)
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Test bench program with a random set of 11 tests
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Verilog Functions
A function returns only a single value, and a function cannot contain delays.
Functions and tasks can be defined in the module that they will be used in.
A function call in the program file can happen just like an expression.
A function can call other functions, but the function cannot call tasks.
If a function or a task is defined as a separate file, then the compiler
directive `include has to be used in the program file.
Example-1: Write a function for generating an even parity bit for a 4-bit number.
function [4:0] even_parity;
input [3:0] A;
reg temp;
begin
temp = A[0]^A[1]^A[2]^A[3];
even_parity = {A, temp};
end
endfunction
module even_test(Z);
output reg [4:0] Z;
reg [3:0] INP;
initial
begin
INP = 4’b0101;
Z = even_parity(INP);
end
endmodule
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Example-2:
Write a function
to add two
4-bit numbers
function [4:0] add4;
input [3:0] A,B;
input cin;
reg [4:0] sum;
reg cout;
begin
integer i;
for (i=0; i<=3; i=i+1)
begin
cout = (A[i] & B[i]) | (B[i] & cin) | (A[i] & cin);
sum[i] = A[i] ^ B[i] ^ cin;
cin = cout;
end
sum[4] = cout;
add4 = sum;
end
endfunction
Function call: i) Z <= add4(X, Y, 0); // for adding Y to Z
ii) Z <= add4(X, ~Y, 1); // for subtracting Y from Z, ignoring Z[4]
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Example-3:
Write a program which
computes the square of a 4-bit
number, by using a function
module squares_test (clk);
input clk;
reg [3:0] temp;
reg [7:0] answer;
function [7:0] squares;
input [3:0] number;
begin
squares = number * number;
end
endfunction
initial
begin
temp = 4’b0011;
end
always @(posedge clk)
begin
answer = squares (temp)
end
endmodule
A function must have at least
one input argument.
The function cannot have output
or inout arguments.
Recursive functions must be
declared as automatic.
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Verilog Tasks
Unlike functions, the tasks can return any number of values.
Tasks can contain delay, event and timing control statements.
Tasks can have arguments of type input, output and inout.
This task adds two 4-bit numbers.
Task call:
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Function Task
At least one input argument,
but no output or inout
arguments
Any number of input, output or
inout arguments
Returns a single value by
assigning the value to the
function name
Passes multiple values that are
declared inside
Can call other functions, but
cannot call tasks
Can call other functions or tasks
Cannot contain any time-
controlled statements
Can contain time-controlled
statements
Executes in zero simulation time
Executes in non-zero simulation
time
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Name Function
$display Prints the test’s results on the screen, exactly after
execution, and then adds a newline character
$write Prints the test’s results on the screen, exactly after
execution, but does not add a newline character
$strobe Prints the test’s results on the screen, at the end of
the current simulation time
$monitor Prints the test’s results on the screen, every time
when one of its parameters changes
System tasks to observe the outputs
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System tasks to observe the outputs
$display(“Simulation time is %t”, $time);
$display(“Simulation time is %t”, $time);
Simulation time is 10
Simulation time is 11
$write(“Simulation time is %t”, $time);
$write(“Simulation time is %t”, $time);
Simulation time is 10 Simulation
time is 11
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always@(posedge reset)
$strobe(“The FlipFlop value is %b at time %t”, q, $time);
The FlipFlop value is 1 at time 17
The FlipFlop value is 0 at time 24
The FlipFlop value is 1 at time 26
initial
$monitor(“At %t, d=%d, clk=%d”, $time, d, clk, “and q is %b”, q);
At 24, d=x, clk=x and q is 0
At 25, d=x, clk=x and q is 1
At 30, d=0, clk=x and q is 1
At 35, d=0, clk=1 and q is 1
At 40, d=0, clk=0 and q is 1