This document describes static timing analysis of a FIFO design using Synopsys Primetime. It includes details of the FIFO design, an introduction to Primetime, the Primetime user design flow, setting up Primetime, using it for timing analysis, Verilog code for the FIFO, a script file, and expected timing report outputs. Primetime is used to perform gate-level timing analysis and check for timing violations related to setup/hold times and other constraints.

1. Static Timing Analysis of
FIFO Using Synopsys
Primetime
-Sumeet Jain
Guide: Dr. Xiaoyu Song

2. Contents:
1. FIFO description………………………………………………….
2. Introduction to Synopsys Primetime…………………………………………
3. Primetime User design flow………………………………………………….
4. Setting up Primetime…………………………………………………………
5. Using Primetime for Static timing analysis…………………………………..
6. FIFO.sv……………………………………………………………………….
7. Script file………………………………………………………………………
8. Timing report………………………………………………………………….
9. References……………………………………………………………………..

3. 1. FIFO:
Fig: 1.1 FIFO design
Description:
•WriteData [DATAWIDTH: 0]: - Writes data on FIFO
•Write Enable (WrEn): - Active high signal, allows data to be written in FIFO memory
•Read Enable (RdEn): - Allows data to be read from FIFO memory on ReadDatabus
•ReadData [DATAWIDTH: 0]: - Data from FIFO memory read on this bus
•fullBar: - Active high signal, shows that FIFO is full
•emptyBar: - Active high signal, shows FIFO is empty
•fillCount: - Counter, shows how much FIFO is filled
•Consist of write and read pointers
•fillCount = WPtr –RPtr
•Producer is only allowed to write when FIFO is not Full

4. •Data is only read when FIFO is not empty
•Data is read out synchronously
2. Introduction to Synopsys Primetime: [1] PrimeTime is the Synopsys stand-
alone, full-chip, gate-level static timing analyzer. PrimeTime performs timing analysis at the gate
level and provides a comprehensive set of modeling technologies for representing non-
synthesized blocks for analysis
Useful timing checks by Primetime
 Setup and hold requirements of sequential devices and gated clocks
 Minimum period and minimum pulse width for clock signals
 User defined minimum and maximum delay constraints
 Required input and output delays
 Clock Skew
[Please refer to the Primetime User guide for checking all the functions provided by primetime]
3. Primetime User design flow:
Fig 1 User design flow [primetime user guide]

5. 1. Read and link the designs and libraries. Set the search path and the link path, then run read_db
and link_design.
2. Specify the attributes, environment, constraints, and timing exceptions, including wire load
models or annotated delays or parasitics; port drive and capacitance; clocks; latches; uncertainty;
input and output delay; and false and multicycle paths.
3. Perform analysis.
4. Optionally, budget the design or characterize the context and write a script for Design
Compiler, and perform mode analysis and case analysis.
4. Setting up Primetime:
Step1 - Open terminal: Right click to open a terminal
Fig 2
Step1.1 - Type “addpkg” (This is a onetime thing….) a blue window, full of tools available, will
pop up. Select Synopsys Primetime and press ok

6. Step2 - Invoke Design compiler by typing “pt_shell” (Invoke primetime from address space
where all files are located) [To start primetime in GUI type start_gui after you invoke primetime]
Fig 5
5. Using Primetime for Static timing analysis:
1. Set the link path to specify where PrimeTime searches for designs and library cells when
linking the design
2. Read the technology library .db format file into memory
3. Read the design .db format files into memory
4. Link the design to resolve all references in the design
5. Set timing constraints
6. Display the timing reports (set up and hold time etc.)

7. 6. FIFO.sv
//`timescale 1ns/100ps
module SVFIFO(clk, reset, WrEn, RdEn, WriteData, emptyBar,
fullBar,ReadData,fillCount);
parameter ADDRWIDTH = 5; // depth = 1<<ADDRWIDTH;
parameter DATAWIDTH = 16;
input logic clk, reset;
input logic WrEn, RdEn;
input logic [DATAWIDTH-1:0] WriteData;
output logic emptyBar, fullBar;
output [DATAWIDTH-1:0] ReadData;
output wire [ADDRWIDTH:0] fillCount;
logic [ADDRWIDTH:0] WPtr;
logic [ADDRWIDTH:0] RPtr;
logic [DATAWIDTH -1:0] fifo [1<<ADDRWIDTH :0];
always_ff @(posedge clk)
begin
if (reset == 0)
begin
WPtr <= 0; //initialising write pointer
RPtr <= 0; //initialising Read pointer
end
else
begin
if (fullBar != 1 && WrEn == 1) // Producer is allowed to write only
// if FIFO is not full
begin
fifo[WPtr[(ADDRWIDTH-1) :0]][DATAWIDTH -1 :0]= WriteData; //write
WPtr <= WPtr + 1; // to FIFO increment the pointer
end
if (emptyBar != 1 && RdEn ==1)//When Comsumer wants to read the FIFO
//FIFO is not empty then content of FIFO are read.
RPtr <= RPtr +1; //read pointer is incremented
end
end
assign fillCount = WPtr - RPtr ; //it calculates the depth
assign ReadData = fifo[RPtr[(ADDRWIDTH-1):0]] [DATAWIDTH -1 :0] ;//data is
//read out of FIFO Asynchronously
always_comb
begin
emptyBar = 0;
fullBar =0;
if (fillCount == 0) // checking for empty
emptyBar = 1;
else
if (fillCount == 1<<ADDRWIDTH) //checking for full
fullBar = 1;
end
endmodule
“Obtain the synthesis file of the above design using synopsys DC and use the file as an input
design for primetime”

8. 7. Script File (source this file after reading the design and libraries)

9. 8. Timing Report

10. 9. References:
1. Synopsys Primetime User guide