1. CHIP PACKAGING TECHNOLOGY
Vinchip Systems
(a Design and Verification Company)
Chennai.

2. Objective
 Why chip packaging?
 Rent’s rule
 Good chip package requirement
 Package Material
 Interconnect levels
 Multichip Modules
 Thermal consideration
 Trends in process technology
 SOI
 Long term developments

3. Why chip packaging?
 Brings signal & supply wires out of
silicon die
 Protects against environmental
condition
 Heat remover
 Provides mechanical strength

4. Rent’s rule:
 The no of input & output pins to the
complexity of the circuit, as measured
by the number of gates .It is written
as
P=K *G^(Beta)

5. Good chip package requirement
 Electrical Requirement
-C ,R ,L
 Mechanical and thermal properties
-Heat removal
-Reliability
 Cost
-Plastic
-Ceramic

6. Package Material
 Ceramic
 Alumina
 Polymer
Factors to be considered
 Thermal expansion
 Dielectric constant
 Interconnect capacitance

7. Interconnect levels
• Die-to Package substrate
->wire bonding process
->7nH-40nH
->Tap Automated Bonding (TAB)
->(0.3-0.5 )nH
->(0.2-0.5)pF
->Flip-chip mounting

8. Cont…
2.Package substrate to board
->DIP <64
->PGA >300
->Surface mount technique
->PLCC
->BGA

9. Multichip Modules
 MCM (multichip module technique)
->reducing the layers
->die directly on the wired
backplane
Advantages:
->C=0.1pF
->L=0.1pF
->reduced I/O pads

10. Thermal consideration
 Temperature:
->Reverse biased diodes
->Electro migration
->Hot electron trapping
Commercial: (0-70)degree C
Industrial : ((-15) to 85) degree C
Military : ((-55) to 125) degree C

11. Trends in process technology
 LDD (Lightly Doped Drain)
->Silicide (TiSi2)
 Short term developments
 Copper and low-K dielectrics
->Conductivity: Cu>Al
->Copper easily diffused in silicon.
->Insulated copper (Titanium Nitride)

12. SOI
 Silicon On Insulator:
->Very thin silicon layer,
deposited on the top of thick
SiO2 layer.
->Parasitic effect reduced
->Better on-off transistor
characteristic
->Performance :22%

13. Long term developments
 Truly 3D Integrated circuits
->Getting signals in/out (challenge)
->Need extra active layers,between
the metals
->Voltage
->Performance
->Heat dissipation

14. Summary
 Thus chip packaging creates good
impact in designing