This document discusses the synthesis of combinational and sequential logic using Verilog. It begins by describing how synthesis tools optimize Boolean equations and map them to hardware implementations. It outlines the tasks performed by synthesis tools like eliminating redundant logic and detecting unused states. The document then discusses the different levels of abstraction in logic design from architectural to logical to physical. It explains how synthesis transforms designs between these levels using a Y-chart. The rest of the document goes into more details about logic synthesis, describing how tools perform optimizations like decomposition, extraction, factoring, substitution and elimination on logic networks. It also discusses best practices for writing synthesizable Verilog code for combinational and sequential logic.

1. Synthesis of combinational
and Sequential Logic

2. Verilog
Synthesis of combinational and Sequential
Logic
 This chapter presents an automated approach to optimizing the
Boolean equations describing a multi-input, multi-output logic
circuits.
 ASIC depends on software tools to manage and manipulate the
database that describes large, complex circuits.
 Synthesis engine plays a strategic role by automating the task of
minimizing a set of Boolean functions and mapping the result in to
a hardware implementation that meets designs objective.
 Automated software tools can optimize logic quickly and without
error

3. Verilog
 To use the tool effectively, designer should understand hardware
description language (HDL) and be skilled by writing descriptions
that conform to the constraints imposed by the tool.
“Understand how to write synthesis-friendly verilog
models is the key to automated design methods”

4. Verilog
Tasks Performed by synthesis tool
1. Detects and eliminates redundant logic.
2. Detects combinational Feedback loop.
3. Exploits don’t care conditions
4. Detects unused states
5. Detects and collapses equivalent states
6. Make state assignment
7. Synthesis optimal, multilevel realization of logic subject to
constraints on area and speed in a physical technology.

5. Verilog
Tasks for the designer
 Understand how to synthesize the combinational logic
 Understand how to synthesize the sequential logic
 Understand how language construct synthesizes
 Anticipate the results of synthesis
 Adhere to style conventions

6. Verilog
Introduction to synthesis
 Models of the circuits are classified using Levels of abstractions
and Views.
Three common levels of abstractions are :
1. Architectural
2. Logical
3. Physical

7. Verilog
Architectural Level
 Describes Operations that must be executed by the circuit to
transform a sequence of inputs into a sequence of outputs, but
does not associate the operations with specific clock cycles.
 Operations will be implemented by distinct, interconnected and
synchronized functional units.
 The design challenge here is to extract computational recourses
that implements the functionality of the machine.

8. Verilog
Logic Level
 Describes a set of variables and set of Boolean functions that the
circuit must implement
 An architecture of register resources and functional units and the
sequential activity of a logic level model are a part of description
 The designers tasks here is to translate the Boolean description in
to an optimized level netlist that will implement the circuit in
satisfactory level of performance.
 Synthesis tools are used to perform this task

9. Verilog
Physical Level
 Geometrical model describes the shapes that defines the doping
regions of semiconductor material used to fabricate transistor
 HDL does not treats geometrical models

10. Verilog
Three Common Views
 Designer may begin at high level of abstraction but ultimate ends
with physical reality. Along the path between the two, an HDL
can facilitate the design process by providing different views of
the circuits.
Three common views are :
1. Behavioral: Algorithmic that specifies sequence of data
transformations
2. Structural: datapath elements and controller that implements
algorithm
3. Physical : Actual geometric patterns of the physical devices

11. Verilog
Y-Chart
 Synthesis creates a sequence of transformations between view of
a circuit, from a higher level of abstraction to a lower one.

12. Verilog
 The Chart shows the sequence of transformation
1. Behavioral synthesis transforms an algorithm to an architecture
of a register and a schedule of operations that occurs in specified
clock cycles.
2. A verilog model of this architecture is formed as RTL
3. Logic synthesis translates RTL description in to a Booleans
representation and synthesize in to a netlist.

13. Verilog
LOGIC SYNTHESIS
 Logic Synthesis generates a structural view (netlist) form a logic
level view (RTL).
 Logic level view is a set of Boolean equations described by a set
of continuous assignment statement in verilog.

14. Verilog
Why Logic Synthesis
 As technology advances, the number of the gates on the chip
increases
 Huge circuits are impractical to design manually. IC’s todays
have 10M of transistors
 Huge reduction of time is required to create circuits.
 Better performance- Gates closer together means lesser delay,
higher frequency of operation
 Fundamentally different approach: instead of manual connecting
low level logic gates, a design language is used.

15. Verilog

16. Verilog
What is Logic Synthesis
 The process of parsing,
translating, optimizing and
mapping RTL code into a
specified standard library
cells.
 Example: To determine the
feasibility of the design, we
need to synthesize the RTL
code into a gates, measuring
timing, power and area.

17. Verilog
Logic Synthesis Input and Output Formats
Inputs:
 Timing library in liberty
format
 RTL in the verilog language
 Timing constrains
Outputs:
Gate level netlist in verilog
language

18. Verilog
Tasks Performed by synthesis tool
1. Detects and eliminates redundant logic.
2. Detects combinational Feedback loop.
3. Exploits don’t care conditions
4. Detects unused states
5. Detects and collapses equivalent states
6. Make state assignment
7. Synthesis optimal, multilevel realization of logic subject to
constraints on area and speed in a physical technology.

19. Verilog
Espresso Minimizer
 Minimizes single Boolean function of several inputs
 Uses transformation
1. Expand: determines prime implicates
2. Irredundant: removes redundant logic
3. Reduce: Determines minimum cover (with SOP with minimum
product terms and minimum variables)

20. Verilog
misII Minimizer
 multi level logic optimization algorithm
 Four transformation play a key role
1) Decomposition
2) Extraction
3) Factoring
4) Substitution
5) Elimination

21. Verilog
misII Minimizer
 multi level logic optimization algorithm
 Four transformation play a key role
1) Decomposition
2) Extraction
3) Factoring
4) Substitution
5) Elimination

22. Verilog
Example 1 (decomposition)
 Figure shows the schematic of function F, that is to be
decomposed interms of new nodes X and Y. The original forms
of F is described as F = abc + abd + a’c’d’ + b’c’d’
F = XY + X’Y’
X= ab
Y= c+d

23. Verilog
Example 2 (Extraction)
 Figure shows the Direct acyclic graph representing a function F,
G and H is to be decomposed in terms of node X and Y
F = (a+b)cd +e G=(a+b)e’ H=cde and X= (a+b) Y=cd
Before Extraction After Extraction

24. Verilog
Example 3 (Factoring)
 Figure shows the Direct acyclic graph representing a function F,
factored to identify Boolean factor in POS form.
F = ac+ad+bc+bd+e
Before Factoring After Factoring
F =(a+b)(c+d)+e

25. Verilog
Example 4 (Substitution)
 Figure shows the Direct acyclic graph F before the function G is
substituted in F
Before Substitution After Substitution
G =(a+b) F=a+b+c

26. Verilog
Example 5 (Elimination)
 The DAG in Figure represents the function F before the function
G is eliminated from it, where before elimination
Before Elimination After Elimination
F=Ga +G’b G=c+d and after elimination F=ac+ad+bc’d’

27. Verilog
Multi level Logic Network

28. Verilog
Multi level Logic Network

29. Verilog
Decomposition

30. Verilog
Extraction

31. Verilog
Substitution

32. Verilog
Elimination

33. Verilog
Final
Before
transfor
mation
After
transfor
mation

34. Verilog
RTL Synthesis
 RTL Synthesis begins with an architecture and converts a RTL
Code into a set of Boolean equation that can be optimized by
synthesis tool
 RTL Synthesis begins with an assumption that already set of
hardware recourses are available.
 Scheduling and allocation of resource have been determined
subject to constraint imposed by the resource of architecture

35. Verilog
High Level Synthesis
 High Level synthesis is called behavioural synthesis , has a goal
of creating an architecture whose resource can be scheduled and
allocated to implement the algorithm. (EX: algorithm for DSP)
 The Algorithm only describes the functionality of the circuit: it
does not explicitly declares a structures of register and datapath.
 A starting point of high level synthesis is an input-output
algorithm, with no details of implementation
 A synthesis tool executes two main steps: resource allocation and
resource scheduling

36. Verilog
High Level Synthesis
a) Parse Tree b) Data Flow Graph

37. Verilog
Synthesis of Combination Logic
 Some Verilog codes are not supported by synthesis tools.
Synthesisable combinational logic described by
1. A netlist of structural primitives
2. A set of continuous assignment statement
3. A level sensitive cyclic behaviour
4. Most EDA vendors do not support assign and deassign
procedural continuous assignment statement
 The design that is expressed as netlist of primitives should be
synthesized to remove redundant logic before mapping to the
technology

38. Verilog
Synthesis of Combination Logic
Pre optimized schematic
Optimized synthesized circuit

39. Verilog
Continuous assignment Statement

40. Verilog
Comparator Synthesis
module comparator #(parameter size = 2)
(output reg agtb, altb, aeqb, input[size-1:0] a,b);
integer k;
always @(a,b) begin; compare loop
for (k=size; k>0; k=k-1)
if(a[k]!=b[k]) begin
agtb=a[k];
altb= ~a[k];
aeqb=0;
disable compare loop
end
end
agtb=0; altb=0; aeqb=1;
end
endmodule
Algorithm:
Check for each bit of two
word for equality.
 If not equal compare
MSB to determine
greater or lesser.
 Synthesis tool correctly
synthesize to
combinational logic
from a level sensitive
behaviour containing
loop construct.

41. Verilog
Comparator Synthesis

42. Verilog
Synthesis of Conditional operator
module mux_logic(output y, input select, sig_G, sig_max, sig_a, sig_b);
assign y = (select==1) || (sig_G==1) || (sig_max==0)? sig_a: sig_b;
endmodule

43. Verilog
Priority Structure
 A case statement implicitly attaches higher priority to the first
statement than to the last statement.
 If statement implies higher priority to the first branch than the
remaining conditional branch statement.
 If case statements are mutually exclusive, synthesis tool, will treat
them as though they have equal priority and will synthesise MUX
rather a priority structure.
 If statement will synthesize to a MUX structure if the branching is
specified by mutually exclusive conditions

44. Verilog
If statement without mutually exclusive
condition
module mux_4pri(output reg y, input
a,b,c,d, sel_a, sel_b, sel_c);
always @(*)
if (sel_a==1) y=a;
else if (sel_b==0) y=b;
else if (sel_c==1) y=c;
else y=d;
endmodule

45. Verilog
ALU
module alu_z1(output aluo, input[3:0] a,b,
input[2:0]op, input e);
reg [3:0] alur;
assign aluo=(e==1)?alur:4b’z;
always@(op,a,b)
case(op)
3’b001:alur=a|b;
3’b010:alur=a^b;
3’b110:~b;
default:alur=4b’0;
endcase
endmodule

46. Verilog
Exploit don’t care condition
module alu_b0(output aluo,
input[3:0] a,b, input[2:0]op, input
e);
reg [3:0] alur;
assign aluo=(e==1)?alur:1'b0;
always@(op,a,b)
begin
case(op)
3'b001: alur=a|b;
3'b010: alur=a^b;
3'b110: alur=!b;
default:alur=4'bx;
endcase
end
endmodule
An assignment to x in a case OR
if statement will be treated as
don’t care condition in synthesis

47. Verilog
ASIC Cells and Resource Sharing
 ASIC cells library usually contain cells that are more complex than
combinational primitive gates. (Most libraries contains FULL
ADDER cells)
 The synthesis tool exploits the available model or builds another
circuit depending on the designers verilog description.
 The Tool must share the resources as much as possible to minimize
the needless duplication of circuitry

48. Verilog
module add_4(output[3:0] sum, output c_out, input[3:0] A,B, Cin);
assign{c_out, sum}= A+B+Cin;
endmodule

49. Verilog
Synthesis of sequential logic with latches
 Latches are synthesized in two ways.
 Intentionally
 Accidentally
 Latches that are synthesized accidentally waste silicon and may
compromise the functionality of the circuit.
 A continuous assignment using conditional operator with feedback
will synthesize into a latch
assign d_out=(Cs==0)?(we==0)?d_in:d_out:1’bz;
If Cs=0 then if we=0; d_in is transferred to d_out,
If we = 1; d_out=d_out ie latched mode
If Cs=1 then d_out is in high impedence condition.

50. Verilog
Synthesis of sequential logic with latches
 We have discussed three ways to describe the combinational logic:
Netlist of primitives, Boolean Equation by continuous assignment
statements, and level sensitive cyclic behaviour. (can all style to a
circuit with latches?).
 Feedback free netlist of combinational primitives will synthesize
into a latch free combinational logic (Eg: Cross coupled NAND
gates)
 A continuous assignment that uses conditional operator with
feedback will synthesize a latch.
•A feedback free netlist of combinational primitives will synthesize in to
latch free combinational logic

51. Verilog
Accidental Synthesis of Latches
module OR_BEHA#(parameter len=4) (output reg y, input[len-1:0]x_in);
integer k;
always @ (x_in)
begin:check_1
y=0;
for(k=0;k<=len-1; k=k+1)
if(x_in[k]==1)begin
y=1;
disable check_1;
end
end
Endmodule

52. Verilog
Accidental Synthesis of Latches
module OR_BEHA#(parameter len=4) (output reg y, input[len-1:0]x_in);
integer k;
always @ (x_in[3:0])
begin:check_1
y=0;
for(k=0;k<=len-1; k=k+1)
if(x_in[k]==1)begin
y=1;
disable check_1;
end
end
Endmodule

53. Verilog
Synthesis of Sequential logic with Flip-Flop
•A variable that is
referenced within an Edge-
sensitive behavior before it
is assigned Value in the
behavior will synthesized as
the output of a flip-flop
module swap(output reg d_a, d_b;
input s1, s2, clk)
always @(posedge clk) begin
if(s1) begin d_a<=0; d_b<=1; end
else
if(s2) begin d_a<=1; d_b<=0; end
else
begin
d_a<= d_b;
d_b<=d_a;
end
end
endmodule

54. Verilog
synthesis of Sequential logic with Flip-Flop
module d_reg( output reg [3:0] data_out, input [3:0] data_in, input clock,
reset);
always @(posedge clock, posedge reset)
begin
if (reset==1’b1)
data_out<=4’b0;
else
data_out<=data_in;
end
endmodule

55. Verilog
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