Ananthprofilepln

Ananth Chellappa
Analog Design Engineer
Professional Profile

Contents

Summary

Work experience

Examples of Initiative and Innovation

Project details

Skills

Patent Applications

Education

Summary

Graduate of IIT(M) and Georgia Tech with 10 years
industry experience at Maxim Integrated Products,
Texas Instruments and Analog Devices

Analog designer with exposure to PLL, ADC, DAC
and switching-regulator design

Good with tools, scripting (perl/unix) and
documentation; recognized by peers for speed,
thoroughness and proactivity

Fast learner, time-sensitive person, motivated to
contribute

Work Experience

Jul 2009 – present : Maxim Integrated Products (Phoenix, AZ)

Oct 2005-Apr 2009 : Texas Instruments (Dallas)
- bandgap references, amplifiers, linear-regulators, switching-regulators,
oscillator

Jan 2005 – July 2005 : Analog Devices (Tucson, AZ)
- autozero opamp, current reference, low-power clock-multiplier PLL

Aug 2001 – Dec 2004 : Graduate Research Assistant at Geogia
Tech
- high-speed optoelectronic receiver (TIA + limiting amp)

July 1998 – Mar 2001 : Texas Instruments India
- PLL, pipeline ADC, DAC/SCF, r-string DAC, SAR ADC

Initiative and Innovation
Issue Action
Custom digital cells (weak, but
good for area) library lacks the 2x4
decoder used in the 4x16 decoder
of the DAC in the buck-regulator
reference section
Drove standard-cell library team to provide this
cell in a new release; impacts all of Maxim
Clock generator used to generate 6
different clock phases uses 22 D-
flip-flops – huge area
Redesigned to use only 6 D-flip-flops and moved
to custom cells to save more than 50% area
Reference bias-current takes about
60 us (nom) to reach final value
Redesigned (moved from single-stage amp with
large comp-cap to 2-stg amp with small comp cap
amd miller-comp) to save area and reduce time-to-
final to about 2.5 us worst-case and achieve better
PSRR without VCC filter (25 pF)

Issue Action
To talk to the chip (on the bench)
through the proprietary 3-pin test-
interface, designers are using a
board with push-buttons to send
the required pulses. While this
accomplishes the result of moving
from register to register and
sending required data, it does not
provide visual feedback and the
ability to automate (through
macros). The designer must
remember or write down what data
has been sent and what state he is
in
Designed a new board with simple level-shifters
(own expense) and interfaced the chip to the PC
through an Arduino MCU board and wrote the
GUI on the PC with Autohotkey (open-source
Windows scripting utility) – everything done from
scratch. This enabled fast bench-correlation and
macros to be written to do a force-trim on about
200 samples of a new chip (by the Test-engineer
using the designer’s setup) to sample the customer
very early. Also used on a class-D audio-power-
supply boost-regulator project. Both the
MAX8989 have been in production successfully
This is an example of doing what needs to be done to achieve success. In the context of
my goals related to IC design, doing such interfaces is not a specific interest of mine

Issue Action
When running LPE (parasitic back-
annotated) simulations, we find
movement on sensitive nodes.
Designers look manually in the cap
file for coupling caps to aggressors,
but, sometimes, this coupling can
be secondary coupling through
other “quiet” nodes
Wrote an ocean script that would look at all
available waveforms in the simulation result and
arrange nodes based on amount of movement
during the problem window. Helped us save time
in locating aggressors and address layout issues
There are thousands of nodes and
we’d like to save all of them for
debug purposes. However, if we
save waveforms with compression,
then we lose accuracy – which is
important for the critical signals
Moved to spectre version 12 so that all waveforms
could be saved but only selected waveforms could
be saved with compression to yield manageable
plotfile sizes

Issue Action
MAX77387 – the flash-LED current-
regulator signals the digital the boost output
voltage is not high enough and the digital
commands the boost output higher – but, the
output voltage does not match the no-load
voltage in the load-line architecture. So, the
digital might decide that the boost-output is
aleady “too-high” and not increase it further
In this application, the load on the boost
is well defined – it is the DAC setting of
the Flash-LED current-regulator. This
information can be used to add the
required adjustment at the output of the
error-amp of the boost and enhance load-
regulation without changing the AC loop-
gain and worrying about stability. This is
in the production version
To check for floating nodes, designers run
the checker and then manually go through
report file and manually locate each of
hundreds of nodes in the schematic
Did the first version and then handed off
to EDA a tool that now lets designers
specify the report file and then just hit a
“next” button in Cadence to be taken to
each node in the schematic automatically

Issue Action
The simple R-string DAC with LSB taps on
top has a transient non-monotonicity issue –
when you traverse MSB codes, you
immediately go from the min to the max
switch on the LSB RDAC – on top, but the
voltage propagation from the MSB DAC on
the bottom takes time – resulting in a glitch
on the output
Add feedforward caps from a few tap
points in the MSB DAC to considerably
alleviate the problem to the point that the
buck-regulator cannot respond to the
glitch because it is so narrow
In meetings, designers tend to talk about
circuit details based on their familiarity with
the result that others cannot follow.
Capturing the ideas with Visio of Cadence
takes time
Use a sharpie marker to produce good
enough, and clear-enough plots that can
be scanned and put up on the projector.
Not an original idea, but my adoption of
it has since seen my peers follow suit

Issue Action
Was new to Maxim and my first
project was on Viewlogic – which is
a very inferior design platform
compared to Cadence. A translator
existed to migrate the data to
Cadence, but no one had used it
Learned the use of the translator, migrated data to
Cadence and pushed management for layout
resources to run LVS to fix translation errors in
the translated schematics. This allowed this
design to be respun on two separate projects
which have since resulted in significant revenue
for the group
Running testmode simulations is a
task no one looks forward to and
usually, on 2nd
and 3rd
passes, we
find bugs in testmodes (on silicon)
because they weren’t simulated
Changed workflow to generate a push-button
ocean script for every simulation and then created
a master perl-script that could stich together an
arbitrary number of simulations, run them and
also post-process simulation results either by
using ocean to look at plots or perl to look at
simulation log output and then report pass/fail

Issue Action
There was no good corner
simulation setup and designers were
running the corners they assumed
would be the worst-case
Learnt the use of the new Maxim in-house tool
and held two training demos to train my peers;
This tool is now widely used at our design center
Sometimes it is necessary to access
a signal buried within the hierarchy
from the testbench level. In the past,
we have had to propagate this node
to the top-level by putting pins on
each cell in the hierarchy
Found deepprobe on the Cadence support site,
learnt its use and fanned out to the team. It is
currently widely used for different purposes –
triggering faults, injecting offsets, speeding up
startup in simulations, etc

Issue Action
Customer (Infineon) had supply
volage to the PA step-down-
regulator (MAX8989) as high as
5.5V. In this condition, though they
preferred to have the buck in
dropout to avoid switching noise,
their DAC (driving the reference
(REFIN) input could not produce a
high enough voltage to make this
happen. So they failed the RF spur
test
Proposed a new feature wherein a REFIN higher
than 1.8V would send the buck and bypass-LDO
into very high-gain mode (effectively
guaranteeing dropout) to prevent switching.
Normal operation where the buck-output was
being modulated by REFIN for efficiency reasons
did not require REFIN above 1.5V
This feature was in the final production version

Block Design Summary
Block Schematic only Working silicon Production Institution(s) Remarks
PLL 1 2 TI-I, ADI Maneatis style
Bandgap 2 1 TI-Dallas 2 precision
designs
Autozero amp 1 1 ADI, TI-Dallas
Sw-cap gain
stage 2 1 TI-I, TI-Dallas 1 involved amp
design
Performance
linear amp 1 TI-Dallas TIA for TS AFE
Linear
regulator 2 2 1 TI-Dallas
Switching
regulator
1 1 TI-Dallas Reuse, no core
changes
2 Maxim
Detailed design
of boost; reuse
of hyst-buck
Voltage buffer 2 2 TI-Dallas
ADC 1 TI-I Recyclic
DAC 1 TI-I R-string

Project Detail – Dual Phase Boost

Sept. 2010 to Nov. 2011 with diversions from re-spins of
MAX8989 PA buck and MAX77693 – Maxim’s PMIC in
the Galaxy III

Target application – camera flash-LED driver. Motivation :
2 inductors carrying half the current each carry ¼ the energy
of a single inductor carrying all of the current – results in
significantly lower footprint – 70% smaller than competing
1.5A solution

Design activity influenced all blocks; Lowest minimum-
ON-time boost designed within the group and only one with
a true PWM mode; world’s smallest 2A boost solution

Project Detail – Touchscreen AFE

July 2008 – Jan 2009. 90 nm CMOS.

ASIC device with digital owned by customer

Joined team July 2008 to work on new device. Silicon for
current device in eval/debug

Customer – large consumer electronics co.

Initially worked on internal LDO for system oscillator. Did
preliminary design (from scratch). Later ported (in-progress)
a 65 nm design from another group

Soon began work on RX architecture, filter topology and
transimpedance amp (TIA) frontend

• Worked on internal (on-chip cap) LDO for system oscillator
• Designed transimpedance amp frontend for new device
• Drove RCA of LDO high-temp failure
• RCA of LDO transient issue; LDO fixes for new device
• Explained yield loss in RX-SNR test @ 100 kHz for current
device
• Drove RCA of 0.2% of units powerup fail in system
• Identified misc improvements to help area/power
• Misc tasks to support project

• New TIA design supported 4x original frequency
• Lower noise at same power obtained by increasing
VDSATs of active load devices and topological
modification of first stage
• VREF is divided down version of the ANA LDO
voltage. Due to nature of the LDO design, noise
depended on mismatch, and flicker noise was
significant at 100 kHz – explained the loss of yield in
the SNR test at 100 kHz

Project Detail – Notebook Charger
• 2Q 2008; Joined project which was significantly behind
schedule
• Took over system oscillator from another resource; found
that resistor area in the circuit could be reduced substantially
• Helped co-worker design a low-offset amp
• Handled entire verification of supervisory blocks and high-
voltage level-shifter
• Key role in top-level simulation efforts

Project Detail – GPS PMIC
• 2Q 2007 – 1Q 2008
• Aggressive schedule; reuse of catalog blocks; chip: pwr
mux, battery charger, resistive touchscreen controller,
buck regulators, white LED boost regulator, LDOs
• Complete ownership of buck-regulators (handled import,
verification, minor tweaks, test-plan)
• Designed thermal shutdown circuit (from scratch) and
testmux
• Eval/debug of silicon; metal fixes
• Key role in top-level simulations

Project Detail – GPS PMIC

Buck regulators (Vin 1.8-6.5V, Vout 0.7-3.3V, 6-bit
programmable, 2A max load, 2.2 uH, 4.7-10 uF) were voltage-
mode; efficiency ~87%; considerable digital content

First-pass silicon did not permit system oscillator to be trimmed
because clock was not mux'ed out by the digital. Shipping of
untrimmed units during sampling phase led to
undesirable/upredictable behavior in the field

Buck regulators would delay 384 clock cycles (to allow internal
bias nodes to be ready) before beginning switching activity. This
deterministic delay was used to trim the system oscillator. This
workaround permitted about 800k units to be shipped before 1P1
silicon was available

Project Detail – DSC PMIC
• 1Q-2Q 2007
• Cost-reduced (area efficient) version of a production
PMIC for digital still cameras
• Chip contained boost regulator, 1 buck regulator,
backlight LED boost regulator, LDOs, 2 buck-boost
regulators
• Taped out as a test-chip. Only partial silicon
evaluation
• Worked on buck-boost and top-level simulations

Project Detail – DSC PMIC
• About 5% of units had an issue with the buck-boost regulators. In
light-load, inductor current would randomly go negative and
Vout would drop and system would reset
• It was found that these units had the PFM-PWM transition point
set very high. At test, units would be trimmed to set this
transition to a value where the problem was not observed. Some
yield loss remained on units that could not be trimmed acceptably
• Was also found that the variation (across units) of this transition
(pre trim) was very wide
• Traced this variation to the Ios of the current-sense amp;
reduced it in the new design

Project Detail – Scanner AFE
• 3Q 2006 – 1Q 2007
• Aggressive schedule; process was new to the team
• Chip contained 240 MHz osc for USB2 data rate, 12 bit
ADC (2 MSPS), CDS-PGA interface to CMOS/CCD image
sensor, offset DAC, LVDS, LED driver
• System used bare die – no trim available (issues with both
EEPROM and poly fuse)
• Designed bandgap reference, reference buffer, 1.5V buffer,
pipeline ADC differential reference buffer and CDS-PGA
amp (scaled down for use as pipeline-ADC residue amp)

• Bandgap reference needed to be fully-isolated. PNP based
topology exists, but better curvature performance available
from an NPN bandgap
• Known fully-isolated NPN bandgap has non-trivial startup –
difficult to sense the NPN current – and some corners
showed oscillations during startup
• Developed new topology to meet requirements
• Designed for statistical variation (no trim)
• Bandgap noise filtered with RC filter; buffers designed for
noise; total integrated noise at ADC reference output (1 uF
caps) was 50 uV rms

• CDS-PGA amp was a two-stage design due to
required voltage swing
• Design used cascode compensation and barely met
settling requirements but exceeded THD
requirements
• However, power consumption was excessive
• Redesigned prior to tapeout with Miller
compensation by another resource

• Considerable wafer probing effort after first silicon to
determine cause of bandgap not powering up
• Traced to a software error in mask generation. N-wells of
PMOS devices shared with NPN collectors resulted in
NLDD being applied – which resulted in very large Vth for
these PMOS devices in these few circuits
• Re-tapout with corrected masks gave working silicon
• 100% revenue share for TI during year 1 after Wolfsen failed
to deliver on time

Project Detail – Display PMIC
• 4Q 2005 – 2Q 2006; targeted at laser projection display
system; co-designed with customer
• Chip contained switching regs, linear regs, charge pump,
piezo driver, fan controller, RF section – video interface,
XTAL oscillator, low-offset amps, laser drivers
• Designed several blocks from scratch and also did a
feasibility study to ensure laser driver speed could be
attained in the 0.6 um process
• First silicon worked, no issues in blocks designed personally.
However, project was put on hold after customer was
acquired by Motorola

Project Detail – Display PMIC
• Designed bandgap reference to be low noise (~600 uA IQQ);
bandgap buffer, reference current generator, 2 linear
regulators (1.2V and 3.0V) – also low noise
• Linear regs used internal zero compensation. Error amps
were bipolar input-pair to eliminate flicker noise
• Designed <50 uV Vos autozero opamp for use in green laser
temp stabilization loop using topology similar to OPA335.
Starting point was OPA333 which uses chopper stabilization.
Made substantial modifications to input and output stages,
but topology was preserved
• Also designed supply-monitor block (from scratch), testmux
(reuse, customization), I/O buffers (reuse, verification) and
laid out IREF block

Project Detail – ADI Internship
• Targeted <10 uV Vos, achieved ~20 uV worst case, classic
autozero scheme. Explored a scheme intended to give a low-
noise AZ amp, later proved invalid
• Designed a temperature insensitive current reference by
imposing VPTAT upon a resistor with 3333 ppm TC made
using the POLY and NWELL resistors
• Designed a simple low-power (~20 uA) PLL clock-
multiplier using the Maneatis scheme without which the chip
would have uncoupled oscillators
• All blocks at schematic only – no silicon

Georgia Tech Research
• Goal was to design an optoelectronic receiver with acceptable
BER at 10 Gbps with 10 uA p2p signal current from a
photodiode using a 0.18 um CMOS process without inductors
• Concept was to use resistive degeneration to get an inductive
peaking effect to improve bandwidth
• Individually laid out and submitted one 0.5 um CMOS chip
with legacy receivers and demonstrated 400 Mbps performance
in the lab
• Receiver was a transimpedance amp (TIA) which converted
the single-ended photodiode current into a differential voltage,
followed by low-gain high-BW stages and a 50 ohm driver (to
the BERT)

Project Detail - TFP7403
• Flat panel display timing device (3Q 2000 – 1Q 2001)
• Designed input and output PLLs (VCO/PFD/etc already available) per
the Maneatis scheme (JSSC '96)
• Charge-pump current is ratioed to the VCO cell current and loop-filter
buffer size is ratioed to the VCO cell size. This gives loop bandwidth
to reference frequency to be independent of process and also constant
damping factor
• Design involves picking these ratios for optimal bandwidth and
acceptable phase margin
• Macromodeling done to speed up simulations, linear modeling done to
estimate phase margin, added additional passive filtering to reduce
reference spur
• Later, ported VCO to a new process

Project Detail - AIC12
• 16-bit 26 KSPS Delta Sigma Analog Interface
Circuit in 0.35 um CMOS (1H 2000)
• Delta Sigma modulator output was 4 level. DAC +
SCF was a fully-differential single-opamp ckt that
implemented a simple switched-cap filter and DAC
(split sampling caps)
• Also worked on an 8 ohm speaker driver during
early phase of the project

Project Detail – Recyclic ADC
• Designed a 14-bit recyclic ADC reusing components
from the TLV1562 (1.5bit/stg pipeline ADC)
• Changed gain-stage to Steven-Lewis style (input
sampled on feedback cap also – so that feedback
factor is 1/2 instead of 1/3 – higher loop bandwidth
• Designed error-correction logic
• Recyclic ADC is basically a single-stage pipeline
ADC – so the latency is similar to a SAR

Project Detail – DSC AFE TLV977
• Designed (reuse, modifications for speed) resistor-
string DACs for use in offset cancellation loop
• Did complete hookup of the 12-bit 18 MSPS pipeline
ADC. HDL coding, synthesis and autolayout of the
error-correction logic
• Modeled the ADC in VHDL and later modeled the
full chip in VHDL to verify top-level hookup
• TI-India, 1999

Project Detail – THS8133 and Remix
• THS8133 – 10-bit 80 MSPS current-steering DAC.
Coded the digital interface in VHDL (1998)
• Remix – 10-bit 6 MSPS SAR ADC testchip –
coded/synthesized/autolayed out digital interface
(1998)

Skills/Strengths
• Analog circuit design
• Analog sub-system (PLL/ADC/DAC/etc) design
for moderate performance
• Analysis – circuits and root-cause
• Tradeoffs – area/power/speed/noise
• Scripting – perl/shell/skill
• Veriloga modeling / macro-modeling
• Tools

Patents
• Fully-isolated bandgap reference
• Method of sensing PTAT current in a fully-isolated
bandgap-reference
• Fully-isolated temperature-threshold detector
• Low-voltage bias generator not requiring
compensation capacitance (pending)
• Low-voltage, low-area bandgap-referenced power-
on-reset circuit

• In October, focus shifted completely to debug and RTP of
current device; new development put on hold
• LDO failure at high-temp was due to use of a 1 nA current
to generate a delay in transitioning to full-strength during
startup to limit inrush current. 1 nA current was vulnerable to
leakage
• Conceived and implemented bench tests to collect data
supporting the hypothesis and give the customer confidence
in the root-cause explanation of this issue which was gating
RTP. Interfaced with modeling team to get true worst-case
model for leakage. Also developed the metal fix for the issue

• Worked on LDO transient issue debug (RCA of large spike
on LDO_DIG output when waking up from sleep mode) –
explained by asymmetric charge/discharge strength of stage
driving pass device. Not a showstopper; addressed on new
device design with a parallel fast-mode that detected and
corrected the situation with about 1 uA additional IQQ
overhead
• For new design, also achieved the strength transition delay
without use of a tiny current and without area overhead by
eliminating a binary-2-therm trim decoder

• Last minute issue gating RTP was a low-rate (0.2% of units)
powerup failure in the system
• Aggravated at low temp (failing unit would pass at high
temp). As temp increased, unit would pass and DIG LDO
voltage ramp rate was not deterministic
• Explained observations based on fact that hysteresis was not
used in implementing the powerup threshold (no noise
immunity) (comparison of bandgap with Vbe)
• Statistics of the fail explained by showing the level-shifter
powerup value (with VDDIN absent (DIG LDO)) was HI
only 80% of the time (mismatch), and required trim input to
the bandgap reference for the fail

• Developed spreadsheets that helped RX architecture
definition
• Extensive perl/shell scripting developed to mimic a test
prescribed by the customer to generate a large number of
datasets from transient simulation (with transient noise) to
validate architecture
• Identified opportunities to save power in the design by
improving RX components (VMID buffer in the SAR
ADC, antialias filter amp (class AB o/p stage systematic
mismatch))
• Also found a way to save area in the HF Osc trim DAC by
sharing nwells in the cross-coupled latches

Fully-Isolated Design

Definition – no node in the circuit (with the
exception of supply and GND) is permitted to touch
the (noisy) substrate

When the process provides a vertical NPN with high
beta, usually the collector is an n-well – which
touches the substrate

Therefore, a bandgap reference topology such as the
Brokaw bandgap, in which the collectors of the
NPNs are used in the circuit, is not permitted

Trajectory at Texas Instruments (Dallas)

Hired into Custom Mixed Signal group in Oct 2005

Moved to High Performance Analog (HPA) group in
July 2008 (project had been outsourced to HPA by
ASIC)

DSPS-R&D begins taking over project in November
2008

Restructuring in Dec 2008 led to resources working
on the project being moved to ASIC

Majority of project team affected by RIF in 2009

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