EELE 5331 Digital ASIC DesignLab ManualDr. Yushi Zhou.docx

EELE 5331: Digital ASIC Design
Lab Manual
Dr. Yushi Zhou
Department of Electrical Engineering
Lakehead University
Thunder Bay, Ontario, Canada
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 MOSFET Devices and Layout Tutorial . . . . . . . . . . . . . 4
2.1 Prepare For Schematic . . . . . . . . . . . . . . . . . . 4
2.2 Perform Simulation . . . . . . . . . . . . . . . . . . . . 7
2.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Layout Veri�cation . . . . . . . . . . . . . . . . . . . . 17
2.5 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.6 How to understand DRC error report . . . . . . . . . . 26

3 CMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 Design speci�cations . . . . . . . . . . . . . . . . . . . 27
3.2 Lab Procedure . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1
EELE5331:Digital ASIC Design [email protected]
1 Introduction
This lab manual is an essential components of EELE5331:
Digital ASIC
Design, o�ered by Dr. Yushi Zhou. The lab works consists of
schematic
entry, symbol generation, pre-layout simulation, layout,
physical and logic
veri�cation, extraction and post-layout simulation for the
design. All the
students are required to submit individual lab report before the
deadline.
All reports must be typed and professionally prepared. The
content that
needs to be included in the report are given at the end of each
lab. There

are total three labs, and each part will be released before the lab
starts.
• Lab 1: MOSFET devices and layout tutorial
• Lab 2: CMOS Inverter
• Lab 3: CMOS Digital Logic Circuits
It should be noted that the students are not limited to the
assigned lab
time, which may not be enough to complete the lab. Students
are expected
to work on the lab during their free time if that case is required.
You may
use remote log-in to complete the labs.
TSMC CMOS 180 nm technology process design kit (PDK) is a
1-Poly,
6-Metal technology, with a maximum supply voltage of 1.8 V
for thin oxide
devices and 3.3 V for thick oxide devices. This process is
suitable for design-
ing analog, digital, RF and mixed-signal circuits and systems.
In this course,
all the labs are designed based upon CMOS 180 nm process.
The computer-
aided design (CAD) tools that are adopted in this course are

from Cadence
Design Systems for the purpose of schematic entry, simulation,
implemen-
tation and veri�cation. The Cadence custom IC design platform
provides
a graphical interface for various stages in the design �ow. An
overview of
the design �ow and which tools are involved in each stage is
shown in Fig.1.
As you may notice that there are loops, indicating iterative
procedures. For
instance, if the physical layout does not pass design rules check
or LVS check,
Page 2
the modi�cation of the layout cannot be avoided. The worst
case happens
when the post-layout simulate presents the functionality defects
due to the
careless design at the �rst step. In such a case, the schematic
design has to
be changed, which has signi�cant impacts on the procedure.

Figure 1: Design Flow
Page 3
2 MOSFET Devices and Layout Tutorial
In this section, a short tutorial of how to use Cadence to
complete the layout
of a single transistor will be given. In particular, you will
investigate the
physical attributes of the MOSFET, including the second order
e�ects. The
I-V curve will be used to compare the results of pre-layout and
post-layout.
2.1 Prepare For Schematic
To start Cadence, there are a few steps that you need to
complete. Please
refer to the Log-in-steps, posted on the course website.. Once
you have suc-
cessfully log-in, you will be led to the home directory as
/home/user. A
good starting point will be creating a design folder, i.e. type
mkdir design.
A new folder, "/design", is created. You are strongly

recommended to have
a Linux/Unix reference by hand. In particular, some most often
used com-
mands, e.g. cd, list, echo, etc., should be familiarized. Now type
cd design.
Then type /CMC/bin/goCadence. A new window will pop-up.
Scroll down
to the bottom. Choose 180 nm as shown in Fig. 2 a). icfb
interface in Fig.
Figure 2: a) Start window b)icfb
Page 4
2 b) is the design framework (DFII) front-end for the CIC
platform. From
icfb you will be able to access all the tools for schematic
capture, symbol
editing, simulation, layout, DRC and LVS checking, and
extraction.
Next step is to create a working library, which must be attached
to the
180 nm technology so as to create the link between the design
library and the

technology library. To do that, go to icfb->File->New->Library.
Name
the library lab1, and under Technology File choose Attach to an
existing
tech�le and press OK. In the popup window, choose cmosp18
from the
drop-down list beside Technology Library.
To create a schematic cellview, go to icfb->File>New-
>Cellview.
Change the Library Name to lab1, and make the Cell Name
nmos. Leave
the View Name and Tool as is. An empty Virtuoso Schematic
Editor Fig. 3
window will open.
Figure 3: Schematic editor
Using the knowledge that you learned from the class,
characterize a
NMOS transisor. Further, you will create a similar schematic
for the PMOS
transistor to obtain the same parameters. This will be done by
biasing the
Page 5

transistor at a �xed voltage, VGS, and observing the changes in
the drain
current, IDS, in response to variations in the drain voltage,
VDS. This pro-
cess will be repeated for several bias points to produce a family
of IDS -
VDS curves. In this lab, we will need 5 Instances: 3 DC Voltage
sources,
1 Transistor (NMOS or PMOS), and 1 Ground. To add an
instance to the
schematic, �nd the instance button in the toolbar on the left
side of the
Virtuoso Schematic Editor (or press I). The instances in the
schematic are
summarized in Table 1. Refer to Fig. 4 for how to add instances
and draw
Table 1: Instances
Library Cell View Parameter
cmosp18 nfet symbol width = 1u, length = 180n
analogLib vdc symbol DC Voltage = v1
analogLib vdc symbol DC Voltage = v2

analogLib vdc symbol DC Voltage = 0
analogLib gnd symbol
wires. To change the parameters of an instance, middle-click the
instance
and choose Properties(or select the instance and press Q). The
values v1 and
v2 are variables, which will be used later in the simulation. In
order to pro-
duce the I-V characteristics of the transistor at a �xed bias
point, the drain
voltage must be varied using either Parametric Analysis or DC
Analysis.
This will be explained in further detail when setting up the
simulation.
In general, you would normally need to create a symbol of the
circuit
being simulated. One of the example is when you are doing
post-layout
simulation, symbol creation will be utilized to distinguish
pre/post-layout
simulation. Since there is only one device, NMOS, in the
circuit, it is not
necessary to create the symbol.

Figure 4: NMOS test circuit
2.2 Perform Simulation
In this section, you will learn how to verify the designed circuit
by simulation.
The Virtuoso Analog Design Environment (ADE) is the
interface used for
simulation. To launch ADE, go to Tools->Analog->Environment
as
shown in Fig. 5. Since your schematic has variables, you will
need to add
Figure 5: ADE interface
them to ADE and assign values to them. Add the variables by
going to
Variables->Copy From Cellview and then they will be listed in
ADE
under Design Variables. To assign a value to a variable, double
click on the
variable and input the desired value in the Value (Expr) �eld.
Assign values
Page 7

of 1.8 and 1 to v1 and v2 respectively(v1 is VDS, and v2 is
VGS).
The following part is the key con�guration for a successful
simulation.
The mode library, which is basically a spice model �le, must be
included
properly. The simulation will fail otherwise. in ADE window,
please do:
• Setup->Simulator/Directory/Host...
� Simulator: spectre
• Setup->Model Libraries ...
� Model Library File:
/CMC/kits/cmosp18.5.2/models/spectre/rf018.scs
section=tt
• Setup->Simulation Files ...
� Include Path: /CMC/kits/cmosp18.5.2/models/spectre/
Once these con�guration is done, the simulator is able to �nd
the correspond-
ing spice model from the library that is provided from the
foundry.

Parametric Analysis
Parametric analysis allows you to sweep one of the parameters
on an instance
over a given range (or speci�c values) when performing a
Transient/AC/DC/etc.
To obtain the I-V characteristics, we will use Transient analysis
for a period
of 1ns (since all the sources and outputs are DC, the time is
really irrelevant).
To create a transient analysis in ADE, go to Analyses->Choose.
In the
new window, choose tran as Analysis and set the Stop time to
1n. To con�g-
ure the parametric analysis, in ADE go to Tools->Parametric
Analysis.
In the Parametric Analysis window, go to Setup->Delete Range
Speci-
�cation and choose Sweep 1. Now enter the variable name as v2
(i.e. the
voltage applied at the gate) and in the Add Speci�cation list,
choose Inclu-
sion List and enter the values 0.6 0.9 1.2 1.5 1.8. These will be
bias points

for the parametric sweeps. Now go to Setup->Add New Variable
To
Page 8
Bottom, set the variable name to v1 (i.e. the voltage applied at
the drain),
From and To to 0 and 1.8 respectively, change Step Control to
Linear Steps
and set Step Size to 0.1. Ensure that v2 comes before v1 in the
Paramet-
ric Analysis setup. Enable Sweep 2 by Selecting it and disable
Sweep 1 by
un-Selecting it.
Before simulating, we need to add some outputs that should be
evaluated
upon completion of the simulation. Since we are interested in
the drain
current, in ADE go to Outputs->To Be Plotted->Select On
Schematic
and choose the drain terminal (red square at the drain of the
transistor).
Also, in ADE go to Outputs->Save all. Check Select device
currents all.

Now when the simulation �nishes, the waveform of the drain
current over
the simulation time will be plotted. In the Parametric Analysis
window, go
to Analysis->Start - Selected to begin the simulation. Now only
v1 will
be swept, and v2 will hold the value speci�ed in ADE.
The waveform viewer is called WaveScan. A new WaveScan
window will
pop-up showing the drain current of the NMOS transistor under
the current
VDS and VGS conditions. To obtain the I-V characteristics of
the NMOS
transistor, the outputs to be evaluated have to be modi�ed.
Plotting the
current through the drain terminal will show IDS =
f(VDS,t)|VGS=fixed, how-
ever we want a plot that is independent of time. To do this, we
must take a
time-average plot. In ADE, go to Tools->Calculator to launch
the Wave-
form Calculator. In the Calculator window, deselect clip graph
selection,

and choose it under the tran tab. The schematic window will pop
up and
click on the drain terminal of the NMOS transistor. Now go
back to the
Calculator window and click on average. Go back to ADE, go to
Outputs-
>Setup,and click on New Expression, then click Get Expression
and
the Expression �eld will be �lled with the expression that was
in the Calcu-
lator. Give a name to the expression such as I-V Characteristics
of NMOS,
then click OK. Under Outputs in ADE, click on the previous
output for drain
current and press the Delete button so that only the I-V
Characteristics of
NMOS will be plotted. Since the simulation data already exists,
you do not
Page 9
need to redo the simulation. Press the Plot Outputs button on
the right side
of ADE. The �nal waveform is shown in Fig. 6. Note, add

marker to each
of the line. Now you should get the expression for plotting I-V
characteris-
tics. You can generate a family of curves showing the I-V
characteristics at
di�erent bias voltages. In the Parametric Analysis window, go
to Analysis-
>Start to begin the simulation. Now v1 will be swept for each
value of v2
speci�ed in the Inclusion List. Fig. 6 shows the parametric
con�gurations
and simulation results.
Figure 6: Parametric con�guration and simulation results
Since we have done a simulation, it is time to save the current
con�gu-
rations in ADE window. Go to Session->Save State ... and in the
Save
As �els, �ve a name with information that you can recall later.
However,
Parametric Analysis will not be saved.
DC Analysis(preferred)
To get IDS vs. VDS curve, DC analysis is much simpler as
compared with

that of Parametric Analysis. Uncheck Enable in tran, and click
dc. Under
DC Analysis, select Save DC Operating Point, and under Sweep
Vari-
able, choose Component Parameter. Click Select Component
and choose DC
source that is connected to the drain of the MOSFET. Then in
the new win-
dow select the �rst item, dc, and press OK. Under Sweep
Range, set 0 to 1.8,
and Sweep Type to linear with step size, 0.1. Click Netlist and
Run in ADE
Page 10
window. This time you can not plot the terminal currents from
dc analysis
directly. To view the dc terminal currents, in ADE go to Tools-
>Results
Browser. In the Results Browser window, in the right hand pane
double
click on dc-dc to open the results of dc analysis, then double
click on M0/d

to plot the I-V characteristics. M0 corresponds to the name of
the device
from the schematic, and ids corresponds to the parameter being
plotted.
The Results Browser is a very powerful tool, as it allows you to
view all the
device parameteres, such as capacitances, currents,
transconductances, and
voltages, that are evaluated during a simulation. Note: you may
not be able
to see the results for some unknown reason for the �rst time
run. So, if this
happens, please try to run DC analysis a few times more. Then,
the saved
data should be appeared in Results Browser. If the issue is still
there, for
example, only variables are in the results window. Please try the
following:
• In Results Browser window, go to File->Clear, then in the
Location
drop-down menu, select the path corresponding to your
cellview. The
simulated data should be available now.
There are some other functions that provide your observability.
For instance,

in ADE, go to Results->Print->DC Operating Points, then
choose the
MOSFET in the schematic editor. A new window showing all
the parameters
under the �xed voltage, v2=1V, will pop-up. To plot I-V curve,
a simple
Parametric Analysis is required. Follow the same step in the
proceeding
section, set Parametric Analysis to sweep v2 for 0.6 0.9 1.2 1.5
1.8 points.
Start analysis. Fig. 7 shows the Result Browser on the left and
simulate
results on the right.
2.3 Layout
In this section, you will be guided to complete a NMOS and a
PMOS layout.
Before you attempt the layout, ensure the schematic is error
free. In addi-
tion, you are strongly recommended to open TSMC 0.18µm
logic 1P6M
salicide 1.8V/3.3V design rule to a reference.
Page 11

Figure 7: Results browser and simulation results
CMOS transistors are generally de�ned by at least four physical
masks.
They are active (also called di�usion, di�, OD or RX), n-select
(also called n-
implant, or nplus), p-select (also called p-implant, or pplus),
and polysilicon
(also called poly, polyg, PO, or PC). The active mask de�nes
all the areas
where either n− or p− type di�usion is to be placed or where
the gates of
transistors are to be placed. The overlap area of the ploy and
active area
de�nes the gates of transistors. n-select surrounds active
regions where n
type di�usion is required. P-select surrounds active regions
where p type
di�usion is required. Further, to form PMOS, or sometimes
even to form
NMOS, n-well or p-well are required, which should be larger
than the active
regions. To connect the body to the corresponding voltage level,

n+ or p+
region should be placed in the body.
Now, create a new cellview in your lab 1 library called NMOS
and choose
Virtuoso from the tool drop-down list. Two new windows will
occur, e.g
Layer Selection Window (LSW) and Layout Editor Window.
LSW is where
you can select the layers to do the layout. Layout Editor is the
main space
where the actual circuits are implemented. Pressing k will start
drawing a
Page 12
ruler, which is quite useful in the layout as you need to know
the precise
line width, perimeter, space, overlap, etc. of what you draw to
clean DRC
errors. A good layout experience is to run DRC periodically to
make it clean
at the very early stages rather than facing unresolvable issue at
the end.

As TSMC is a out-of-date technology, it lacks of capability of
automation,
especially, there is no available PCELL(parametrized cell) for
both NMOS
and PMOS. Your �rst layout work is to draw the NMOS and
PMOS. It is
therefore, two types of drawing objects, e.g. rectangles and
paths, are
the most recognized option to be used in the layout. A rectangle
is exactly
what it sounds like. Simply left click mouse will start to create
a rectangular
shape. You can stretch the shape using s. The layer that is
chosen to form
the shape is done through LSW or the layer can be changed later
by editing
the object's properties. A path is a shape that is de�ned by a
start and
end point, intermediate vertices and a width value. It is used
primarily to
connect devices and run signals from point to point as a path
has �xed width.
The following steps should be completed in turn:
• Drawing a gate to determine the length of the transistor.

• Drawing an active region to determine the width of the 1
�nger tran-
sistor. You may need to draw multiple �ngers to minimize the
gate
resistance and the drain capacitance. Or for matching purpose,
inter-
digitized layout may need multiple �ngers.
• Applying the doping to the active region.
• Drawing contacts for the source and drain terminals.
• Drawing contacts for the substrate connection. Note: Avoid
single con-
tact as contact show large variation during fabrication, and it
also has
large resistance, which is the detriment for the circuit's
performance.
• Drawing interconnects for signal routing.
• Drawing I/O pins
Page 13
To draw the gate, go to LSW, and choose the polysilicon
drawing layer.
Using path with 0.18 width is the easiest way to draw a gate.

You can
also use a rectangle to complete this task with the aid of ruler.
The height
should be larger than 1 as the width of the transistor is 1. Note
the default
unit is µm.
For the source and drain, we know these two regions are heavily
dopant
by either the donor atoms in p-sub or acceptor atoms in n-well.
The region is
�rst de�ned by the so called active region. Go to LSW palette,
and choose
active region drawing layer. Using path again with the width 1.
Make sure
the active region is perpendicular to the gate polysilicon. Then,
n+ region
is the next drawing layer, which must overlap the active region
by 0.35 in all
directions. Select n+ fro LSW, and start from the centre of the
polysilicon,
draw a path. Using ruler to mark 0.35 in all directions. Stretch
out the
path. Till now, a transistor has been formed. The drawing of
gate, drain

and source are shown in Fig. 8.
Figure 8: a) Poly gate, b) With active region, and c) n+
Page 14
The next step is to create contacts, which are used to connect
poly to
metal and di�usion to metal. Go to LSW, choose contact
drawing layer and
de�ne the dimensions 0.22x0.22. Note: active contact to gate
spacing > 0.16;
active overlap of contact >0.10. Using ruler to mark some key
points. You
may need to adjust the active region and n+ region. MOSFET is
a four
terminal device. The substrate is the de�ned as the 4th
terminal. If it is
a NMOS, the p-sub should be connected to the lowest potential.
If it is a
PMOS, the n-well should be connected to the highest potential
to avoid any
forward biasing of the junction diode. Connect substrate also
prevent latch-

up from high injecting current and voltage to any node of the
circuits. The
region that is used to create contact in p-sub is called p+. Find
the proper
drawing layer from LSW. Create a rectangular with considering
the rules
mentioned previously. Add active region. Leave a space for two
contacts.
Fig. 9 shows the transistor with drain and source contacts. Fig.
10 depicts
the p-sub contacts.
Figure 9: Adding contacts
The next step is to add interconnects. In general, signal routing
is in
the lower layer. The higher layers are used for power grid
layout and other
passive components, e.g inductors and capacitors. For digital
cell, try to
limit the layers to metal 1 and metal 2. Do not go beyond metal
3, which
Page 15

Figure 10: Adding p-sub contacts
will bring di�culties to the physical designer to integrate all the
function
blocks in a complex system. Keep in mind, a product consists of
a variety of
function blocks, i.e. not only the one that you designed but
other designed
blocks will be integrated into a small area. It is crucial to limit
your own
layout in a small area as much as possible.
So far, we have placed two contacts for each of terminal except
for the
gate. You may question, what about the gate? There is not
enough space to
place a contact to the gate. You can extend the polysilicon of
the gate a little
bit more, which does not a�ect the channel length as the
channel length is
de�ned by the part of the gate, overlapping the active region.
Go to Create-
>contact and select m1_poly from drop-down list. A PCELL
contact is
created. Put it to the extended poly. Go to LSW, choose metal 1

drawing
layer, and draw a metal 1 path(please refer page 44 of the
design manual for
metal 1 rule). Usually, you should run a few times DRC to clean
the DRC
violation. But for the sake of simplicity, we assume DRC is
clean(only true
in this tutorial). We introduce DRC later. Fig. 11 is to show
how to draw
metal 1 wire.
Once this is done. The last step is to add pin. Go to Create-
>Pin, and
entre G S D B as the terminal names, select Display Pin Names,
and make
sure the pin type is metal 1_t. It will fails LVS otherwise. Set
I/O type to
inputoutput and place the pins accordingly. Fig. 12 is the �nal
layout of an
NMOS.
Page 16
Figure 11: Drawing interconnects

To create a PMOS, there are two ways. You can either repeat all
the
steps that you have done so far or simply go to Design->Save
As ... (a
easy way only for this tutorial) and make the cell name PMOS.
Open PMOS
layout view. Change the n+ to p+ region by changing the
property of the
di�usion. Keep the active region as we still need it to de�ne
the width of the
PMOS. Similarly, for the p-sub contacts should be changed to
n+ contacts.
Add a n-well around the transistor to de�ne the substrate
region, as shown
in Fig. 13. It should be noticed that in practical, the width of the
PMOS
is not same as the NMOS. In other words, you most likely will
have to go
through the all steps for the PMOS layout.
2.4 Layout Veri�cation
Physical veri�cation is one of the key steps to ensure the design
is functional
correct after layout, and meet the manufacture rules set by the

foundry. In
this section, you will perform DRC, Extraction, LVS and post-
layout simu-
lation.
Page 17
Figure 12: NMOS layout
Design Rule Checking (DRC)
The design rule veri�cation step checks that all polygons and
layers from the
layout database meet all of the manufacturing process rules. A
complete set
of design rules for TSMA 180 nm PDK can be found in
"/CMC/kits/cmosp18/doc".
To perform a DRC check, in Layout editor window, go to
Verify->DRC.
Click Set Switches button and choose do_drc and
ignore_substrate/well_soft_connect
from the list and press OK. Then Run DRC. Check the results
listed in the
icfb window, as shown in Fig. 14. Clean all the errors that are
listed. To get

more information about the error. Go to Layout editor window.
You will
see the �ashing boxes with an X through them. Got o Verify-
>Markers-
>Explain and click on one of the �ashing boxes to see detail
about the
error. You should refer to the design manual to get help as most
of time the
information is too simple to understand.
Page 18
Figure 13: PMOS layout
Figure 14: DRC results
Extraction
Extraction is a hand-o� step back to the circuit designer, who
will simulate
the circuit based upon the extraction �le. Sometimes, there are
speci�c re-
quirements from the circuit designers to the layout engineer.
For example,
the circuit designer may be more interested in the parasitic

capacitance due
to the wire coupling. The layout engineer should switch o� the
parasitic re-
sistance before the extraction. Feedback will be given by the
circuit designer
after the post-layout simulation to the layout engineer if there is
a need of
modi�cation for the layout. As you can see, the extracted
netlist is a good
vehicle that link the design engineer and layout engineer.
Page 19
To do the extraction, go to Verify->Extract, click on Set
Switches,
choose parasitic_caps. The extracted netlist consists of the
layout devices
that you created, as well as parasitic capacitance which are not
considered
at the schematic level. This is very crucial for the designer. In
particular, for
the high-speed circuit, a few fF capacitance may a�ect the data
speed sig-

ni�cantly. As you may notice that there is no parasitic cap and
parasitic
res option. This is due to the old version of extraction tool, e.g.
Diva Ex-
traction. More advanced extraction tools such as Cadence QRC
extraction
or Mentor xRC can extract parasitic inductances and mutual
inductances as
well. Go to icfb to check if there is any error.
To view the extracted �le, go to File->Open and �nd the cell
name that
you created, change the view name to extracted and press OK. If
you see
Fig. 15, press Shift-F, which leads to the full layer views, as
shown in Fig.
16, where the parasitic capacitance is shown.
Figure 15: Extraction View
Layout vs. Schematic Check (LVS)
LVS veri�cation is checking that the design is connected
correctly. The
schematic is the reference circuit and the layout (extracted
netlist) is checked
against it. The following are veri�ed [2]:

Figure 16: Extraction View
• Electrical connectivity of all signals, including input, output,
and power
signals to their corresponding devices.
• Device sizes: transistor width and length, resistor sizes,
capacitor sizes.
• Identi�cation of extra components and signals that have not
been in-
cluded in the schematic; �oating nodes would be an example of
this
To pass LVS, we have to modify the schematic as we add Pins
to the layout
while in the schematic, there are no pins declared. Open
Schematic editor for
your won design. Delete all the voltage sources and ground
instances, which
are not existing in the layout view. Press P, type G D S B for
the name and
set direction to inputoutput. Place Pins in the schematic
respectively, shown
in Fig. 17. Do not forget save and check any time you modify

the circuits.
Next is to create a symbol from the schematic for the
simulation. Go
to Design->Create Cellview->From Cellview ..., and press OK.
In
the Symbol Generation Options window, under Pin
Speci�cations assign the
pins as follows: Left Pins: G; Right Pins: B; Top Pins: D;
Bottom Pins: S,
shown in Fig. 18. Click Load/save and in the expanded window
make sure
analog is chosen then press Load. It is important that you click
NO if a
message appears calling for Overwrite Base Cell CDF. This
ensures that the
parameters of the base cell are not changed. In the Symbol
editor, you can
Page 21
Figure 17: NMOS transistor with I/O
change the shape the symbol, shown in Fig. 19. Now, go back to
Layout

Figure 18: Pin assignment
editor, click Verify->LVS, and �ll in the �elds same as Fig. 20.
If the
schematic and extracted netlist match, a pop-up window will
indicate this,
shown in Fig. 21. Otherwise, refer to the LVS output log to see
where the
mismatches are and correct them.
Page 22
Figure 19: Symbol
Post-layout simulation
The last step is to verify the functionality and timing after the
layout. As
we mentioned previously, the circuit designer will include the
extracted �le
to the test bench, which is also used for schematic simulation,
to compare
and check if the performance is acceptable. The common way to
make sure
the testing environment is identical to the pre-post simulation is
to consider

the DUT(Design Under Test) is a black box no matter which
design is in.
The way to implement this is to use con�g.
First Creating a common test bench in the schematic editor, e.g.
NMOS_tb.
In this tutorial, we create two test circuits. One is for schematic
simulation,
and the other is for post-layout simulation. In practical, you
should avoid
it. Only create one test circuit is enough. Nevertheless. we build
two test
circuits as Fig. 22. Then close schematic editor and Create-
>Cellview,
use the same name, e.g. NMOS_tb. Change Tool to Hierarchy-
Editor.
In the New Con�guration window, type schematic in the view
�eld. Then
press Use Template and in the Use Template Window choose
spectre from
the Name drop-down list. In Cadence hierarchy editor, got to
Viw->Tree
and right click on one instance of the nmos transistor and go to
Set In-

stance View->extracted. For the other one we choose schematic.
The
�nal con�guration is shown in Fig. 23. Press Save button
followed by the
Update button. Then press Open to open the con�g view of the
test bench.
Page 23
Figure 20: LVS con�guration
Figure 21: LVS result
Open ADE, and load the state that you saved for the dc analysis.
Open dc
analysis, change sweep variable to design variable and set the
variable name
to the one connect to the drain terminal, e.g. v1. Then press OK.
Perform
the same Parametric analysis to obtain the I-V curve. Do
remember, to
observe the result, you have to go to Results Browser, you will
see the results
as Fig. 24.
Page 24

Figure 22: Post-layout simulation
Figure 23: NMOS con�g view
2.5 Report
Please prepare the report according to the following
descriptions:
1. Deadline: Oct. 13th, 2018.
2. File name: EELE5331_ Name.
3. A brief description of the lab and the simulations are
necessary.
4. Schematic of NMOS and PMOS.
Page 25
Figure 24: Schematic simulation and Post-layout simulation
results
5. The family of I-V curve for both NMOS and PMOS.
6. The layout and extracted views of NMOS transistor.
7. Screen shot of DRC result same as Fig. 14. Note: The time
when DRC

is done must be clearly captured.
8. Screen shot of LVS result. The LVS output log �le, si.log,
can be found
under Home/design folder/LVS/.
9. The family of I-V curve for extracted NMOS transistor.
10. A brief summary with respect to the results from schematic
and ex-
tracted �le.
2.6 How to understand DRC error report
Most of the time, DRC error is less meaningful. To understand
the DRC
report, please go to /CMC/kits/cmosp18/doc, where two
documents,
CMOSP18designRulesLogic.pdf and
CMOSP18designRulesMixed.pdf, have more
detail about the error information.
Page 26
3 CMOS Inverter
Shown in Fig. 25 is a CMOS inverter [1]. In this lab, the static

and dynamic
characteristics of the CMOS inverter, the most critical device in
digital ASIC
design, will be examined in detail, e.g. VTC, noise margin,
delay, etc. Fur-
ther, a layout of an inverter will be created, characterized and
compared with
the schematic simulation.
Figure 25: CMOS inverter: a) schematic, and b) layout
3.1 Design speci�cations
One of the design parameter for an inverter is the propagation
delay, e.g.
τp, indicating how fast of the output changes with respect to the
input.
It is de�ned as the di�erence between VDD/2 of the input and
VDD/2 of
the output. Fig. 26 shows the current charging and discharging
the load
capacitor through NMOS and PMOS, where one can determine
the rising
propagation delay and falling propagation delay. Most of
practical design,
the rising edge is not same as the falling edge although it is

preferable. As a
result, characterize rising and falling edge separately is of great
interest. It
Page 27
Figure 26: CMOS inverter charging and discharging: a)
charging, and b)
discharging
can be noted that the delay relays on how fast charging and
discharging the
load capacitor, e.g. CL. The NMOS and the PMOS both have
ON resistor,
depending on the region of the CMOS transistor. In digital IC
design, the
ON resistance of NMOS and PMOS are evaluated when the
CMOS transistor
is in the triode region. According to the �nal voltage level, the
propagation
delay may varies.
In this lab, the steady-state voltage is de�ned as 30% and 70%.
From
what you learned in the electronic circuit I, the needed

equations are listed
as below:
τp =
1
2
(τpdr + τpdf) (1)
where
τpdr = ln2RonpCL (2)
τpdf = ln2RonnCL (3)
Ron,n =
1
µnCox(
W
L
)n(VDD −Vtn)
(4)
Ron,p =
1
µpCox(
W
L
)p(VDD −|Vtp|)
(5)

Given the following parameters:
• tox=4.08 nm
• �0=8.854 × 10−12 F/m
Page 28
• �ox=3.9
• µn = 459 cm2/V ·s
• µp = 109 cm2/V ·s
• Vtn=0.45V
• Vtp=-0.44V
For this lab, you are required to design a CMOS inverter
achieving 100
ps propagation delay with symmetrical swing while driving a
load capaci-
tance of 50 fF. Please compare the schematic simulation with
the
speci�cations.
3.2 Lab Procedure
Create a new library called Lab2 and attach it to the cmosp18
tech�le. Create

a schematic cellview in the lab2 library called inverter. Create a
schematic
for a CMOS inverter according to Table 2. Since the calculated
width
Table 2: N/PMOS
cmosp18 nfet symbol width = wn, length = 180n
cmosp18 pfet symbol width = wp, length = 180n
is too small. You need to modify the width of the transistors to
adapt to the layout. Width for NMOS and PMOS should be 4
times larger than what you have calculated. Once the schematic
is
created. The next step is to add pin, e.g. VDD, GND, IN and
OUT, in
accordance with the input or output. An inverter symbol should
be created
after this step, similar to what you have done in the �rst lab.
Further, instead
of using default shape, you can always change the shape of the
symbol. For
Page 29

instance, you can delete the green box and draw the symbol of
inverter using
Line tool. The bubble at the end of the inverter can be drawn by
changing
the line mode to circle mode. Do not forget check and save after
the symbol
is created.
To verify the inverter, you need to create a testbench in a new
cellview
called inverter_tb. Use the instances in Table 3 Verify the
design in ADE
environment as you did in Lab1.
Table 3: Instances for testbench
lab2 inverter symbol
analogLib vpulse symbol Voltage1=0, Voltage2=1.8, Delay
Time=0, Rise Time
=Fall Time= 10p, Pulse width=2n, Period=4n
analogLib vdc symbol DC Voltage = 1.8
analogLib cap symbol DC Voltage = 50f

analogLib gnd symbol
First simulation is the static analysis. Before start a simulation,
model
library path, simulator, etc. should be con�gured. The netlist
checking may
fail if the simulation model is not found. After this step, a few
simulations
are required. Similar to Lab1, a DC analysis is performed.
Under Sweep
Variable, choose component parameter. Press select component
and in
the schematic choose the instance of vpulse, then an new
window will occur.
Select dc and press OK. Set Start, Stop to 0 and 1.8 with the
step size of
0.1. And run simulation, plot the output. You should see a
simulation result,
showing Vin vs. Vout. To �nd out VIL,OL, and VIH,OH, you
need to �nd out the
slop=-1 from the result. To do that, open Waveform Calculator,
chose
vt, and click wave. Then choose deriv function in Calculator.
Change

the drop-down to New Subwindow and press Eval. Use this
waveform to
determine VIL,OL, and VIH,OH. Mark the -1 using marker.
Page 30
The second simulation is dynamic analysis. Create a tran
analysis. En-
suring the duration cover at least two cycles of the input signal.
Open Wave-
form Calculator and �nd the delay function. Place the cursor in
the blank
Signal1 �eld and choose vt under the tran tab. The schematic
window will
come up, click on the IN net. Repeat this for the Signal2 �eld,
and choose
the OUT net. Set Threshold Value 1 to VDD/2(you may change
this value
if the threshold voltage is not VDD/2) and Edge Type 1 to
Rising. Click
>>> button and on the next page, set Threshold Value 2 to
VDD/2 and
Edge Type 2 to Falling. Click OK and the expression will
appear in the top

�eld of the Calculator window. Add the expression to the
outputs as you did
in Lab 1, and name it Output Falling Delay. The Output Rising
Delay can
be obtained in the same way, but by reversing the Edge Types.
Now you
have two pre-de�ned expressions to obtain the rising/falling
edge delay. Run
tran simulation to verify the speci�cation. You may need to
change the size
in accordance with the simulation.
Then perform the layout. Use what you have learned from Lab 1
to
complete the inverter design, including layout, DRC, LVS,
extraction and
post-layout simulation. You should use con�g option that was
introduced
in Lab1 to con�g the view between schematic and extracted-
view such that
both pre-post layout simulation are tested using the same
testbench. Note:
post-layout simulation should include static and dynamic
analysis same as

pre-layout simulation.
3.3 Report
Please prepare the report according to the following
descriptions:
1. Deadline: Oct. 28, 2018.
2. File name: EELE5331_ Name.
3. Show the calculation of the width for NMOS and PMOS.
Page 31
4. Schematic of the CMOS inverter (after change the width to 4
times
larger).
5. Schematic of the testbench.
6. Screen shot of static and dynamic CMOS inverter
simulation(after
change the width to 4 times larger).
7. The layout and extracted views of the CMOS inverter(after
change the
width to 4 times larger).
8. Screen shot of DRC result same as Fig. 14. Note: The time

when DRC
is done must be clearly captured.
9. Screen shot of LVS result. The LVS output log �le, si.log,
can be found
under Home/design folder/LVS/.
10. Screen shot of static and dynamic CMOS inverter for post-
layout sim-
ulation.
11. A brief summary with respect to the results from schematic
and ex-
tracted �le. Explain any deviations from your calculation.
Page 32
Bibliography
[1] J. M. Rabaey, Am Chandrakasan, and B. Nikolic �Digital
Integrated
Circuits: A Design Perspective,' Pearson, Second edition, Jan.
2003.
[2] A. Kabbani and T. Khan, �ELE754 Lab Manual," 2009
33
IntroductionMOSFET Devices and Layout TutorialPrepare For
SchematicPerform SimulationLayoutLayout

VerificationReportHow to understand DRC error reportCMOS
InverterDesign specificationsLab ProcedureReport

EELE 5331 Digital ASIC DesignLab ManualDr. Yushi Zhou.docx

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