Unified methodology for effective correlation of soc power

Unified Methodology for
effective correlation of
SoC Power Estimation
and Signoff
Pankaj Singh
Girish Ravandur
Edwin Marelie
Lalit Gohate

Topics
1. Challenges with Accuracy of Power Estimation and Correlation
2. Overview:
– Modified Flow for Early Power Estimation
– SoC Power Estimation and Correlation Flow
3. Unified SoC Power Pattern Methodology
– SPP Code Development
• Parameter Table
• Code Flow
– SoC Power Analysis
4. Post-Silicon Measurements Flow
5. Correlation with Unified Methodology
6. Conclusion and Benefits
2set date Copyright © Infineon Technologies AG 2016. All rights reserved.

Introduction: Challenges with Accuracy of
Power Estimation and Correlation with Silicon
30001-01-01 Copyright © Infineon Technologies AG 2016. All rights reserved.

Accurate Power Estimation
› Increased design complexity leads to difficulty in Accurate power
estimation and Correlation with silicon.
– Late Design changes.
– Expensive Design re-spins.
IP Design
SoC
(RTL)
SoC
(Gate)
Tape
Out
Silicon
Power
Analysis
Late Change
Deviation
Detected
Redesign
Need: Early and accurate power estimates minimizing re-design

Common Framework for Power
Measurements
› Lack of common methodology from EDA vendors for power
measurements and correlation across platforms.
– Significant effort is spent to debug issues related to power
measurement/correlation.
– Multiple iterations of power pattern delivery
Need: Unified Framework across Pre and Post Silicon platforms
for accurate power estimation and measurements
Result
Result
Result
Post-
Si
Test
Code
1
correlations
No
Post-
Si
Test
Code
2
Post-
Si
Test
Code
3
No
Debug
Debug

Power Estimation and Measurement Flow

Modified Flow for Early Power Estimation
› Beneficial to do early power estimation and overcome accuracy
limitations:
– Rely on past Silicon data
– Check ESL estimates (as starting point)
– Focus on design changes, critical logic.
– Add realistic scenarios from concept.
– Compare and iterate at each stage.
Ref 1
IP
Design
SoC
(RTL)
SoC
(Gate)
Tape
Out
Silicon
Power
Analysis
Late Change
Minimized
Power
Analysis
Early
Architecture
Feedback
Deviation
Detected
Deviation
Detected
Spyglas
s Power
Analysis
Minimized
Redesign
Correlations
Correlations

SoC Power Estimation and Correlation Flow
› SoC Power Pattern
(SPP) Methodology is
developed for Power
Measurement
Correlations.
› This methodology
cover from Pre- to
Post-Silicon Phase.
› Power Measurement is
done by validation,
production test,
characterization test
team.
Pre-Silicon
FSDB
(RTL)
FSDB
(GLS)
SoC Power Analysis Methodology
Power Analysis
Report
(GLS)
Power Analysis
Report
(RTL)
Match the
Specs?
Match the
Specs?
Final Power Analysis
Report
(RTL)
Final Power Analysis
Report
(GLS)
Yes Yes
No
Silicon testing
[testers]
Production
Testing
Characteriz-
ation
testing
IBIS
Testing
Power
Measurement
(Silicon)
Post-Silicon
Power
Testcase
Post-Silicon
Validation
Power
Measurement
(Silicon)
POWER SPECIFICATIONS
MAX, REAL, FREERUN.
Unified SoC Power
Verification
Methodology
Feedbacktodesign
No
Design
Update
s
Iterate with Verification
Requirements
SPP act as single-source Test Code for different
Test Platform supporting easy convergence and
correlation of results across platforms

Unified SoC Power Pattern (SPP) Methodology

Unified SoC Power Pattern Methodology
› Single-source code reused
across different pre and post
silicon platforms.
› This comprehensive Unified
Methodology covers:
– Customer Requirements for
traceability
– SPP Code Development
– Power Analysis
– 1st Silicon Bring-up
– Post-Silicon Validation
– Production Tester
– Characterization Tester
Power Analysis
+
IR Drop,EM
Analysis
.fsdb
PROD Tester
.inf
.sre
.inc
First Si-
Bring up
.elf
.tde
Validation
.elf
.tde
Customer
Requirement
1st Silicon
Bring-upCHAR
Pattern
PROD
Pattern
VAL
SPP
Code
Development
Power
Analysis
CHAR
Tester
.sre
.tde

SPP Code Development
› SPP development starts with Customer Requirements from Concept.
SPP
Framework
Customer
Requirement
CPU
MainPower
Clocking
Block
DMA
Power
Saving
Block
Parameter
Table
Serial
Interface 1
Serial
Interface 2
Task Scheduler
Block
Timer 1
IP3 Timer 3 Timer 4
Serial
Interface 3
IP2 Timer 2IP4
IP6
IP1
IP5
SPP blocks
Design
› SPP consist of the following main elements:
– Main Power
– Parameter Table
– Task Scheduler
– DMA
– CPU
– Clocking
– Power Saving
– IP Module

SPP Code Development: Parameter Table
› Parameter Table is re-used across different platforms and maintained
by central SoC Test pattern team : Provides consistent setup &
promotes reuse.
– Multiple Test Scenario can be generated via this Parameter Table
(Max, Real, ADAS, Emulation) without changing the SPP Code.
Parameter Table
(.TDE)
1st Silicon
Bring-up
CHAR
Pattern
PROD
Pattern
VAL
Simulation
Customer
Requirement
Parameter Table based on
Customer Requirement
Application
Concept
Customer
Reusable Reusable
SPP Code
Parameter
Table for Max
Power
Parameter
Table for Real
Power
Parameter
Table for
ADAS Power
Parameter
Table for ED
Power
ADAS Power
MAX
Power
REAL
Power
ED Power

SPP Code Development: Parameter Table
– The test parameters is preloaded to the defined SRAM location before
the code execution.
– The code flow is controlled by externally preloaded parameters.
J750IBIS
LABV93K

SPP Code Development: SPP Code Flow
› The MainPower module is the central block of the SPP Software.
› It executes the init(), run(), and postprocessing().
CPU 0
Init
CPU 1
Wait
CPU 2
Wait
IP1 init
Serial
Interface
init
ADC init
DMA init
CPU 0
Run
CPU 1
Run
CPU 2
Run
IP1 run
Serial
Interface
run
ADC run
DMA run
IP1
Task Scheduler
Serial Interface
DMA Channel
ASCLIN
DMA Channel
Int Int
› To get the correct power measurement, it is necessary to create
realistic application scenarios.
› This is achieved by triggering the IP Modules after completion of the
first run.
› DMA and Task Scheduler enable re-triggering of IP modules

SoC Power Analysis
› Activity file dumped for power-critical signals after careful analysis
saving power analysis runtime and memory resource.
› The Fast Signal Database (FSDB) file from the SPP is delivered to the
Power Analysis Team.
› The Power analysis starts with RTL and is improved with netlist.

Post-Silicon Measurements:
Post –silicon Validation (E-Beam Board)
Production Tester
Characterization Tester

1st Silicon Bring-up and Validation
› 1st Silicon Bring-up and Validation uses the same setup.
› The input files are:
– .elf, generated from the SPP
– .tde, unified parameter table file

1st Silicon Bring-up and Validation
› Unified framework allows early 1st silicon bring-up and minimizes power
pattern re-delivery due to test environment issues.
› Good correlation is achieved with the Unified framework
-2.5% -5%
+6.5% +5% +5%
CPU1 CPU2 CPU3 CPU4 CPU5
Current(mA)
CPU Cores
CPU1-5 Current with
Real Pattern
Expected
Current
Measured
Current
X1
X2
X3
X4
X1
+4%
X2
+4%
X3
+5.5%
X4
+5%
Y1
Y2
Y3
Y4
Y1
+6%
Y2
+5%
Y3
+2.4%
Y4
+2.4%
Tj =
+125°C
Tj =
+150°C
Tj =
+160°C
Tj =
+165°C
Current(mA)
IDD Total and IDD Leakage
Current
Expected
PORST Leakage
IDD: PORST
Leakage
current
Expected IDD
Current
IDD Current

Production and Characterization Tester
› The file format is slightly different for Production and Characterization
tester:
› The unified framework promotes re-use of parameter table [TDE files]
for both production and Characterization testers by creating wrappers
(INF format ) for production tester.
› The consistent setup with same source code provides high confidence in
power measurements across different tester platforms.
Production
Tester
.inf
.inc
.sre
CHAR
Tester
.tde
.sre

Enhancements in Test Environment
› Download of the source code ‘SRE’ file into the Characterization Tester
can be time consuming.
› Limited amount of Tester Memory further adds to this complexity.
› To overcome these challenges following simplified innovative approach
is used resulting in more than 80%:
– Generate CPU Power Code only for 1 CPU
– Use the DMA routine to copy the code to other CPUs memory
– This approach significantly reduces the download time for source
code.
20Copyright © Infineon Technologies AG 2016. All rights reserved.
765.987
149.06
Old Method New Method
Download Time for
SRE (ms/download)
3350152
566232
Vector Memory
(vectors/download)
Old Method New Method725
121
SRE File size (KB)
80.5%
Reduction
83.3%
Reduction
83%
Reduction

Unified
Test
Code
Unified
Test
Code
Unified
Test
Code
Unified
Test
Code
Correlation with Unified Methodology
› Single source code enables simple and first time right correlation
between Pre- and various Post-Silicon platforms.
Result
Result
Result
Post-Si
Test
Code 1
Post-Si
Test
Code 2
Post-Si
Test
Code 3
Pre-Si
Test
Code
Pre-Si
Design
Power
Analysis Result
C
o
r
r
e
l
a
t
i
o
n

Conclusion and Benefits
› Unified Methodology for Effective Power correlation and Signoff is
proven on silicon . It provides effective correlation results (within 6%
deviation). Following are the main benefits:
 Minimize late design changes/re-spins.
 Early and accurate estimation of SoC power and good correlation of
results with silicon minimizes late design changes or design re-spins.
 Promotes reuse.
 Common frame work promotes reuse across pre-silicon and different
post silicon platforms.
 First time right.
 Minimize pattern re-delivery. Fully automated and Configurable flow
minimizing manual error and effort for generation of test code to
meet the specific requirements of different platforms.
 Early silicon bring-up.
 Easy replication of issue in pre-silicon verification environment for
debug and re-generation of pattern.

References
1. http://chipdesignmag.com/sld/blog/2016/08/25/power-
analysis-and-management/
2. Clarke E. FPGAs and Structured ASICs: Low-Risk SoC for the
Masses [Online]. Available: http://www.designreuse.com
3. V. Tiwari, S. Malik, and A. Wolfe, “Power Analysis of Embedded
Software: A First Step Towards Software Power Minimization,”
IEEE Trans. VLSI Systems, vol. 2, pp. 437–445, Dec. 1994.
4. Ghodrat, M.A.; Lahiri, K.; Raghunathan, A., "Accelerating
System-on-Chip Power Analysis Using Hybrid Power
Estimation," Design Automation Conference, 2007. DAC '07.
44th ACM/IEEE , vol., no., pp.883,886, 4-8 June 2007
5. S. Nithin et al., "Dynamic voltage (IR) drop analysis and design
closure: Issues and challenges," in Proc. of ISQED, pp. 611-
617, March 2010.

Acronyms
Acronyms Description
ELF Executable and Link Format
FSDB Fast Signal Database
GLS Gate Level Simulation
PORST Power On Reset
RTL Register-Transfer Level
SoC System on Chip
SPP SoC Power Pattern
TDE Tableau Data Extracts
VAL Validation
SRE
ADAS Advanced Driver Assistance Systems

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Unified methodology for effective correlation of soc power

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