Saikiran Kastury has experience designing integrated circuits and layouts using tools like IC Studio. He completed a PG Diploma in ASIC Design from RV-VLSI Design Center in 2016. Some of his projects there included creating a standard cell library using a 90nm process and analog layout of a differential amplifier using a 180nm process. He also created leaf cells for an SRAM using a 28nm process. For his undergraduate project at GITAM, he designed an automatic metro train that used a GPS system and stored passenger information.

1. Powered by Nanochip Solutions
Powered by Nanochip Solutions
Saikiran Kastury
kasturisaikiran@gmail.com, 8121995136
BENGALURU-560076, Karnataka
Career Objective
My objective is to grab the opportunities given by the company and use them in the way that
can be helpful to the company and can help me to achieve a higher position in my professional
life
Core Competancy
ICSTUDIO,KEILSOTWARE,ELECTRONIC CIRCUIT SIMULATOR,VI editor,Questa,perl
scripting,linux
Using Ic studio created layouts of integrated circuits by satisfying design rules of various
process ,maintaining minimum no of parasitic errors& compatibility.
Created c code for various Micro Controller 8051 based projects by using the KELI
SOFTWARE
Before creating final electronic circuit for specific application I have checked it's functionality
by creating the circuit virtually using ELECTRONIC CIRCUIT SIMULATOR
Using VI editor created few verilog codes and there respective test bench codes . Spice net lis
is also created for clearing LVS check in IC studio for particular layout
This tool is used for verifying there is any bug in my verilog codes
Created some basic C programs such as identifying prime number using perl scripting
How to operate the linux operating system by using commands
Education Details
PG Diploma in Advanced Diploma in ASIC Design - Full Custom 2016
RV-VLSI Design Center
Bachelor Degree in Instrumentation Technology 2016
GITAM, with 7.88 CGPA
PUC / 12th 2012
SRI CHAITANYA, with 87.8 %
SSLC 2010
D.A.V Public Schoool, with 79.7 %

2. Powered by Nanochip Solutions
Powered by Nanochip Solutions
Domain Specific Project
RV-VLSI
Graduate Trainee Enggineer Oct-2016 to Oct-2016
Standard Cell library
Description
The library is a collection of various low-level electronic logical functions. This is used by
physical design engineers in logical synthesis. The library is created by using 90nm process.
The unique features of cells is that their height is fixed
Tools
IC STUDIO by MENTOR GRAPHICS
Challenges
drawing layouts for those circuits by satisfying design rules of 90nm process that means
maintaining minimum spacing between metals, between poly ,between ploy and contacts etc.
Understanding the spice net list of each cell and drawing the layouts so that logic of circuits is
statisfied as spice netlist provides information about connections in layout .
Ideally Poly routing for bigger layout is not recommended as it would increase resistance of
the channel so remembering this creating layouts in optimized way became difficult
Finally while placing the input pins and out pins it was difficult to place them so that the
automatic routing and placing tool could recognize them
RV-VLSI
Graduate Trainee Enggineer Nov-2016 to Nov-2016
ANALOG LAYOUT
Description
Designed a two stage differential amplifier by using cmos . It's function is to amplified input
voltage signal . The differential amplifier is designed by using 180nm process`
Tools
IC STUDIO by mentor graphics
Challenges
Matching the transistors according to their functionality. In analog circuits by following
Matching Technics the noise in circuit can be eliminated
Metal 2 layer in addition to metal 1 layer is used in analog layouts as result complication in
routing and parasitics will increase .So keeping this in mind routing is done
Designing own floor plan by following the matching technics
Creating spice net list according to the functionality of the circuit

3. Powered by Nanochip Solutions
Powered by Nanochip Solutions
RV-VLSI
Graduate Trainee Enggineer Nov-2016 to Nov-2016
Leaf cells
Description
The leaf cells are similar to standard cells.These are used in creating layout of SRAM. 28nm
process is used to create these cells.
Tools
IC STUDIO by Mentor Graphics
Challenges
While creating layouts using 28nm it became difficult to maintain ploy on ploy grid and contact
on the contact grid for complicated circuits as they were one of the design rules
As in 28nm process horizontal poly are not allowed so it was impossible for ploy routing so
metlal is only used for routing so the optimization of the circuit was tough
Reducing parasitics in 28nm was one of the biggest challenge
B.E / B.Tech Academic Project
GITAM
AUTOMATIC METRO TRAIN
Description
Designed the program in such a way that the BOT is self operated. A GPS system is fixed to it
so that the train can be tracked from far away places . The information about no of passengers
traveled is also stored.
Tools
microC PRO software PICKIT2 Micro controller USB Programmer PIC KIT2 Burner
Challenges
Interfacing GPS , Memory Storing system to the controller Designing code according to my
requirement Connecting the electronic components with help of soldering