EFFICIENT POWER MANAGEMENT TECHNIQUES SUCH AS SKIN TEMPERATURE AWARE POWER MANAGEMENT AND BATTERY BOOST FOR IMPROVED ENERGY EFFICIENCY [PERFORMANCE/WATT]
DEVELOPING PERFORMANCE ANALYSIS ENVIRONMENT BY REUSING EXISTING VERIFICATION ENVIRONMENT
HOLISTIC VIEW OF SOC VERIFICATION :
EVOLUTION OF UVM METHDOLOGY, UVM 1.2 AND CHALLENGES WITH MULTI LANGUAGE SUPPORT/AMS SUPPORT.
EDA INDUSTRY/TOOL CHALLENGES WITH HW-SW DEBUG, VP MODEL VERIFICATION.
H/W ASSISTED SIMULATION ACCELERATION, CHOOSING EMULATION CONFIGURATION FOR YOUR DESIGN.
1.Car Security
Understanding the Car Onboard Communication / Connection and inherent Security Weakness
2.Addressing the Security Concerns : System’s Viewpoint
Hardware Security Module & Secure Hardware Extension
Look at Software Principle of MAC and Associated Hardware
3.Achieving Security implementation checks via Software and Addressing the Hardware Safety aspect.
Closing the Loop for Security Safeness: Complete Solution to Ensure Security/Safety Compliance with Software
eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.
"ZYNQ-7000 High Performance Electric Drive and Silicon Carbide Multilevel inverter with Scilab Hardware-in-the-loop"
By Giulio Corradi, Xilinx for ScilabTEC 2015
1.Car Security
Understanding the Car Onboard Communication / Connection and inherent Security Weakness
2.Addressing the Security Concerns : System’s Viewpoint
Hardware Security Module & Secure Hardware Extension
Look at Software Principle of MAC and Associated Hardware
3.Achieving Security implementation checks via Software and Addressing the Hardware Safety aspect.
Closing the Loop for Security Safeness: Complete Solution to Ensure Security/Safety Compliance with Software
eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.
"ZYNQ-7000 High Performance Electric Drive and Silicon Carbide Multilevel inverter with Scilab Hardware-in-the-loop"
By Giulio Corradi, Xilinx for ScilabTEC 2015
Automotive embedded systems now include numerous software-intensive functions that are critical from a safety point of view (e.g., braking, assisted driving, etc). These functions are distributed on the Electronic Control Units and they need to exchange large amount of data with real-time constraints. In this context, the communication system plays a major role and it has to respect stringent dependability constraints. Security, especially with the widespread of wireless networks, is now becoming a serious matter of concern too. In this talk, we will review the main threats to dependability and security in automotive communication systems, the existing technical solutions to attain them, and, highlight areas where developments might be needed.
This White Paper talks of different aspects of Hardware and Software co-design with respect to embedded product design and the need need for co-design along side many more aspects.
Autonomous driving requires safety considerations and the need of “fail operational” requires redundancy. In the networking portion of a car, this may mean separate networks, possibly of different technologies. Or it could mean a network topology and technology that supports scalable redundancy, like Ethernet TSN.
This presentation focuses on IEEE 802.1CB-2017, which is the TSN standard that supports data redundancy through the network. Various network topologies are examined. The relative costs of adding TSN redundancy for these topologies (including some, or all of, the end-stations/ECUs & bridges) are examined for various bandwidth utilizations, along with the expected packet loss. Each topology and bandwidth will be modeled under various bit-rate error values with the results discussed.
This presentation aims at providing a clear understanding of the TSN standards that support redundancy, and an understanding of the cost/benefit tradeoffs so proper engineering decisions can be made and proper expectations set.
ANSYS SCADE Usage for Unmanned Aircraft VehiclesAnsys
SCADE on-board the UAS P.1HH HammerHead
The Use of SCADE to develop the P.1HH Vehicle Control & Management System (Integrated Modular Avionics System) greatly reduced development time and effort.
Learn more about ANSYS SCADE Solutions for Aerospace & Defense http://bit.ly/1EdcsOJ
OLA Conf 2002 - OLA in SoC Design Environment - paperTim55Ehrler
The integration of Open Library Architecture (OLA) libraries within nano-technology design environments can positively impact SoC design cycle times. Consistent calculation of desired information across a standard application programming interface (API) ensures analysis convergence among tools, eliminates data exchange processing and storage requirements, and significantly reduces iterations through design processes steps.
Insights on the Performance and Configuration of AVB and TSN in Automotive Ap...RealTime-at-Work (RTaW)
Switched Ethernet is profoundly reshaping in-car communications. To meet the diverse real-time requirements in automotive communications, Quality-of-Service protocols that go beyond the mere use of priorities are required. In this work, the basic questions that we investigate on a case-study with diverse and demanding communication requirements is what can we expect from the various protocols aimed at providing a better timing Quality of Service on top of Ethernet? And how to use them? Especially how to use them in a combined manner. We will focus on the Credit-Based Shaper of AVB, the Time-Aware Shaper of TSN and the use of priorities as defined in IEEE802.1Q. The performance metrics considered are the distributions of the communication latencies, obtained by simulation, as well as upper bounds on these quantities obtained by worst-case schedulability analysis. If there have been over the last 5 years numerous studies on the performance of AVB CBS, the literature on comparing AVB to TSN and other candidate protocols is still sparse. To the best of our knowledge, this empirical study is the first to consider most protocols currently considered in the automotive domain, with the aim to gain insights into the different technological, design and configurations alternatives. In particular, an objective of this study is to identify key problems that need to be solved in order to further automate network design and configuration.
[EWiLi2016] Towards a performance-aware power capping orchestrator for the Xe...Matteo Ferroni
In the last few years, multi-core processors entered into the domain of embedded systems: this, together with virtualization techniques, allows multiple applications to easily run on the same System-on-Chip (SoC). As power consumption remains one of the most impacting costs on any digital system, several approaches have been explored in literature to cope with power caps, trying to maximize the performance of the hosted applications. In this paper, we present some preliminary results and opportunities towards a performance-aware power capping orchestrator for the Xen hypervisor. The proposed solution, called XeMPUPiL, uses the Intel Running Average Power Limit (RAPL) hardware interface to set a strict limit on the processor’s power consumption, while a software-level Observe-Decide-Act (ODA) loop performs an exploration of the available resource allocations to find the most power efficient one for the running workload. We show how XeMPUPiL is able to achieve higher performance under different power caps for almost all the different classes of benchmarks analyzed (e.g., CPU-, memory- and IO-bound).
Full paper: http://ceur-ws.org/Vol-1697/EWiLi16_17.pdf
In this webinar, learn how OPAL-RT's state-of-the-art Hardware-in-the-Loop (HIL) simulation solutions empower engineers to design and test ECUs, and other integrated power electronic systems and controllers, with efficiency.
Automotive embedded systems now include numerous software-intensive functions that are critical from a safety point of view (e.g., braking, assisted driving, etc). These functions are distributed on the Electronic Control Units and they need to exchange large amount of data with real-time constraints. In this context, the communication system plays a major role and it has to respect stringent dependability constraints. Security, especially with the widespread of wireless networks, is now becoming a serious matter of concern too. In this talk, we will review the main threats to dependability and security in automotive communication systems, the existing technical solutions to attain them, and, highlight areas where developments might be needed.
This White Paper talks of different aspects of Hardware and Software co-design with respect to embedded product design and the need need for co-design along side many more aspects.
Autonomous driving requires safety considerations and the need of “fail operational” requires redundancy. In the networking portion of a car, this may mean separate networks, possibly of different technologies. Or it could mean a network topology and technology that supports scalable redundancy, like Ethernet TSN.
This presentation focuses on IEEE 802.1CB-2017, which is the TSN standard that supports data redundancy through the network. Various network topologies are examined. The relative costs of adding TSN redundancy for these topologies (including some, or all of, the end-stations/ECUs & bridges) are examined for various bandwidth utilizations, along with the expected packet loss. Each topology and bandwidth will be modeled under various bit-rate error values with the results discussed.
This presentation aims at providing a clear understanding of the TSN standards that support redundancy, and an understanding of the cost/benefit tradeoffs so proper engineering decisions can be made and proper expectations set.
ANSYS SCADE Usage for Unmanned Aircraft VehiclesAnsys
SCADE on-board the UAS P.1HH HammerHead
The Use of SCADE to develop the P.1HH Vehicle Control & Management System (Integrated Modular Avionics System) greatly reduced development time and effort.
Learn more about ANSYS SCADE Solutions for Aerospace & Defense http://bit.ly/1EdcsOJ
OLA Conf 2002 - OLA in SoC Design Environment - paperTim55Ehrler
The integration of Open Library Architecture (OLA) libraries within nano-technology design environments can positively impact SoC design cycle times. Consistent calculation of desired information across a standard application programming interface (API) ensures analysis convergence among tools, eliminates data exchange processing and storage requirements, and significantly reduces iterations through design processes steps.
Insights on the Performance and Configuration of AVB and TSN in Automotive Ap...RealTime-at-Work (RTaW)
Switched Ethernet is profoundly reshaping in-car communications. To meet the diverse real-time requirements in automotive communications, Quality-of-Service protocols that go beyond the mere use of priorities are required. In this work, the basic questions that we investigate on a case-study with diverse and demanding communication requirements is what can we expect from the various protocols aimed at providing a better timing Quality of Service on top of Ethernet? And how to use them? Especially how to use them in a combined manner. We will focus on the Credit-Based Shaper of AVB, the Time-Aware Shaper of TSN and the use of priorities as defined in IEEE802.1Q. The performance metrics considered are the distributions of the communication latencies, obtained by simulation, as well as upper bounds on these quantities obtained by worst-case schedulability analysis. If there have been over the last 5 years numerous studies on the performance of AVB CBS, the literature on comparing AVB to TSN and other candidate protocols is still sparse. To the best of our knowledge, this empirical study is the first to consider most protocols currently considered in the automotive domain, with the aim to gain insights into the different technological, design and configurations alternatives. In particular, an objective of this study is to identify key problems that need to be solved in order to further automate network design and configuration.
[EWiLi2016] Towards a performance-aware power capping orchestrator for the Xe...Matteo Ferroni
In the last few years, multi-core processors entered into the domain of embedded systems: this, together with virtualization techniques, allows multiple applications to easily run on the same System-on-Chip (SoC). As power consumption remains one of the most impacting costs on any digital system, several approaches have been explored in literature to cope with power caps, trying to maximize the performance of the hosted applications. In this paper, we present some preliminary results and opportunities towards a performance-aware power capping orchestrator for the Xen hypervisor. The proposed solution, called XeMPUPiL, uses the Intel Running Average Power Limit (RAPL) hardware interface to set a strict limit on the processor’s power consumption, while a software-level Observe-Decide-Act (ODA) loop performs an exploration of the available resource allocations to find the most power efficient one for the running workload. We show how XeMPUPiL is able to achieve higher performance under different power caps for almost all the different classes of benchmarks analyzed (e.g., CPU-, memory- and IO-bound).
Full paper: http://ceur-ws.org/Vol-1697/EWiLi16_17.pdf
In this webinar, learn how OPAL-RT's state-of-the-art Hardware-in-the-Loop (HIL) simulation solutions empower engineers to design and test ECUs, and other integrated power electronic systems and controllers, with efficiency.
Iben from Spirent talks at the SDN World Congress about the importance of and...Iben Rodriguez
@Iben Rodriguez from @Spirent talks at the SDN World Congress about the importance of and issues with NFV VNF and SDN Testing in the cloud.
#Layer123 Dusseldorf Germany 20141016
2011-11-03 Intelligence Community Cloud Users GroupShawn Wells
Hosted by TMA, spoke about Red Hat's virtualization portfolio, RHEV & KVM technical updates (Xen vs KVM, sVirt), RHEV 3, and security automation (OpenSCAP).
Video and slides synchronized, mp3 and slide download available at URL http://bit.ly/2qoUklo.
Mark Price talks about techniques for making performance testing a first-class citizen in a Continuous Delivery pipeline. He covers a number of war stories experienced by the team building one of the world's most advanced trading exchanges. Filmed at qconlondon.com.
Mark Price is a Senior Performance Engineer at Improbable.io, working on optimizing and scaling reality-scale simulations. Previously, he worked as Lead Performance Engineer at LMAX Exchange, where he helped to optimize the platform to become one of the world's fastest FX exchanges.
Microservices and Deployment MethodologiesYash Gupta
Presented by Successive Technologies at Nasscom, this presentation explores why Microservice Architecture is preferred over monolithic apps and how to deploy and manage microservices.
Optimising Service Deployment and Infrastructure Resource ConfigurationRECAP Project
This is a presentation delivered by Alec Leckey (Intel) at the 2nd Data Centre Symposium held in conjunction with the National Conference on Cloud Computing and Commerce (http://2018.nc4.ie/) on April 10, 2018 in Dublin, Ireland.
Learn more about the RECAP project: https://recap-project.eu/
Install the Intel Landscaper: https://github.com/IntelLabsEurope/landscaper
Plan with confidence: Route to a successful Do178c multicore certificationMassimo Talia
The modern approach Multi-Processor in the civil and military Embedded equipments certification. The Processor assessment is conduct by Rockwell Collins Inc., the operating system selection is conducted by Windriver Inc.
WSO2 Customer Webinar: WEST Interactive’s Deployment Approach and DevOps Prac...WSO2
To view recording please use below URL:
http://wso2.com/library/webinars/2016/06/west-interactives-deployment-approach-and-devops-practices/
For nearly 30 years West Interactive Services has been creating communication solutions that empower enterprises worldwide to strengthen customer engagement. As a customer of WSO2 since 2012, WEST has built solutions using WSO2 API Manager, WSO2 Business Activity Monitor (WSO2 BAM), WSO2 Enterprise Service Bus (WSO2 ESB), WSO2 Data Services Server (WSO2 DSS), WSO2 Application Server and WSO2 Identity Server which facilitate nearly 300 million unique customer interactions each month.
The most recent deployment with WSO2 allows WEST interactive to expose client connections, data sources and application logic through a common protocol and messaging architecture. This is achieved using a combination of WSO2 API Manager, WSO2 ESB, WSO2 DSS, WSO2 Application Server and WSO2 Message Broker. This webinar will discuss the DevOps related theories and practices that have been followed by WEST during the process of designing, building and maintaining this part of the solution. These will address the following areas:
Design process of the solution
Deployment and production hardening practices
Runtime artifacts and lifecycle management
DevOps, virtualization and automation
Troubleshooting and debugging practices
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
POLYTEDA LLC, a provider of semiconductor design software and PV-services announced the general availability of PowerDRC/LVS version 2.2.
This release is dedicated to delivering fill layer generation for multi-CPU mode, new KLayout integration functionality and other significant improvements for multi-CPU mode
A day in the life of an enterprise CIO can be daunting—challenges such as managing complex environments, security and ongoing TCO pressures face us everyday. Addressing these challenges offer opportunities to significantly improve operations, productivity and have an impact on the bottom line if done successfully. To learn more please visit our website here: http://www.cisco.com/web/CA/index.html
An Approach to Overcome Modeling Inaccuracies for Performance Simulation Sig...Pankaj Singh
RNM is finding prominence in functional verification signoff, However there is clear modeling gap when it comes to performance simulation of high-speed SerDes. Sometimes the pre-silicon simulation results show passing results with respect to Jitter tolerance (JTOL) specification which may not match the actual silicon validation results. These performance issues manifest due to inaccuracies of model where it may not comprehend the actual circuit behavior. There is no clear methodology to overcome these model gaps for performance simulation signoff.
This paper discusses in detail the techniques used to accurately model and verify high-speed SerDes systems for performance simulation.
Overcoming challenges of_verifying complex mixed signal designsPankaj Singh
Efficient and Innovative Digital Mixed-Signal (DMS) verification methodology is required to enable effective verification of RX path of SERDES. This presentation describes the usage of Real value models and Capture -Verify approach to verify complex high speed mixed signal design.
Real value models are the backbone of DMS methodology. Real value models are created for all critical modules in Receive path like Equalizer and Sampler and its associated peripheral modules. It is critical to make sure created models are functionally equivalent to respective designs. This is achieved by verifying each created model with respective designs for all functional modes. While the Real Value models are effective in meeting overcoming the simulation performance bottleneck by achieving 10x faster simulation time; the Nonlinearity factors of the front-end design are not represented accurately in discrete domain real value models for next generation of SerDes Design at very high data rate.
To overcome this problem, a novel approach called ‘capture and verify’ is used for verifying the jitter tolerance and eye parameters. In this approach, waveforms from spice level verification of Equalizer for different functional modes are captured and stored. These stored waveforms are used to generate run time table-based models to accurately represent the analog modules. These run time models are used in top-level simulations along with real value models thereby achieving required goal of simulation performance without compromising on accuracy of results.
The complete Design Verification (DV) environment is developed using UVM-e Methodology. Verification environment contains model for transmitter with all de-emphasis settings along with protocol compliant channels with multiple attenuations. DV infrastructure has hooks to plug-in required channel models to verify SERDES. This verification environment is also capable of verifying the clock data recovery (CDR) path of the design using protocol compliant jitter and Spread-Spectrum Clocking (SSC) stimulus.
The real value modelling bridges the gap between the performance requirements of the simulation and accuracy limitations of design. A significant speed-up in simulation performance is achieved (almost 10X in this case) by replacing with functionally equivalent real value models for mixed signal designs. Usage of Capture and Verify methodology with spice simulation waveforms for critical blocks ensures non-linearity of the next generation high speed SerDes design is well captured in simulations provide complete comprehensive solution for high speed mixed signal designs.
Qualifying a high performance memory subsysten for Functional SafetyPankaj Singh
Addressing the Challenges of Safety verification for LPDDR4.
✓Avoid traditional approach of starting functional safety after functional verification : Iterative and expensive development phase
1. Functional Safety Need to be Architected and not added later.
2. Safety Analysis must start prior to implementation. ‘Design for safety/verification’
3. Reuse & Synergize : Nominal and Functional Safety Verification.
✓Fault optimization with formal and other techniques is necessary to overcome challenges with scaling simulation and analysis.
✓Integrated push button fault simulation flow is need of hour and saves verification engineers time.
✓Analog defect modelling and coverage can be performed based on IEEE P2427.
Safety Verification and Software aspects of Automotive SoCPankaj Singh
IP-SoC Conference 2017 Grenoble
Automotive industry has evolved over last 100 years. Electronic systems were
introduced into the automotive industry in 1960. Since then the complexity has grown
many fold and today’s automobiles have as many as 150 programmable computing
elements or Electronic Control Units(ECUs) with several wiring connections.
The software content has also increased significantly with today’s car having more than
100 million of lines of software code.
This increased hardware and software complexity increases the risk of failure that could
impact negatively on vehicle safety. This has led to concerns regarding the validation of
failure modes and the detection mechanisms. Car maker and suppliers need to prove
that, despite increasing complexity, their electronic systems will deliver the required
functionality safely and reliably.
This presentation describes the challenges and methodology related to Safety
verification and Software development aspects of Automotive Microcontroller SoC.
Panel:The secret of Indian leadership in Electronic Design skill... From Desi...Pankaj Singh
Panel Discussion: D&R IP-SoC, Bangalore 2015. Topic:The secret of Indian leadership in Electronic Design skill... From Design to Services to Embedded Software
Power Optimization with Efficient Test Logic Partitioning for Full Chip DesignPankaj Singh
This paper introduces efficient test logic partitioning to not only optimize and reduce the overall test power during silicon validation but also reduce power in functional mode by shutting off test logic. Approach used in optimizing test power has been successful in reducing overall functional mode leakage power by 50% without any additional area overhead or test time increase. Results shared are based on WIMAX full chip SoC design.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Le nuove frontiere dell'AI nell'RPA con UiPath Autopilot™UiPathCommunity
In questo evento online gratuito, organizzato dalla Community Italiana di UiPath, potrai esplorare le nuove funzionalità di Autopilot, il tool che integra l'Intelligenza Artificiale nei processi di sviluppo e utilizzo delle Automazioni.
📕 Vedremo insieme alcuni esempi dell'utilizzo di Autopilot in diversi tool della Suite UiPath:
Autopilot per Studio Web
Autopilot per Studio
Autopilot per Apps
Clipboard AI
GenAI applicata alla Document Understanding
👨🏫👨💻 Speakers:
Stefano Negro, UiPath MVPx3, RPA Tech Lead @ BSP Consultant
Flavio Martinelli, UiPath MVP 2023, Technical Account Manager @UiPath
Andrei Tasca, RPA Solutions Team Lead @NTT Data
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
PHP Frameworks: I want to break free (IPC Berlin 2024)
OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY
1. OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC:
PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY
PANKAJ SINGH, ASHISH JAIN, NARENDRA KAMAT
2. 2| The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
OUTLINE
POWER MANAGEMENT FOR IMPROVED ENERGY EFFICIENCY AND
VERIFICATION CHALLENGES
SKIN TEMPERATURE AWARE POWER MANAGEMENT
BATTERY BOOST
PERFORMANCE ANALYSIS ENVIRONMENT
REUSE VERIFICATION ENVIRONMENT
SOC VERIFICATION
UVM METHODOLOGY & WHAT NEXT.
CHALLENGES/GAPS: HW-SW DEBUG, VIRTUAL PROTOTYPE MODEL.
EMULATION CONFIGURATION OPTIONS.
Power Mgmt for
Energy Efficiency &
Verification
Challenges
Performance
Analysis
Verification
Environment
SoC Verification
Challenges
3. POWER MANAGEMENT FOR
IMPROVED ENERGY EFFICIENCY AND
VERIFICATION CHALLENGES
Power Mgmt. for
Energy Efficiency &
Verification
Challenges
Performance
Analysis
Verification
Environment
SoC Verification
Challenges: UVM,
HW-SW Debug, VP,
Emulation
4. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
4
POWER MANAGEMENT UNIT
* Physical monitors on the chip/platform, or digital estimators
based on activity, other parameters
Power
Monitors
Current
Monitors
Temperature
Monitors
Monitors*
Filters &
Comparators
>
<
=
Platform
Constraints
CPU
Graphics
NorthBridge/
Memory Interface
Multimedia
APU Power
Controllers
Operating
points for
different
APU
Entities
APU
activity,
power,
thermal
inputs
PLATFORM INFRASTRUCTURE CONSTRAINTS
Platform Component Constraint
Cooling solution/Heat sink Heat dissipation ability to maintain die & system temperature
AC Brick Power/Current carrying capability
Battery pack Power/Current carrying capability
Voltage Regulators/FETs on the board Current carrying capability, thermals
5. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
5
MUCH MORE CONFIGURABILITY AND FLEXIBILITY
APU
Power/
Thermal
Profile
APU
Power/
Thermal
Profile
Platform
Power
and
Thermal
Profile
Old Paradigm: Adjust platform design to fit the APU’s power/thermal profile
APU
Power/
Thermal
Profile
Platform
Power
and
Thermal
Profile
Platform
Power
and
Thermal
Profile
New Reality/Challenge: Configure APU to fit the platform’s power/thermal profile
6. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
6
DYNAMIC CONFIGURABILITY
2-in-1 Convertibles:
Clamshell versus tablet/slate mode
Docked
versus
Undocked Modes
System
BIOS
Platform Events
Docked/Undocked,
Tablet/Clamshell Mode
Changes
Power
Management
Unit
Frequency/
Power Limits
To match the Config
Requirements
Parameters Config 1 (Docked) Config 2 (Undocked) Config 3 (…)
TDP Limit 18W 12W 15W
Surface Temp Limit 50C 42C 45C
… … … …
7. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
7
SKIN TEMPERATURE AWARE POWER MANAGEMENT
Without STAPM
With STAPM
Without STAPM
With STAPM
8. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
8
BATTERY BOOST
= Increased
efficiency
Energy use drops While Performance
increases
Based on 3DMark11 (Performance preset) on 15W quad-code Kabini (KB 15w4c) and 15W quad-code
Beema (BM 15w4c) . Pre-production engineering samples of APUs used with 2x8GB DDR3
1866 RAM, 1280x720 display panel, Windows 8.0 and unreleased reference driver
9. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
9
VERIFICATION CHALLENGES
Complex interaction among various hardware components and software
components require a multi-level verification approach
Software readiness as important and critical for time-to-market as a robust and
verified hardware design
Verification environment not only needs to model SOC components but
System/Platform components as well
IP level verification of
basic blocks like the
activity monitors
SOC level verification
of the accumulator and
controller logic
APU
FIRMWARE
BIOS
DRIVER
Software validation
using a behavioral
level model of the
hardware
HW-SW cosim and/or
Emulation for verification
of interfaces between
hardware components
and software modules
10. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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VERIFICATION CHALLENGES
Typically software readiness and hardware schedules are mis-aligned
‒ Software development delayed with respect to hardware development to bank on the
time between design tapeout and silicon arrival
‒ Puts any software-hardware co-verification at great risk
‒ Alignment of software and hardware schedules a ‘must-have’ requirement for
successful execution of current generation power management architecture
IP Level Verification
SOC Verification
HW/SW Co-verification/Emulation
Software (BIOS, Driver, Firmware) Verification
11. PERFORMANCE ANALYSIS
ENVIRONMENT
Power Mgmt. for
Energy Efficiency &
Verification
Challenges
Performance
Analysis
Verification
Environment
SoC Verification
Challenges: UVM,
HW-SW Debug, VP,
Emulation
12. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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SOC PERFORMANCE
Trends:
‒ Chip industry: Lot more disparate
client IPs on one chip…
‒ Platform/software use cases: Big
Data, HPC, more displays, higher
resolution…
Memory is the bottleneck
‒ Interconnect performance is
critical to maximize potential of
engine IPs
Each client has different general
characteristics
‒ CPU: Latency sensitive for single-threaded
performance; latency-under-
load
‒ GFX: Massively parallel
workloads; huge appetite for
memory bandwidth
‒ Display and Real-time clients:
Burst traffic, with demanding
QoS requirements
Visual
Computing
HPC
Big
Data
Evolutionary
design
System-on-
Chip
Reuse
New Class of
Applications: Large Data
Sets, Massively Parallel
New Class of
Constraints: IP Reuse,
Large Complex SOCs
Memory
Subsystem
(Interconnect)
Performance
Applications demand
high-performance
memory access
Larger no# clients
demand high
performance memory
access
13. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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PERFORMANCE VALIDATION FOR INTERCONNECT IP
Ensure that performance metrics of interest meet the product goals
Metrics:
‒ Peak bandwidth
‒ DRAM utilization efficiency
‒ Unloaded latency for different clients
‒ Loaded latency curve
Use RTL simulation
Related approach is to use an abstract performance model.
14. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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BANDWIDTH MEASUREMENT AT INTERFACE
Inbound Data
• Record number of bytes
moved
Outbound Data
• Record number of bytes
moved
LATENCY MEASUREMENT AT INTERFACE
Inbound Request
• Save tag/timestamp
Outbound Response
• Match tag
• Delta with saved timestamp
• Record latency
15. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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INTERCONNECT IP
Interconnect
CPU0 CPU1
IO GPU
DRAM
Chn 1
DRAM
Chn 0
Interface points
for primary
performance
measurements
- Need low development/maintenance cost
- Interfaces not necessarily identical
Key
challenges
- Reuse existing functional verification code
- Leverage industry-standard UVM framework
- Software engineering approach
Approach
DESIGN PARAMETERS
16. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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TRACKER CLASS
Simple/minimal code
Two types:
Bandwidth[B.W] &
Latency
Data structures to track
the selected
metric[B.W and
latency]
One tracker per metric
per interface
Scoreboard instantiates
tracker objects, and
invokes track method
when transactions are
observed
17. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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PERFORMANCE SCOREBOARDS AT EACH INTERFACE
Interconnect
CPU0 CPU1
IO GPU
DRAM
Chn 1
DRAM
Chn 0
SB SB
SB SB
SCOREBOARD FUNCTIONS
Callbacks registered with
verification monitors for all
data transactions (UVM:
analysis ports)
Master (instantiate) tracker
objects
When callback received,
invoke track method on all
trackers.
18. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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END OF SIMULATION
Top-level performance environment module
queries each scoreboard for metrics
Each scoreboard queries each instantiated
tracker for metrics
Bottom-up rollup of data, formatted and
printed in a file for analysis.
Env
CPU0
Scoreboard
BW Tracker
Latency
Tracker
CPU1
Scoreboard
BW Tracker
Latency
Tracker
GPU
Scoreboard
BW Tracker
Latency
Tracker
IO
Scoreboard
BW Tracker
Latency
Tracker
19. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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ADVANTAGES
Minimal new code (low development/maintenance costs)
Leverages existing verification testbench infrastructure
Exploits recurring measurement patterns
Code portable from IP-level to SOC-level
UVM (standard) compliant
20. SOC VERIFICATION CHALLENGES
Power Mgmt. for
Energy Efficiency &
Verification
Challenges
Performance
Analysis
Verification
Environment
SoC Verification
Challenges: UVM,
HW-SW Debug, VP,
Emulation
21. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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VERIFICATION CHALLENGE : INCREASED COMPLEXITY, INCREASE IN
CORES AND REDUCED TIME TO MARKET
Baseline Design
Design Complexity
Power Management
Firmware
Software
Baseline
Design
Design
Complexity
Power
Management
Firmware
Software
Complexity
Time
Reduced Design Cycle
Increased Complexity
Design Cycle
0
5
10
15
20
25
0
20
40
60
80
100
120
140
2006 2011 2014
IPs (left axis)
Average IP and Processor Core trends
in advanced SoCs
Source: Caspi, HVC 2013
IP Cores
Embedded Processor Cores
Ref: [3]
22. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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UVM
UVM 1.2
Testbench
UVM Methodology – A big leap in Verification. What Next?
reusable
Source : uvm cookbook
23. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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HW-SW DEBUG
SoC verification involves lot of embedded
software
The number of heterogeneous cores are
growing
‒ Need for the debug process capability of simultaneously
viewing multiple cores both from a HW perspective as
well as from programmers point of view
SoC debug need a simultaneous view of both
hardware and software
‒ RTL and gate level, including HDL source code,
waveform, schematic, assertion, testbench, transaction
and power-aware debug
‒ Programmer's view of both C/C++ and assembly code as
well as memory, register and breakpoint windows
‒ No standard tool or accepted methodology exist. The
debug tool released this year by EDA company’s could
evolve and fill the HW-SW gap.
24. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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VIRTUAL PROTOTYPE MODEL - GAPS
RTL and VP are developed in two parallel streams
VP model used for Architecture exploration, SW development, Reference model
for verification. However gaps exist in developing good quality of VP model
‒ Largely the firmware code is applied to verify the VP – may not cover entire VP . No
randomization used.
‒ Coverage still largely eludes the VP verification. Tools available in market do not
address the coverage topic in a straight forward way especially toggle coverage
Therefore, determining “Are we Done? “ for VP verification poses big gaps
25. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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EMULATION: WHEN TO USE WHICH CONFIGURATION?
Characteristics
In-circuit
Emulation
Embedded Target
Emulation
Hybrid
Virtual/Emulation
Why
• Connecting real hardware to
your design
• Real peripheral device testing
• Real-world traffic
• Enables Save/Restore
• Easily re-locatable
• Additional debug monitoring
• Enables Save/Restore
• Easily re-locatable
• Capacity savings
• Highest performance
• Improved software debug
When to use
• When testing in real
environment with real devices
is important
• When CPU validation is a
higher priority
• When highest model accuracy
is required
• When getting deep into
workloads is important
• When CPU validation is a
higher priority
• When capacity is available
• Need to run large software
workloads
• When CPU validation is a
lower priority
• Fast initial bring-up of OS
Who
• Platform engineering teams
• Design teams
• Product engineering teams
• Platform engineering teams
• Design teams
• Software teams
• GFX driver developers
• Platform engineering teams
• Design teams
Reference: [3] cdnlive ’14 . Alex Starr, Brian Fisk
26. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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SUMMARY
EFFICIENT POWER MANAGEMENT TECHNIQUES SUCH AS STAPM AND BATTERY
BOOST FOR IMPROVED ENERGY EFFICIENCY [PERFORMANCE/WATT]
DEVELOPING PERFORMANCE ANALYSIS ENVIRONMENT BY REUSING EXISTING
VERIFICATION ENVIRONMENT
HOLISTIC VIEW OF SOC VERIFICATION :
EVOLUTION OF UVM METHDOLOGY, UVM 1.2 AND CHALLENGES WITH MULTI LANGUAGE
SUPPORT/AMS SUPPORT.
EDA INDUSTRY/TOOL CHALLENGES WITH HW-SW DEBUG, VP MODEL VERIFICATION.
H/W ASSISTED SIMULATION ACCELERATION, CHOOSING EMULATION CONFIGURATION FOR
YOUR DESIGN.
Power Mgmt for
Energy Efficiency &
Verification
Challenges
Performance
Analysis
Verification
Environment
SoC Verification
Challenges
27. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
| OCTOBER 31, 2014 |
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THANKYOU
28. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014
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REFERENCES
1. Applying AMD's "Kaveri" APU for Heterogeneous Computing. Hot Chips 26 -
Palo Alto, CA. Bouvier Dan, Sander Ben
2. UVM CookBook
3. Complementing In-circuit Emulation with Virtualization for Improved
Efficiency, Debug Productivity, and Performance. CDNLIVE SI VALLEY 2014.
Alex Starr, Brian Fisk
4. Harry Foster, Mentor Graphics. DAC’14