The document provides an overview and summary of Nobuya Okada's educational background, work experience, achievements, skills, and personality. It includes 3 sections: 1) Education/career overview which lists his educational history and work experience. 2) Job details which summarizes his major achievements and roles developing various ASICs and IPs over 21 years of experience. 3) Other profile which outlines his patent/awards, language skills, personality traits, and commitments.
FPGA introduction for absolute beginners
- What is inside FPGA (Altera example)
- What are the major differences between firmware development for MCU and FPGA
- Some very basics of Verilog HDL language (by similarities with C/C++)
- Testbench approach and Icarus simulator demonstration
- Altera Quartus IDE demonstration -- creating project, compilation, and download
- Signal-Tap internal logic analyzer demonstration
(Verilog source code examples attached inside presentation)
A review of the history of digital design throughout the years until the era of programmable logic, and a detailed exploration of the architecture of FPGA chips, followed by an introduction to SoC FPGAs and some of their benefits.
FPGA introduction for absolute beginners
- What is inside FPGA (Altera example)
- What are the major differences between firmware development for MCU and FPGA
- Some very basics of Verilog HDL language (by similarities with C/C++)
- Testbench approach and Icarus simulator demonstration
- Altera Quartus IDE demonstration -- creating project, compilation, and download
- Signal-Tap internal logic analyzer demonstration
(Verilog source code examples attached inside presentation)
A review of the history of digital design throughout the years until the era of programmable logic, and a detailed exploration of the architecture of FPGA chips, followed by an introduction to SoC FPGAs and some of their benefits.
Design of LDPC Decoder Based On FPGA in Digital Image Watermarking TechnologyTELKOMNIKA JOURNAL
LDPC code and digital image watermarking technology, which is an effective method of digital copyright protection and information security, has been widely used. But this is a multi-disciplinary, multi technology application scheme. In order to realize FPGA design of LDPC decoder in the application scheme, an effective implementation method of digital watermarking application system must be found. In this paper, MATLAB software and Qt development environment are combined to achieve the digital watermarking application software design. It could get real-time input data for the LDPC decoder. Then the hardware of the LDPC decoder is primarily implemented by FPGA in the digital image watermarking system. And the serial port is used to make the output data of the decoder back to computer for verification. Through the simulation results, the Modelsim time simulation diagram is given, and the watermark image compared with the original image is got. The results show that the resource usage of our system is few, and the decoding rate is fast. It has a certain practical value.
The presentation is dedicated to advantages and disadvantages of FPGA (Field-Programmable Gate Array): its construction and speed features, as well as security elements. It also deals with such issues as new devices synthesis and expanding the existing hardware functionality, realisation of microprocessors for specialized tasks, as well as OpenCL, a system for parallel calculations.
This presentation by Andriy Smolskyy (Lead Software Engineer, GlobalLogic) was delivered at Embedded TechTalk Lviv on June 17, 2015.
This presentation contains the basics of FPGA design, what are HDL [hardware description languages], how VHDL design works on FPGA, what are the high tech applications, FPGA R & D opportunities, latest FPGA tools, resources and the National Activities on FPGA happened at Nepal.
In this presentation we described implementation of Digital Signal processing on FPGA. If you still have any query about Digital Signal processing on FPGA then feel free to contact us at:
http://www.siliconmentor.com/
eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.
Field-programmable gate array\
only for these students that are intrested in Field-programmable gate array
field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as they were for ASICs
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable). However, programmable logic was hard-wired between logic gates.[6]
In the late 1980s, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.[6]
Some of the industry's foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985.
Design of LDPC Decoder Based On FPGA in Digital Image Watermarking TechnologyTELKOMNIKA JOURNAL
LDPC code and digital image watermarking technology, which is an effective method of digital copyright protection and information security, has been widely used. But this is a multi-disciplinary, multi technology application scheme. In order to realize FPGA design of LDPC decoder in the application scheme, an effective implementation method of digital watermarking application system must be found. In this paper, MATLAB software and Qt development environment are combined to achieve the digital watermarking application software design. It could get real-time input data for the LDPC decoder. Then the hardware of the LDPC decoder is primarily implemented by FPGA in the digital image watermarking system. And the serial port is used to make the output data of the decoder back to computer for verification. Through the simulation results, the Modelsim time simulation diagram is given, and the watermark image compared with the original image is got. The results show that the resource usage of our system is few, and the decoding rate is fast. It has a certain practical value.
The presentation is dedicated to advantages and disadvantages of FPGA (Field-Programmable Gate Array): its construction and speed features, as well as security elements. It also deals with such issues as new devices synthesis and expanding the existing hardware functionality, realisation of microprocessors for specialized tasks, as well as OpenCL, a system for parallel calculations.
This presentation by Andriy Smolskyy (Lead Software Engineer, GlobalLogic) was delivered at Embedded TechTalk Lviv on June 17, 2015.
This presentation contains the basics of FPGA design, what are HDL [hardware description languages], how VHDL design works on FPGA, what are the high tech applications, FPGA R & D opportunities, latest FPGA tools, resources and the National Activities on FPGA happened at Nepal.
In this presentation we described implementation of Digital Signal processing on FPGA. If you still have any query about Digital Signal processing on FPGA then feel free to contact us at:
http://www.siliconmentor.com/
eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.
Field-programmable gate array\
only for these students that are intrested in Field-programmable gate array
field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as they were for ASICs
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable). However, programmable logic was hard-wired between logic gates.[6]
In the late 1980s, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.[6]
Some of the industry's foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985.
POLYTEDA LLC, a provider of semiconductor design software and PV-services announced the general availability of PowerDRC/LVS version 2.2.
This release is dedicated to delivering fill layer generation for multi-CPU mode, new KLayout integration functionality and other significant improvements for multi-CPU mode
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal1
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to
describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on
an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving.
This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the
OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL
code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show
that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is
given.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is given.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving.
This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the
OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC.
5. Educational background Overview Hokkaido University 1986/4 – 1990/3 Graduated with Bachelor’s degree in Electrical Engineering. Majored in Semiconductor Properties. Graduation thesis Theme Study on Properties of InGaAs Photo Conductive Detector. Laboratory Semiconductor Properties Laboratory Adviser Professor : Hideki Hasegawa Tutor : Kouichi Iizuka Overview InGaAs(III-V Group compound semiconductor) is ideal material for photo conductive detector with its property such as: - Narrow band gap - High electron mobility - Adaptive wave length(800~2600nm) suits for optical fiber(1.3um/1.55um) Main activity Developed simulation model of InGaAs Photo Conductive Detector. Experiment on Lithography, Etching Process. Semiconductor band structure Photovoltaic effect
8. Job details Major achievement Development of 0.18um ASICs : 1998/10 – 2001/12 Infrastructure As a 0.18um ASIC startup member, collaborated with corresponding department, studied about Library, EDA Tool Kit, methodology for Signal-Integrity, etc. Product A Developed ASIC for 10G-DWDM FEC(Dense Wavelength Division Multiplexing Forward Error Correction), which consists of 2x16ch for each Tx and Rx using 666MHz LVDS I/F, 1.5MGate @ 166MHz, and a few FIFOs. Logic density was low, but for the reason of critical timing, promoted Hierarchical-Design method for both of Front-(customers-side) and Back-end. Considering the immaturity of the process, took contingency measures such as pessimistic antenna factor, OCV(On-Chip-Variation) factor, etc. Design margin made from these measures had concealed all the degradation of process spec decided after Product development, and achieved no re-spin. cf : http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1012787 Product B Developed ASIC for W-CDMA base station, consists of 3x2 ch SerDes using 666MHz LVDS I/F and a small amount of Logic To achieve LVDS signal transmission on customer’s equipment, examined PCB design, Package property, and Pin arrangement. Other Products After developing above 2 Products and paving the road, then assisted the other junior members with their Product development. Total number of Products was about 10.
9. Major achievement Job details Development of Java accelerator IP : 2001/12 – 2003/2 Java accelerator IP Examined method for performance improvement with senior Assistant Manager, who originally developed the Java Accelerator. And defined the specification. As an Assistant Manager with 3 junior members, wrote RTL (about 10000 lines:30% of total), verified the function, executed logical synthesis, and interfaced the IP to ASIC development team. In parallel to the IP development, also developed evaluation board with FPGA. Implemented the IP into FPGA and debugged the functions which could not be verified by simulation due to complex test scenario and long execution time. Through the debugging with FPGA and ICE, found a few Bug and gave feedback to ASIC development team by using ECO(Engineering Change Order). This ECO was in time for Tape-out. This Java Accelerator IP was adopted by DoCoMo’s N505x.
10. Major achievement Job details Development of PDC DBB ASIC : 2003/2 – 2004/6 Product C Examined customer’s required specification, analyzed internally with corresponding department, and decided to promote a cutting-edge V850E2 CPU core and peripherals. To obtain customer consent on using V850E2, there were many issues to be solved, such as power consumption, man-power for F/W transplanting, developing KIT status, and the most worried issue was the lack of adoption result. As an Assistant Manager with 3 junior members, organized exclusive FAE team to solve these issues. Developed evaluation board consists of V850E2 prototype sample, FPGA, Memories and pre-generation baseband ASIC which has “External CPU Mode”. This board emulated almost the same system architecture of the target ASIC After initial test, brought up the on-site evaluation environment including ICE. Supported customer’s F/W development. This accelerated launch of customer’s Set. Implemented new Memory controller, which has Mobile SDRAM/Sync-burst Flash ROM access function, into FPGA. And debugged the Memory controller on board. Found a few functional Bug in Memory controller, and made a feedback to ASIC before Tape-out. Conducted design review of Memory controller with customer. This DBB ASIC was adopted by DoCoMo’s N506x.
11. Major achievement Job details Development of GSM/GPRS/EDGE DBB IP : 2004/11 – 2008/2 GSM/GPRS/EDGE DBB IP Having no design resource in GSM/GPRS/EDGE, searched for IP venders, and finally agreed in contract with TTPCom. Conducted IP acceptance inspection with 2 members. Q&A between TTPCom basically on teleconference, or by face-to-face meeting with Account manager of TTPCom. As a technical manager, managed a team of 20 members. Designed H/W specification with 7 members, divided into sub-functions, and assigned each function to individual members. RTL code size was 43474 lines(VHDL from TTPCom) plus 20910 lines(Verilog-HDL). Developed GSM/GPRS/EDGE function sample chip, provided it to board evaluation team and S/W development team. For integrating into W-CDMA/GSM and Application Processor 1-chip SoC, modified bus architecture from AHB to AXI, in order to improve performance. This W-CDMA/GSM/Application Processor 1-chip SoC was adopted by DoCoMo’s N905x and N906ix.
12. Design flow experience: Job details ASIC design flow Tape-out Wafer Fab Program development Test card/board development Wafer Test Assembly Final Test Characteristic Evaluation Mass Production Release Sample Shipment Acknowledgement from Customer C++/SystemC (TLM) Simulation Test bench (TLM) High Level Synthesis RTL Simulation Constraint Test bench (SystemVerilog)
13. Design flow experience: Job details IP / FPGA design flow Design Specification Design checker RTL coding Simulation Logic Synthesis DFT / ATPG Design Rule Check STA SDF Interface with Back-end RTL / Netlist Simulation Coverage check Power Analysis Formal Verification Logic Synthesis P & R FPGA Implementation Board Specification Board Design Board Ordering Board Inspection Evaluation with ICE/Logic Analyzer
14. Work involved: Job details Category detail Process technology 0.8 / 0.5 / 0.35 / 0.25 / 0.18 um 130 / 90 / 65 nm Developed Product DBB for PDC/W-CDMA ASIC for W-CDMA Base station ASIC for PC graphic/peripheral controller ASIC for optical transmission ASSP for ADSL modem IP Java accelerator / DBB for GSM / ATM TC layer Used IP CPU : ARM9/11 / V850E/E2 DSP : in-house Peripheral : MEMC / DMAC / UART / INTC / DCU Memory : 1pSRAM / 2pSRAM / ROM Other : SerDes Interface PCI / HSTL / SSTL / SSTL-2 / SSTL-18 / LVDS Analog PLL / A-D converter / D-A converter / Analog switch / Comparator Discrete FPGA / Mobile SDRAM / Sync Flash Rom
20. Personality Other Profile Character Communication type Pleasure Reading, Movies, Music, Travel, Studying English, Home video editing, Walking with my dog
