This document provides biographical information about an experienced engineer with expertise in system-on-chip (SoC) design, field-programmable gate array (FPGA) design, application-specific integrated circuit (ASIC) design, embedded systems design, and high-speed serial connectivity. The engineer has over 20 years of experience in the electronics industry working on advanced product developments. Educational background includes a BSEE degree and professional training in areas like SoC design, FPGA design, Verilog, system verification, and more. References and samples of past work are also provided.

1. Who is this guy? Present San Diego California 2000 1997 Ottawa Canada 2009 2006 San Diego California Optical Networks Division 1997 1993 Ottawa Canada * nowMotorola/VideoDistributionDivision * nowMitel/Communications Infrastructure Division 1993 1989 Sarajevo Bosnia Herzegovina 2006 2000 San Diego California www.energoinvest.com 1989 1984 BSEE www.etf.unsa.ba { Experienced SoC ~ FPGA ~ ASIC ~ Embedded ~ High-Speed } Designer | Architect

2. SoC Designer | Architect SoC is the chip hosting microcomputer subsystem It typically also sports significant 3rd party IP content SoC is the art of partitioning & creating clean structure with natural, well defined (often standardized) interfaces and buses (AMBA/AXI/AHB/APB, CoreConnect, OpenCoreProtocol, Avalon,…) It’s like my boards (of the `90s), now on the chip A typical ASIC designer lacks the system, application and use-case perspective, which I describe as: ‘Design Functionality, not only RTL code’

3. My SoC design/architecture sample

4. FPGA Designer FPGA is the front-end heaven of Logic Design Logic (If-Then implications) is my strong attribute! Typical ASIC designer produces too ‘cloudy’ RTL which threatens timing closure: FPGA RTL is harder to write! FPGA expertise is also about befriending with underlying gate/clock/interconnect fabric, mega-macros, adapting to them & making choices within the given physicals Xilinx is my specialty: V2Pro, Spartan3, V4, Virtex5 ‘Programmable Imperative ~ Software Defined Silicon’ C-to-Verilog and HPC4mare my passion (and future of electronics) Check my blog: FPGA Day & Night(http://chili-chips.blogspot.com)

5. My FPGA design sample

6. ASIC Designer While FPGA is Logic/RTL/Front-End centric, ASIC has significant Physical/Back-End/Fab workload Tool complexity swells. Tools grow more important. Automation, scripting, processing and filtering of massive netlists and timing reports is often the key I’ve used Synopsys tool flow, TCL, Perl, shell scripting Completed projects in COT and ASIC engagement model (and variants) Worked with standard-cell and full-custom flows; Transistor-level analog designers; Place-n-Route, Packaging guys; DFT gals

7. My ASIC design sample Hard-macro for DDR3 SDRAM PHY – Pure COT, mixed-signal project

8. Embedded & High-Speed Embedded is the computing system (CPU/MCU+mem) with few well defined functions which it excels in Designing one needs good judgment for HW/SW partitioning & great deal of CS in addition to EE. I write firmware in ‘C’ and Assembly and have been through schematics/boards Completed significant work in multi-Gbps serial & high-speed DDR connectivity, wearing both designer and user hat; At board, chip and IP level

9. My Embedded Design Sample First project: 1989/90 ISDN BA Terminal Adapter as an add-on card for the PC ISA bus, based on Intel 80188 micro and Mitel ISDN chipset. I designed all the hardware and wrote device drivers and BIST in ASM86 as ‘C’ externs. Many more projects followed, more complex and higher-speed, but this one remained the dearest…

10. Experience Experience is the breadth of perspective. It’s knowingwhat$, why? and how! Experience is the insight that guides ~ ~ Doing it right in the first pass  It’s knowing what it takes: : Setting realistic goals and expectations. Thanks to experience, one can quickly acquire new domain skills, tools, methodologies…

11. My Experience 20 years in the electronics industry, mostly as the key contributor on advanced, ‘Technology Frontier’ and carrier-class product developments

12. A Snapshot of Professional Training

13. A Snapshot of Professional Training (cont’d)

14. References 1) Jim Lew-Digital Design Manager at AMCC http://www.linkedin.com/pub/9/552/80a Jasmin directly reported to Jim. 2) Shaw Yuan- Sr. Communication Systems Engineer at Entropic http://www.linkedin.com/pub/2/106/2a9 Jasmin worked with Shaw on DSP aspects of FPGA-based proof-of-concept prototype platform for MoCA cable modem technology. 3) Omer Acikel- Digital Communication System Engineer at AMCC http://www.linkedin.com/pub/5/a93/729 Jasmin worked with Omer on using FPGAs to accelerate Simulink/MATLAB sims of a DFE/FFE-based CDR block for 10Gbps long-reach SerDes. 4) LinkedIn Recommendations: View Full Profile: http://www.linkedin.com/in/jasminibrahimovic

15. Thank You! Q&A www.chili-chips.com