This document discusses accelerating verification of high-level synthesis (HLS) blocks using the JEDA HLV Tool Suite. It provides a new verification flow that allows identifying untested and dead code earlier at the SystemC/C-level, improving testbenches faster using faster C models. The JEDA tools provide hardware-aware coverage measurement at the SystemC level that reliably carries over to the RTL level, allowing for both fast time to RTL and efficient verification. This enables achieving true faster time to market by moving verification automation to the high level.

1. Accelerate Your HLS Flow with High Level Verification (HLV) Tool Suite The Next Level of RTL Verification

2. 2 HLV™ for High level synthesis- © 2009 JEDA Technologies, Inc Why HLV ? You are using High Level synthesis To achieve faster time to RTL But still verify HLS block at RTL? Move verification automation to high level also To achieve true faster time to market

3. 3 HLV™ for High level synthesis- © 2009 JEDA Technologies, Inc A SoC Design with HLS BlocksVideo Example CPU (Video Configuration) External Memory Blocks from HLS

6. Improve C-testbench faster with 10-100x faster C-models