With the rapid advances in multimedia and communication system, high capacity signal processing are in demand, so High Speed MAC are essential to improve performance of signal processing System. Multiplication occurs frequently in finite impulse response filters, fast Fourier transforms, discrete cosine transforms, convolution, and other important DSP and multimedia kernels. The objective of a good multiplier and accumulator (MAC) is to provide a physically compact, good speed and low power consuming chip. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power.In These Project I propose a high speed MAC adopting the new SPST implementing approach. This multiplier and accumulator is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. Language: Verilog. Software:Modelsim ,Xilinx ISE

2. The objective of these project is to provide physically
compacted high speed and Low power MAC chip.
With advances in multimedia and communication system
high speed MAC unit makes an improvement in
performance of signal processing systems.
In these project high speed MAC is adopted by
SPST(Spurious Power Suppression Technique)
implementation approach.
The MAC unit is designed by equipping the SPST on
Modified Booth Encoder which is controlled by detection
unit using AND gates.
The total design is coded with Verilog-HDL and the
synthesis is done using Xilinx ISE compiler.

3. The Fused Multiply and add operations was introduced in IBM
POWER1 Processor in 1990.
In 1999 Kahan,Engineer has pointed out MAC with low
significant bits.
 Later a 1-Bit MAC unit is designed, with appropriate geometrics
that gives optimized power, area and delay. The delay is estimated
by control Unit and the data flow between the MAC blocks.
Similarly N-Bit MAC unit is designed and controlled for low power
using a control logic that enables the pipeline stages at appropriate
time.
A Multiplier uses Booth Algorithms and array of full adders or
wallency tree instead of full adder.
A adder uses carry-select or carry-save adder in the operation of
addition in the MAC unit.

4. The proposed method in these project is SPST(Spurious
Power Suppression Techinique),which uses a detection
logical circuit to detect the affective data range of arithmetic
units.Besides there is a data asserting control realized by
using registers to further filter out the useless spurious
signals of arithmetic unit every time when the latched
portion is being turned on.

5. MAC is divided into 4 operational steps i.e.
1.Booth Encoding.
2.Partial Product Summation.
3.Final Addition.
4.Accumilation.
The MAC inputs are obtained from the
memory location and given to the multiplier
block.
The multiplier output i.e.,128bits is given as
the input to carry save adder which performs
addition.
The output of CSA is 129 bit i.e.,1bit is for the
carry (128bit+1bit).Then the output is given to
the accumulator register used in this design is
parallel in Parallel out(PIPO).

13. In Digital Signal Processing MAC is used in Signal filtering,
convolution and decreasing number of inner products.
Optical Communication.
Multimedia Image Processing
Real time signal processing like audio signal processing,
video/image processing or large capacity data processing.

14. The MAC unit operates completely independent of the CPU,it can
process data separately .And there by can reduce CPU load.The
application like optical communication systems which is based on
DSP, require extremely fast processing of huge amount of digital
data.
MAC unit increases system speed, reduces area and power
consumption.

15. The MAC is designed by equipping SPST on a modified booth
encoder which is controlled by a detection unit using an AND gate.
The modified booth encoder will reduce the number of partial
products generated. The SPST adder will avoid the unwanted
addition and thus minimize the switching power dissipation. The
SPST MAC implementation with AND gates have an extremely
high flexibility on adjusting the data asserting time. This facilitates
the robustness of SPST can attain 30% speed improvement and
22% power reduction in the modified booth encoder. This design
can be verified using Modelsim and Xilinx using verilog.