This document proposes designing a high speed arithmetic logic unit (ALU) using an ancient Vedic multiplication technique. It compares different types of adders and multipliers in terms of delay and design utilization to choose the best components for a 4-bit ALU. Simulation results show that implementing the ALU with a Vedic multiplier and carry lookahead adder reduces power dissipation compared to a conventional design when clock gating is used.

1. A Novel Approach to Design High Speed Arithmetic
Logic Unit Based On Ancient Vedic Multiplication
Technique
presented By
Mounica.J
14204127

2. INTRODUCTION
 Every digital domain based technology depends upon the operations
performed by ALU either partially or whole.
 The speed of ALU greatly depends upon the speed of multiplier.
 All of these operational sub-modules (adder, subtractor, multiplier and
logical gates) have been designed as the combinatorial circuit.
 And for the synchronization of these operational sub-modules, the
multiplexers which have been used to integrate these sub-modules in a
single unit have been triggered by positive edge clock.

3. problem statement
 An Arithmetic-Logic unit performs many different arithmetic and logic
operations. ALU Design consists of different kinds of Adder, Sub
tractor, Multiplexer, Inverters, NAND, NOR, XOR, etc.
 We are comparing different types of adders and multipliers in terms of
delay and design utilization summary and we are choosing the best to
design the 4 bit ALU .

4. Ripple Carry Adder

5. CARRY SAVE ADDER

6. CARRY BYPASS ADDER

7. CARRY SELECT ADDER

8. CARRY LOOK AHEAD ADDER

9. COMPARISION OF ADDERS

10. CONEVENTIONAL MULTIPLIER

11. VEDIC MULTIPLIER

12. COMPARISION OF MULTIPLIERS

13. SUBTRACTOR

14.  Determine B′s 2′s complement A+ (2’s complement of B)
 If A≥B, an end carry will result. Discard the end carry.
 If A<B, no end carry will result. To obtain the answer in a familiar form,
take the 2’s complement of the sum and place a negative sign in front.

15. BLOCK DIAGRAM OF ALU

16. simulation Results
Ouput Waveforms Of Novel ALU With Out Clock Gating

17. simulation results with clk gating

18. power dissipations comparisions
with out clk gating with clk gating