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Melp codec optimization using DSP kit
- 2. Digital Baseband Transceiver
- 11. Audio compression is a form of data compression designed to reduce the size of audio files. Speech coding is the application of data compressionof digital audio signals containing speech. Source Encoder
- 12. Mixed Excitation Linear Predictive(MELP) A MELP vocoder uses a mixed-excitation model based on a traditional LPC parametric model, but includes the additional features of mixed-excitation, periodic pulses, pulse dispersion and adaptive spectral enhancement.
- 13. MELP Characteristics Sampling rate 8000Hz Frame size 180 samples Bits/Sample 16bits Frame duration 22.5 ms Bit Rate 2.4Kbps
- 14. Project is about speech compression using MELP codec MELP is developed for extremely low bit data rate Optimization of MELP to reduce its processing time The project is designed for HF range communication THEME OF PROJECT
- 15. Features of the SigC55x MELP System include Multichannel real-time performance. Flexible audio interface. Small form-factor for MELP production systems
- 16. CPU architecture consists of the following four units. Instruction buffer unit Program flow unit Address data flow unit Data computation unit DSP TMS320C55x CPU ARCHITECTURE
- 17. Instruction buffer unit Decodes instruction Decode logic unit Maintains constant stream of tasks for computational units
- 18. Program flow unit keeps track of the execution point within the program Hardware loop control Pipeline protection
- 19. Address data flow unit Provides the address pointers for data accesses Dedicated hardware for managing the five data buses Increases the instruction level parallelism
- 21. The main ALU
- 23. Barrel shifter
- 25. Overview of the CPU Architecture
- 26. Using intrinsic Optimization level of compiler Assembly language tools Parallelism Pipelining Efficient looping Optimization Techniques
- 27. Using intrinsic ETSI functions Predefined functions by TEXAS instruments GSM.h Replacement for ETSI function
- 28. Three levels of optimization O0 O1 O2 O3 Optimization level of compiler
- 31. Simplifies expressions and statements
- 32. Expands calls to functions declared inline-O0 Optimization level
- 33. -O1 Optimization level Performs all -O0 optimizations Performs local copy/constant propagation Removes unused assignments
- 34. -O2 Optimization level Performs all -O1 optimizations Performs loop optimizations Eliminates global unused assignments Performs loop unrolling
- 35. Performs all -O2 optimizations Removes all functions that are never called Inline calls to small functions. Reorders function declarations so that the attributes of called functions are known when the caller is optimized -O3 Optimization level
- 36. Create loops that efficiently use C55x hardware loops, MAC hardware, and dual-MAC hardware. Use intrinsics to replace complicated C/C++ code Use long accesses to reference 16-bit data in memory Refining the C/C++ Code:
- 37. Parallelism Built in parallelism Example Dual Mac MAC *AR2+, *CDP+, AC0 :: MAC *AR3+, *CDP+, AC1 User defined parallel AC1 = AC1 + (*AR4+ * coef (*CDP+)) || repeat (CSR) ASSEMBLY LANGUAGE TOOLS
- 38. Efficient looping Loop unrolling Single repeat: repeat(CSR/k8/k16) Local block repeat: localrepeat{} Block repeat: blockrepeat{} Branch on auxiliary register not zero ASSEMBLY LANGUAGE TOOLS
- 39. Efficient looping Loop unrolling Loop unrolling involves structuring computations to exploit the reuse of data among different time or geometric iterations of the algorithm
- 41. Using CSR saves outer loop cycles when the single-repeat loop is an inner loop.
- 42. An optional syntax extension enables the repeat instruction to modify the CSR after copying the content of CSR to RPTC.Efficient looping
- 44. Overall lower power consumption
- 45. No repetition of wait-state and access penalties when executing loop code from external RAMEfficient looping
- 46. Block repeat Its mechanism always refetches the loop code from memory. When you nest a block-repeat loop inside another block-repeat loop, initialize the block-repeat counters (BRC0 and BRC1) in the code outside of both loops. Efficient looping
- 47. Branch on auxiliary register not zero This instruction performs a conditional branch (selected auxiliary register content not equal to 0) of the program counter (PC). Efficient looping
- 49. The second segment, referred to as the execution pipeline, decodes instructions and performs data accesses and computations. Assembly language tools
- 50. Results
- 52. Special Thanks Our special thanks to all those who cooperate and guide. Under there supervision I am able to complete this project.