Download as ODP, PPTX
![ Support for system level caches and other performance
enhancing components
Bufferable (B) bit, ARCACHE[0] and AWCACHE[0]
Cacheable (C) bit, ARCACHE[1] and AWCACHE[1]
Read Allocate (RA) bit, ARCACHE[2] and AWCACHE[2]
Write Allocate (WA) bit, ARCACHE[3] and AWCACHE[3]
Cache Support](https://image.slidesharecdn.com/amba3james0801-121106095203-phpapp01-151203125056-lva1-app6891/75/axi-protocol-22-2048.jpg)
![Cache Encoding
ARCACHE[3:0]
AWCACHE[3:0]
C : low
RA : low
WA : low](https://image.slidesharecdn.com/amba3james0801-121106095203-phpapp01-151203125056-lva1-app6891/75/axi-protocol-27-2048.jpg)
![ To support complex system design, for the interconnect and
other devices in the system to provide protection against
illegal transactions
Normal or privileged, ARPROT[0] and AWPROT[0]
Secure or non-secure, ARPROT[1] and AWPROT[1]
Data or instruction, ARPROT[2] and AWPROT[2]
Protection Unit Support
Low
Low
Low
High
High
High](https://image.slidesharecdn.com/amba3james0801-121106095203-phpapp01-151203125056-lva1-app6891/75/axi-protocol-28-2048.jpg)
Uploaded byAzad Mishra
axi protocol
The AXI protocol specification describes an advanced bus architecture with burst-based transactions using separate address/control and data phases over independent channels. It supports features like out-of-order transaction completion, exclusive access for atomic operations, cache coherency, and a low power interface. The AXI protocol is commonly used in System-on-Chip designs for high performance embedded processors and peripherals.
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axi protocol
- 1. AMBA Specification Advanced eXtensibleInterface Bus (AXI)
- 2. Architecture AXI protocolis Burst-based transactions with only start address issued. Address/Control is issued ahead of actual data transfer. 5 channels. Read Transaction Write Transaction Master Slave Read Data Channel Master Slave Write Address ChannelRead Address Channel Write Data Channel Write Respone Channel
- 3. Key Features ofAXI Protocol Separate address/control and data phases Separate Read and Write data channels Support for unaligned data transfers using byte strobes Ex:Access a 32-bit data that starts at address 0x80004002 Burst-based transactions with only start address issued Ability to issue multiple outstanding addresses ID signals Out of order transaction completion ID signals Easy addition of register stages to provide timing closure 5 channels independent, each channel transfers info. in only one direction.
- 4. Channel Definition Five independentchannels which consists of two- way handshake signals VALID, READY VALID Asserts when valid data or control information are available on the channel READY Asserts when receiver can accept the data LAST Asserts while the final data completes
- 5. Flexible Interconnect (Basic fabric,a lot of channels) Shared address and data buses Shared address buses and multiple data buses Multilayer, with multiple address and data buses
- 7. Basic Transactions AXI Master AXI Master AXI Slave AXI Slave AXI Slave AXI Slave Read Address ARREADY Readdata RREADY Write Address AWREADY Write Response BREADY Write Data WREADY To Read To Write AXI Master AXI Master
- 8. Transaction Handshake Dependencies Read Write Writedata can appear before Write address Write data appear in the same cycle as the address Read data always come after Read address Write response always come after write data
- 9. Channel Handshaking The sourcepresents the data /control_info and drives the VALID signal HIGH. The data/control_info from the source remains stable until the destination drives the READY signal HIGH, indicating that it accepts the data/control_info.
- 10. AXI Signals ARID ARADDR ARLEN ARSIZE ARBURST ARLOCK ARVALID ARREADY RID RLAST RDATA RRESP RVALID RREADY WVALID WLAST WDATA WSTRB WID WREADY BID BRESP BVALID BREADY ARPROT ARCACHE AWID AWADDR AWLEN AWSIZE AWBURST AWLOCK AWVALID AWREADY AWPROT AWCACHE ACLK ARESETn Global Signals WriteAddress Channel Read Address Channel Write Data Channel Read Data Channel Write Response Channel CSYSREQ CSYSACK CACTIVE Low Power Signals
- 11. AHB/AXI Burst Transfer A21A22 A23A11 A12 A13 A14 D21 D22 D23D11 D12 D13 D14 A31 D31 ADDRESS DATA A21A11 D21 D22 D23D11 D12 D13 D14 A31 D31 ADDRESS DATA AHB AXI A21 A31
- 12. AHB/AXI Burst Transfer A21A22 A23A11 A12 A13 A14 A31ADDRESS DATA A21A11 D21 D22 D23 D11 D12 D13 D14 A31 D31 ADDRESS DATA D11 D12 D13 D14 AHB AXI D21 Out of Order Completion D21 D22 D23 D11 D12 D13 D14D31 DATA Data Interleaving A32 D32 Wait Cycle Wait Cycle
- 13. AXI Ordering Model ARIDRIDWID BIDAWID Write Address Channel Read Address Channel Write Data Channel Read Data Channel Write Response Channel AXI Master1 AXI Master2 AXI Interconnect AXI Slave1 AXI Slave2 A B C D 1 2 1 3 A D 1 3 2. Write interleaving B C 2 1 1. Out of order completion Write interleaving depth = 1 X Write interleaving depth > 1 OK
- 14. AXI Transfer Behavior D14D13D11D12D31 A11 D21 D22 D23 D24 D14B33 A31 A21 Read Address Channel Write Data Channel Read Data Channel Write Response Channel Write Address Channel A41 D32 D33 D41 Out of Order Completion • Write data channel • Read data channel Data Interleaving • Write data channel
- 15. Register Slices *trade-off betweencycles of latency and maximum frequency of operation*Matching channel latency for max Freq *Apply to across any channel All channels are unidirectional and independent the order in which AXI channel Register slices can be inserted across any channel No change in functionality Increase in latency slices can be inserted at any point in the interconnect isolate paths to non-performance-critical devices but retain low-latency connections to performance-critical devices
- 16. Burst Operation …………. Burst length 1beat 2 beats 8 beats 16 beats Undefined length 4 beats SIZE Word halfword …… Burst Transfer ………
- 17. Burst Transfer Type Burst beat4 Size 1 word 0 1 2 3 4 x 1word=4 word 4 5 Wrap Increment 3 102 3 542 Fixed 0 FIFO
- 18. Burst Control signals Burstlength Burst Size Burst Type Every transaction must have the number of transfers No component can terminate a burst early to reduce the number of data transfers.
- 19. Write Strobes WSTRB :Write strobes. This signal indicates which byte lanes to update in memory. There is one strobe for each eight bits of the write data bus. 7 63 56 6 55 48 5 47 40 4 39 32 3 31 24 2 23 16 1 15 8 0 7 0 64-bit write data bus WDATA : 8 – 1024 bits wide WSTRB : 1 – 128 bits wide WSTRB 1 0 1 0 0 1 0 0
- 20. Aligned Transfer 7 63 56 6 5548 5 47 40 4 39 32 3 31 24 2 23 16 1 15 8 0 7 0 Address: 0x00 Transfer size: 32 bits Burst type: incrementing Burst length: 4 transfers 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0F E D C B A 9 8 64-bit write data bus WSTRB 0 0 0 0 0 1 1 0 WSTRB 0 1 0 1 0 0 0 0 For wrapping burst type, all transfers are aligned transfers
- 21. Unaligned Transfer 7 63 56 6 5548 5 47 40 4 39 32 3 31 24 2 23 16 1 15 8 0 7 0 Address: 0x07 Transfer size: 32 bits Burst type: incrementing Burst length: 4 transfers 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 F E D C B A 9 8 F E D C B A 9 8 WSTRB 1 0 0 0 0 0 0 0 WSTRB 0 0 0 0 1 1 1 0 64-bit write data bus For incrementing burst type, fist transfer can be unaligned transfers, but the rest transfers are aligned transfers
- 22. Support forsystem level caches and other performance enhancing components Bufferable (B) bit, ARCACHE[0] and AWCACHE[0] Cacheable (C) bit, ARCACHE[1] and AWCACHE[1] Read Allocate (RA) bit, ARCACHE[2] and AWCACHE[2] Write Allocate (WA) bit, ARCACHE[3] and AWCACHE[3] Cache Support
- 23. The interconnector any component can delay the transaction for an arbitrary number of cycles, usually only relevant to writes Bufferable Bit AXI Master1 AXI Master2 AXI Interconnect AXI Slave1 A1 1 A2 1 A3 1 B1 2 B2 2 B3 2 A1 1 A2 1 A3 1 B1 2 B2 2 B3 2 B1 2 B2 2 B3 2 A1 1 A2 1 A3 1 B1 2 B2 2 B3 2 Write interleaving depth = 2
- 24. IF atransaction is bufferable It is acceptable for a bridge or system level cache to provide write response If non-bufferable Final destination to provide response Bufferable Bit (Conti.) AXI Master1 AXI Master2 AXI Interconnect AXI Slave1 Bufferable Non-bufferable
- 25. Cacheable Bit Write : a number of different writes can be merged together Read : a location can be pre-fetched or can be fetched just once for multiple read transactions Read Allocate Bit If the transfer is a read and it misses in the cache then it should be allocated Write Allocate Bit If the transfer is a write and it misses in the cache then it should be allocated Cache Support
- 26. Cacheable Write –Sparse Strobes ARM11-MPCore processor and L220 Level 2 cache controller use sparse strobes. This is due to the fact that they use a merging write buffer. If the application writes several bytes at address 0x0, 0x3, 0x4, the write buffer will be drained using a 64-bit transfer, and strobes will be 0b00011001 and the AXI slave must only update the bytes that are enabled. 7 63 56 6 55 48 5 47 40 4 39 32 3 31 24 2 23 16 1 15 8 0 7 0 64-bit write data bus WSTRB 0 0 0 1 1 0 0 1 Cacheable Bit Write : a number of different writes can be merged together
- 27. Cache Encoding ARCACHE[3:0] AWCACHE[3:0] C :low RA : low WA : low
- 28. To supportcomplex system design, for the interconnect and other devices in the system to provide protection against illegal transactions Normal or privileged, ARPROT[0] and AWPROT[0] Secure or non-secure, ARPROT[1] and AWPROT[1] Data or instruction, ARPROT[2] and AWPROT[2] Protection Unit Support Low Low Low High High High
- 29. This isused by some masters to indicate their processing mode. A privileged processing mode typically has a greater lever of access within a system Normal / Privileged AXI Master1 CPU AXI Interconnect AXI Slave1 AXI Slave2 AXI Master2 Normal access Privileged access Normal access
- 30. This isused in systems where a greater degree of differentiation between processing modes is required Secure / Non-secure AXI Master1 AXI Interconnect AXI Slave1 (Secure) AXI Slave2 (Non-secure) AXI Slave3 (Non-secure) Non-secure SLVERR response OKAY response Non-secure slave disappears from the memory map during secure accesses Secure DECERR response
- 31. This bitgives an indication if the transaction is an instruction or a data access Data / Instruction When a transaction contains a mix of instruction and data items It’s recommended that, by default, an access is marked as a data access unless specifically known to be an instruction access Instruction Data Data
- 32. Access / ResponseSignals Slave-generated errors Address decode errors Access Signals Response Signals
- 33. Exclusive Access 0 12 3 4 5 Cycle 1 0 1 2 3 4 5 Cycle 2 0 1 2 3 4 5 Cycle 3 Master1 Exclusive Read Master2 Write Master1 Exclusive Write Exclusive Write success Response : EXOKAY Exclusive Write fail Response : OKAY Exclusive Read success Response : EXOKAY Exclusive Read fail Response : OKAY Semaphore type without locking the bus access
- 34. Low-power interface signals SignalSource Description CSYSREQ Clock controller System low-power request. This signal is a request from the system clock controller for the peripheral to enter a low-power state. CSYSACK Peripheral device Low-power request acknowledgement. This signal is the acknowledgement from a peripheral of a system low-power request. CACTIVE Peripheral device Clock active. This signal indicates that the peripheral requires its clock signal: 1 = peripheral clock required 0 = peripheral clock not required.
- 35. CSYSREQ and CSYSACKhandshake CSYSREQ To request that the peripheral enter a low-power state, the system clock controller drives the CSYSREQ signal LOW. During normal operation, CSYSREQ is HIGH. CSYSACK The peripheral uses the CSYSACK signal to acknowledge both the low- power state request and the exit from the low-power state.
- 36. Acceptance/ Denial oflow-power request Acceptance Denial
- 37. Independently acknowledgedaddress and data channels Out-of-order completion of bursts Write data interleaving Exclusive access (atomic transaction) Access security support System level cache support Unaligned address & byte strobe Static burst, which allows bursts to FIFO memory Low power mode Advantages of AXI Protocol
Editor's Notes
- #8 The AXI protocol is burst-based. Every transaction has address and control information on the address channel that describes the nature of the data to be transferred. The data is transferred between the master and slave using a write channel to the slave or a read channel to the master. In write transactions, in which all the data flows from the master to the slave, the AXI has an additional write response channel to allow the slave to signal to the master the completion of the write transaction. Address channel The address channel is used in every transaction and carries all the required address and control information for that transaction. AXI supports the following transactions: Variable-length bursts, from 1 to 16 data transfers per burst Bursts with a transfer size of eight bits up to the maximum data bus width Wrapping, incrementing, and non-incrementing bursts Atomic operations, using exclusive and locked access System-level caching and buffering control Secure and privileged access Read channel The read channel conveys both the read data and any read response information from the slave back to the master. The read channel includes: The data bus, which can 8, 16, 32, 64, 128, 256 or 1024 bits wide A read response indicating the completion status of the read transaction Write channel The write channel conveys the write data from the master to the slave and includes: The data bus, which can 8, 16, 32, 64, 128, 256 or 1024 bits wide One byte lane strobe for each eight data bits, indicating which bytes of the data bus are valid Write channel data is always treated as buffered, so that the master can perform write transactions without slave acknowledgement of previous write transactions. Write response channel The write response channel provides a way for the slave to respond to write transactions.
- #9 It is important that during a write transaction, a master must not wait for AWREADY to be asserted before driving WVALID. This could cause a deadlock condition if the slave is conversely waiting for WVALID before asserting AWREADY.
- #15 The ordering model AXI enables out-of-order transaction completion and the issuing of multiple outstanding addresses. These features enable the implementation of high-performance interconnect, maximising data throughput and system efficiency. The ID signals, AID, WID, RID and BID, support out-of-order transactions by enabling each port to act as multiple ordered ports. All transactions with a give ID must be ordered, but there is no restriction on the ordering of transactions with different IDs. Note: There is no requirement for slaves and masters to use these advanced features. Simple masters and slaves can process one transaction at a time in the order they are issued Write data interleaving Write data interleaving enables a slave interface to accept interleaved write data with different AID values. The slave declares a write data interleaving depth that indicates if the interface can accept interleaved write data from sources with different AID values. The write data interleaving depth is statically configured. By default, the write data interleaving depth of any interface is one. Write data interleaving can prevent stalling when the interconnect combines multiple streams of write data destined for the same slave. The interconnect might combine one write data stream from a slow source and another from a fast source. By interleaving the two write data streams, the interconnect can improve system performance. Efficient DMA support The first two bursts that are illustrated in this example could have been generated by a single master implementing a DMA function. Note that the read and write transfers are packed together very efficiently with only a single clock cycle delay (although even that is not strictly required). Effectively, the AXI protocol has enables the implementation of a ‘fly-by’ DMA with a single master interface
- #16 Register slices Each AXI channel transfers information in only one direction, and there is no requirement for a fixed relationship between the various channels. This is important because it enables the insertion of a register stage in any channel, at the cost of an additional cycle of latency. This makes possible a trade-off between cycles of latency and maximum frequency of operation. It is also possible to use register slices at almost any point within a given interconnect. It can be advantageous to use direct, fast connection between a processor and high-performance memory, but to use simple register slices to isolate a longer path to less performance-critical peripherals. Multiple frequency domains The unidirectional structure of the AXI channels, enabling the efficient use of register slices, also provides an efficient protocol for mapping between different clock domains. The maximum data rate is limited by the lowest frequency in the channel; however, once the retiming of the data has been achieved at the inevitable cost of some latency, the bandwidth of the remainder of the burst is maintained. Multiple clock domains within a design contribute to the reduction in system power. With Intelligent Energy Management, the clock frequencies can be varied, dynamically to optimise the system for power. The support of efficient movement of data between asynchronously related clock domains by AXI is essential to the support of dynamic energy management. Register slices do not have to be placed evenly across all four of the AXI channels; they only need to be added to the critical paths. With no fixed pipeline requirements between the channels, the different latencies in each channel is handled by the AXI protocol. Critical paths can arise through the routing of the channels themselves and also through the characteristics of the AXI interface of the master or slave.
- #18 In a fixed burst, the address remains the same for every transfer in the burst. This burst type is for repeated accesses to the same location such as when loading or emptying a peripheral FIFO. Two restrictions apply to wrapping bursts: • the start address must be aligned to the size of the transfer • the length of the burst must be 2, 4, 8, or 16.
- #20 Byte Invariance To access mixed-endian data structures that reside in the same memory space, the AXI uses a byte-invariant endian scheme. Byte-invariant endianess means that the byte transfer to a given address passes the eight bits of data on the same data bus wires to the same address location. Components that have only one transfer width must have their byte lanes connected to the appropriate byte lanes of the data bus. Components that support multiple transfer widths might require a more complex interface to convert an interface that is not naturally byte-invariant. Most little-endian components can connect directly to a byte-invariant interface. Components that support only big-endian transfers require a conversion function for the byte-invariant operation. Why? To achieve the full benefits of re-use, there should be as few dependencies as possible affecting the insertion of an AXI component into a system. Byte-invariant endianess ensures that the slave or master can select an endianess with out knowledge of that selected by other components in the system.
- #21 Byte Invariance To access mixed-endian data structures that reside in the same memory space, the AXI uses a byte-invariant endian scheme. Byte-invariant endianess means that the byte transfer to a given address passes the eight bits of data on the same data bus wires to the same address location. Components that have only one transfer width must have their byte lanes connected to the appropriate byte lanes of the data bus. Components that support multiple transfer widths might require a more complex interface to convert an interface that is not naturally byte-invariant. Most little-endian components can connect directly to a byte-invariant interface. Components that support only big-endian transfers require a conversion function for the byte-invariant operation. Why? To achieve the full benefits of re-use, there should be as few dependencies as possible affecting the insertion of an AXI component into a system. Byte-invariant endianess ensures that the slave or master can select an endianess with out knowledge of that selected by other components in the system.
- #22 Unaligned transfers The AXI protocol uses burst-based addressing, which means that each transaction consists of a number of data transfers. Typically, each data transfer is aligned to the size of the transfer. For example, a 32-bit wide transfer is usually aligned to four-byte boundaries. However, there are times when it is desirable to begin a burst at an unaligned address. For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be accessed do not align with the natural data width boundary. For example, a 64-bit (eight-byte) data packet that starts at a byte address of 0x0003 is not alignes to a 64-bit boundary. The AXI protocol enables a master to use the low-order address lines to signal an unaligned start address for the burst. The information on the low-order address lines must be consistent with the information contained on the byte-lane strobes The master can also simply provide an aligned address and, in a write transaction, rely on the byte lane strobes to provide the information about which byte lanes the data is using.
- #27 A start address of 0x1 means that you can use any of the byte lanes WSTRB[7:1] on the 64 bit data bus (assuming AWSIZE indicated a 64 bit transfer), but not WSTRB[0].Obviously if AWSIZE indicated a 32 bit transfer, even with a bus width of 64 bits we could only use WSTRB[3:1] for this transfer to AWADDR=0x1. Byte Invariance To access mixed-endian data structures that reside in the same memory space, the AXI uses a byte-invariant endian scheme. Byte-invariant endianess means that the byte transfer to a given address passes the eight bits of data on the same data bus wires to the same address location. Components that have only one transfer width must have their byte lanes connected to the appropriate byte lanes of the data bus. Components that support multiple transfer widths might require a more complex interface to convert an interface that is not naturally byte-invariant. Most little-endian components can connect directly to a byte-invariant interface. Components that support only big-endian transfers require a conversion function for the byte-invariant operation. Why? To achieve the full benefits of re-use, there should be as few dependencies as possible affecting the insertion of an AXI component into a system. Byte-invariant endianess ensures that the slave or master can select an endianess with out knowledge of that selected by other components in the system.
- #33 The exclusive access mechanism enables the implementation of semaphore type operations without requiring the bus to remain locked to a particular master for the duration of the operation. The advantage of exclusive access is that semaphore type operations do not impact either the critical bus access latency or the maximum achievable bandwidth. The slave must have additional logic to support exclusive access. The AXI protocol provides a fail-safe mechanism to indicate when a master attempts an exclusive access to a slave that does not support it. A master might not complete the write portion of an exclusive operation. The exclusive access monitoring hardware must monitor only one address per transaction ID. Therefore, if a master does not complete the write portion of an exclusive operation, a subsequent exclusive read changes the address that is being monitored for exclusivity.
- #34 If the master attempts an exclusive read from a slave that does not support exclusive accesses, the slave returns the OKAY response instead of the EXOKAY response. The master can treat this as an error condition indicating that the exclusive access is not supported. It is recommended that the master not perform the write portion of this exclusive operation. At some time after the exclusive read, the master tries an exclusive write to the same location. If the location has not changed since the exclusive read, the exclusive write operation succeeds. The slave returns the EXOKAY response, and the exclusive write updates the memory location. A master might not complete the write portion of an exclusive operation. If this happens, the slave continues to monitor the address for exclusivity until another exclusive read initiates a new exclusive access.