A fast acquisition all-digital delay-locked loop using a starting-bit prediction algorithm for the successive-approximation register

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A Fast-Acquisition All-Digital Delay-Locked Loop
Using a Starting-Bit Prediction Algorithm for the
Successive-Approximation Register
Abstract:
This brief presents a fast-acquisition 11-bit all-digital delay-locked loop (ADDLL) using a novel
starting-bit prediction algorithm for the successive-approximation register (SBP-SAR). It can
effectively eliminate the harmonic lock and the false lock. The achievable acquisition time is
within 17.5–23.5 or 17.5–32.5 clock cycles when the ADDLL works at the low or high clock
rate, respectively. The digital-controlled delay line and the SBP-SAR of the ADDLL chip are
synthesized using Taiwan Semiconductor Manufacturing Company’s (TSMC’s) 0.18-µm CMOS
cell library. The proposed ADDLL can operate at a clock frequency from 60 MHz to 1.1 GHz.
The proposed architecture of this paper analysis the logic size, area and power consumption
using Xilinx 14.2.
Enhancement of the project:
Existing System:
To widen the operating frequency range of the DLLs, various architectures of DLLs were
reported. Looking into the acquisition time of the DLLs, we conclude that the successive
approximation register (SAR)-based realizations, the time-to-digital converter (TDC)-based
realizations, and the hybrid TDC-feedback DLL have sufficiently fast DLL response time
compared with the multiphase-clock DLLs. In the SAR-based DLLs, the required acquisition
time ranges from tens to hundreds of clock cycles, depending on the number of SAR bits they
have. In the TDC-based DLLs, the acquisition time is within 15 clock cycles. Furthermore, the
hybrid realization advanced the acquisition time to only three clock cycles.

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Although the TDC-based DLLs and the hybrid DLL possess short acquisition time, most of their
circuits have to be custombuilt; i.e., the design efforts of their circuits are high. On the other
hand, the force/release SAR-based DLLs were cell-based all-digital DLLs (ADDLLs). El-Shafie
and Habib only showed the simulation result, whereas we verified our method by measuring the
ADDLL chip. The acquisition time of the ADDLL requires 33 clock cycles for an 11-bit SAR
and the jitter performance was comparable with its full-custom counterparts. Since Yao et al. [1]
successfully demonstrated the possibility of using a cell-based design to realize a SAR ADDLL
running up to 1.2-GHz clock, it is worth developing a more powerful algorithm to shorten the
average acquisition time of the SAR ADDLL. Simulation results verified that a short average
acquisition time could be obtained using a starting-bit predicting algorithm of SAR (SBP-SAR)
for a wide-operating-range ADDLL. This brief further refines the SBP-SAR algorithm and
realizes the SBP-SAR ADDLL using TSMC’s 0.18-μm CMOS cell library. The ADDLL
acquisition time can be confined from 17.5 to 32.5 clock cycles.
Disadvantages:
 The harmonic lock and the false lock are occurs
Proposed System:
DCDL Structure
The DCDL in this brief is similar to that, except that we modify the lattice delay unit (LDU) that
is shown in Fig. 1. Unlike the LDU proposed, every NAND block of the LDU in this brief is
actually composed of two parallel small NAND gates with their input connections interchanged.
This modification further equalizes the loads of all nodes of the LDUs in the DCDL. Compared
with our previous work, the DLL jitter performance of this brief is improved.

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Fig. 1. Modified LDU.
Intrinsic Delay
The intrinsic delay Tint is the shortest delay of the DCDL. It is equal to the shortest delay of the
fine-tuning delay unit plus the delay caused by cascading two NAND gates and a buffer. We
duplicate this part of the DCDL as a subblock called τint for delaying CLKin to get CLKint. Fig. 2
shows the schematic of τint.
Fig. 2. Schematic of the subblock τint.
Proposed ADDLL
Fig. 3 shows the flowchart of the proposed ADDLL. In the beginning, k = 0 and the system starts
the SBP operation. The ADDLL judges whether the DCDL delay is less than Tc_int + 4Tclk. If
CLKout does not show up when Ncounter ≤ 1, then k will be increased by 1. This process repeats
until the DCDL delay is less than Tc_int + 4Tclk. Next, the starting bit is determined by the SBP-
SAR algorithm presented in Section II. Next, a SAR search takes over the phase acquisition.
Once the SAR procedure is completed, the ADDLL operates in a closed-loop tracking mode.

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Fig. 3. Flowchart of the proposed ADDLL.
Fig. 4 shows the block diagram of the proposed ADDLL. It consists of a 11-bit DCDL, a phase
detector, a divide-by-2-or-3 frequency divider (FD), and an SBP-SAR controller. The dotted line
in Fig. 4 encloses the SBP-SAR controller. It consists of a 11-bit SAR, a starting-bit generator
(SBG), a timing controller, a delay subblock τint, and some supporting circuits. Notably, if
SELSAR = 0, D[10:0] = Ddb[10:0]. Otherwise, D[10:0] = DSAR[10:0]. Ddb is the initial code
of the DCDL for each SBP operating cycle. The values of Ncounter, HalfDM, and Cycle1
determine the SAR starting bit for the corresponding SBP cycle.

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Fig. 4. Block diagram of the proposed ADDLL.
Fig. 5 shows the schematic of the FD. According to the simulation results, when the clock
frequency is >550 MHz, the divisor should be 3 for sufficient settling time of the SAR. In this
case, we let SELdiv23 be 1. Otherwise, the divisor is 2 and SELdiv23 is 0. The signal ENSAR is
used to enable the FD. Notably, the first cycle of the SAR operation of our ADDLL extends to 3
cycles of CLKin, no matter what divisor value is. The D flip-flop DFFdum in the FD can fulfill this
requirement.
Fig. 5. Schematic of the FD.
Advantages:
 eliminate the harmonic lock and the false lock
Software implementation:

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 Modelsim
 Xilinx ISE

A fast acquisition all-digital delay-locked loop using a starting-bit prediction algorithm for the successive-approximation register

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