Bumpless control for reduced thd in power factor correction circuits

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Bumpless Control for Reduced THD in
Power Factor Correction Circuits
Introduction:
Power factor correction circuits should conserve energy and
have a high power factor, as a matter of course. In the commercial
marketplace, certifying a product with an energy-saving program
differentiates that product and offers a competitive advantage. Two
examples of energy-savings certifications are the 80 PLUS program
that requires 90% efficiency at a 0.2 per unit (p.u.) load, and the
ENERGY STAR version 5.0 standard that requires a power factor of
at least 0.65 at a 0.1 p.u. load. Researchers have devised control
strategies that may be used to meet these requirements, and typically
use multiple controllers. The salient features of these approaches is to
partition the PFC operation into discrete regions based on load, CCM-
DCM operation, or other criteria; synthesize a controller for each
region; and switch between the controllers based on the operating
region. Switching between controllers will result in a discontinuous
signal that can degrade performance,
Existing system:
The sensed signal which contains the diode current information
is positive. Therefore the proposed sensing circuit has a simple
structure because it is freed of an external amplifier and negative bias
voltage. The effect of the sensing resistor on the output voltage is
negligible because the Digital Control of a Power Factor Correction
Boost rectifier with the proposed diode sensing scheme. Voltage

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across the R sense is very small with respect to the output voltage
ripple.
Drawbacks:
 Degrade performance.
 Less power factor.
Proposed system:
Bumpless controllers will be introduced, the DCM-CCM models
for the inner current loop will be used to illustrate the significant
differences between the plant in the two operating modes, two
bumpless controllers will be synthesized for the two operating modes,
the bumpless controllers will be tested in simulation, and the
bumpless controllers will be implemented in hardware using a 750
watt semi-bridgeless PFC. The bumpless controllers will be designed
for a semi bridgeless topology. The semi-bridgeless PFC topology
was chosen for its high efficiency. The PFC has two loops, a current

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loop and a voltage loop. The plant for the current loop may be derived
using state space averaging, or Vorperian’s model, for the PWM
switch.
Advantages:
 High power factor.
 Good performance operation.
 Low ripple content.
Applications:
 Energy storage applications.
 Renewable energy applications.

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Block diagram:
Input AC
Supply
Semi bridgeless
PFC circuit
Output C
filter
Load
Isolation Circuit12V DC
5V DC
Buffer Circuit
Micro Controller
Circuit

Bumpless control for reduced thd in power factor correction circuits

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Bumpless control for reduced thd in power factor correction circuits