This paper presents a dual flip flop synchronizer circuit to address clock domain crossing issues. The synchronizer is designed using True Single Phase Clock (TSPC) logic and implemented using Silicon On Insulator (SOI) technology. Simulation results show the TSPC synchronizer on SOI improves rise time by 46.15%, fall time by 28.57%, reduces power dissipation by 24.23%, and reduces power delay product by 59.20% compared to an equivalent bulk CMOS design. The TSPC synchronizer on SOI also occupies less chip area than alternative synchronizer designs.