This document proposes a new Network-on-Chip (NoC) router design called Minimally-Buffered Deflection (MinBD) Router that combines deflection routing with a small buffer. The MinBD router buffers incoming packets that would otherwise be deflected, reducing the deflection rate. It also uses a prediction buffer and status signals to predict network congestion and control packet injection. The design is implemented on an FPGA with low resource utilization, demonstrating its efficiency.

1. http://www.iaeme.com/IJECET/index.asp 12 editor@iaeme.com
International Journal of Electronics and Communication Engineering & Technology
(IJECET)
Volume 6, Issue 8, Aug 2015, pp. 12-18, Article ID: IJECET_06_08_003
Available online at
http://www.iaeme.com/IJECETissues.asp?JTypeIJECET&VType=6&IType=8
ISSN Print: 0976-6464 and ISSN Online: 0976-6472
© IAEME Publication
MINIMALLY BUFFERED DEFLECTION
ROUTER INTERCONNECT WITH
PREDICTION, IN NETWORK-ON-CHIP
WITH FPGA IMPLEMENTATION
Roshni Sadashiv Kolpe
Dept. of E&TC
Dr. D. Y. Patil School of Engineering,
Ambi – Pune, India
Prof. S. R. Gulhane
Dept. of E&TC
Dr. D. Y. Patil College of Engineering,
Ambi – Pune, India
ABSTRACT
A conventional Network-on-Chip (NoC) router uses input buffers to store
incoming packets which improves performance, but also it consume power
significantly. While NoC with bufferless router design has shown reduction in
area and power, and also offers similar performance to conventional buffered
NOC designs for many workloads, compared to conventional buffered routers
at high network load. This degradation is a significant problem for
widespread adoption of bufferless NoCs.
In this work, we propose a new NOC router design called Minimally-
Buffered Deflection (MinBD) Router combines deflection routing with a small
buffer, which place some network traffic in this small buffer which would have
been deflected otherwise. And using the prediction flow control technique for
the side buffer. The side buffer would generate status signals, which are sent
out to neighboring router switches, would help control the congestion in the
network, by predicting the routing flow.
Key words: Network-on-Chip, Minimally-Buffered Deflection (MinBD)
Router, Prediction Buffer
Cite this Article: Roshni Sadashiv Kolpe and Prof. S. R. Gulhane Minimally
Buffered Deflection Router Interconnect with Prediction, In Network-On-Chip
with FPGA Implementation. International Journal of Electronics and
Communication Engineering & Technology, 6(8), 2015, pp. 12-18.
http://www.iaeme.com/IJECET/issues.asp?JTypeIJECET&VType=6&IType=8

2. Minimally Buffered Deflection Router Interconnect with Prediction, In Network-On-Chip
with FPGA Implementation
http://www.iaeme.com/IJECET/index.asp 13 editor@iaeme.com
1. INTRODUCTION
A network-on-chip is a component of current and future multi core and many core
CMPs (Chip Multiprocessors) [10], and its design can be critical for system
performance. As core counts rises, NoCs with designs such as 2Dmesh are expected
to become more common to provide adequate performance scaling. Unfortunately,
packet-switched NoCs are consuming significant power. In the Intel Terascale 80-
core chip, 28% of chip power is consumed by the NoC [7]; for MIT RAW, 36% [35];
for the Intel 48-core SCC, 10% [3]. NoC energy efficiency is thus an important design
goal [4], [5].
Bufferless yields simpler and more energy-efficient NoC designs: e.g., CHIPPER
[12] reduces average network power by 54.9% in a 64-node system compared to a
conventional buffered router. But, at high network traffic, deflection routing reduces
performance and efficiency. This is because deflections occur more frequently when
many flits contend in the network. Relative to a buffered network, a bufferless
network with a high deflection rate wastes energy, and suffers worse congestion,
because of these unproductive network hops. In contrast, a buffered router is able to
hold flits (or packets) in its input buffers until the required output port is available,
incurring no unnecessary hops. Thus, a buffered network can sustain higher
performance at peak load. Our goal is to obtain the energy efficiency of the bufferless
approach with the high performance of the buffered approach. One prior work, AFC
(Adaptive Flow Control), proposes a hybrid design that switches each router between
a conventional input-buffered mode and a bufferless deflection mode [8]. However,
switching to a conventional buffered design at high load incurs the energy penalty for
buffering every flit: in other words, the efficiency gain over the baseline input-
buffered router disappears once load rises past a threshold. AFC also requires the
control logic for both forms of routing to be present at each network node, and
requires power gating to turn off the input buffers and associated logic at low load.
Ideally, a router would contain only a small amount of buffering, and would use this
buffer space only for those flits that actually require it, rather than all flits that arrive.
We propose minimally-buffered deflection routing (MinBD) as a new NoC router
design that combines both bufferless and buffered paradigms in a more fine and
efficient way. MinBD uses deflection routing, but also incorporates a small buffer and
prediction buffer. The router always operates in a minimally-buffered deflection
mode, and can buffer or deflect any given flit. When a flit first arrives, it does not
enter a buffer, but travels straight to the routing logic. If two flits contend for the same
output, the routing logic chooses one to deflect, as in a bufferless router. However, the
router can choose to buffer up to one deflected flit per cycle rather than deflecting it.
This fine-grained buffering-deflection hybrid approach significantly reduces
deflection rate, and improves performance, as we show. It also incurs only a fraction
of the energy cost of a conventional buffered router. Using prediction buffer and
status signals, we can calculate or predict the total resource availability of the
network. This information helps to avoid excess injection of packets in the network
thus, reduces congestion and deflection rate. MinBD provides higher energy
efficiency while also providing high performance, compared to a comprehensive set
of baseline router designs.

3. Roshni Sadashiv Kolpe and Prof. S. R. Gulhane
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Figure 1 Typical Router
2. MINBD: MINIMALLY-BUFFERED DEFLECTION ROUTER
The MinBD (minimally-buffered deflection) router is a new router design that
combines bufferless deflection routing with a small buffer, which we call the “side
buffer.” We start by outlining the key principles we follow to reduce deflection
caused inefficiency by using buffering:
1. When a flit would be deflected by a router, it is often better to buffer the flit and
arbitrate again in a later cycle. Some buffering can avoid many deflections.
2. However, buffering every flit leads to unnecessary power overhead and buffer
requirements, because many flits will be routed productively on the first try. The
router should buffer a flit only if necessary.
3. Finally, when a flit arrives at its destination, it should be removed from the
network (ejected) quickly, so that it does not continue to contend with other flits.
3. PREDICTION BASED FLOW CONTROL IN MINBD
Collecting congestion data at the routers and delivering this data to the traffic sources
for flow control may cause large communication overhead; so it is not a scalable
approach. Moreover unpredictable delays in the feedback loop of flow control
algorithms prevent the timely transmission of the congestion information and control
signals. To mitigate this problem, we propose a prediction-based control which relies
on the traffic source and router model. These models enable us to predict the
availability of any router at a future time step.
We would further improve upon the MinBD design, using the prediction flow
control technique for the side buffer. The side buffer would generate status signals,
which are sent out to neighbouring router switches.

4. Minimally Buffered Deflection Router Interconnect with Prediction, In Network-On-Chip
with FPGA Implementation
http://www.iaeme.com/IJECET/index.asp 15 editor@iaeme.com
We assume that there is an external control mechanism, which accumulates
such status signals from neighbouring router switches, which helps in its decision
making process of routing appropriate flit/s to the appropriate router switch. This
mechanism would help control the congestion in the network, by predicting the
routing flow.
4. PACKET FORMAT IN PROPOSED SYSTEM
The devices communicate using a simple packet-based protocol. The packets are of
fixed size, and include a 3-bit header and 16-bits of packet data for a total of 22 bits.
The header is comprised of a 3-bit source identifier and 3-bit destination identifier.
TABLE I PACKET DATA FORMAT
5. IP CORE FPGA DESIGN IMPLEMENTATION
METHODOLOGY
Goal: To develop a synthesizable IP core in HDL, for the input block (receiving
packets) of the routing logic.
A.HDL:
 Design Description using Verilog-HDL
B. Verification Scheme:
 Functional Simulation using Xilinx ISE Simulator
 Test bench for top level design using Verilog-HDL
 Stimulus for testing IP Core
 Simulation results / Timing diagram Analysis
C. FPGA Implementation
 Design to be synthesized using Xilinx ISE Software.
 Generate a design bit stream for FPGA device.
6. SIMULATION
A. Simulation Environment
We have simulated input buffer concept using prediction in Verilog. The target FPGA
device is the Xilinx Spartan3 xc3s400-5fg456 with 100 slices with related logic. The
Xilinx ISE 14.2 is used to synthesize the code.
B. Simulation Result
Each node has an input port consists of FIFO buffers, one for each input link, and a
mechanism to connect inputs to outputs. Each of these buffers can store 32 flits
belonging to the same message. The message is of 22bits, 16 bits of data, 3 bits of
destination address & 3 bits of source address.
Bits 21 6 5 3 2 0
Field Packet Data Src Dest

5. Roshni Sadashiv Kolpe and Prof. S. R. Gulhane
http://www.iaeme.com/IJECET/index.asp 16 editor@iaeme.com
For, input packet = 0fff07 then simulation results are as follows
Calculated packet data= 3ffc, Destination address= 7

6. Minimally Buffered Deflection Router Interconnect with Prediction, In Network-On-Chip
with FPGA Implementation
http://www.iaeme.com/IJECET/index.asp 17 editor@iaeme.com
C. Summary
TABLE II Device Utilization Summary
Logic Utilization
Device Utilization Summary
Used Available Utilization
Number of Sliced Flip Flops 190
7,168 2%
Number of 4 input LUT’s 100 7,168 1%
Number of occupied slice 100 3,584 2%
Number of slices containing only related
logic
100 100 100%
Number of slices containing unrelated
logic
0 100 0%
Total number of 4input LUTs 100 7,168 1%
Number of bounded IOBs 202 264 76%
FPGA IMPLEMENTATION
 FPGA implementation of Input buffer of Router has been performed on Xilinx
Spartan-3E FPGA XC3S250. The Device Utilization Summary of Input Buffer of the
Router is given in Table II. The design of the Input Buffer of router has been
implemented on XC3S250-4pq208. The device utilization summary indicates that
202 IOBs out of 264IOBs have been used.
 The 8-bits version of the input block was used for implementation of interconnect on
a Spartan-3 FPGA as the 22-bit version could not be accommodated on this FPGA.
The input packets are generated using DIP switches.

7. Roshni Sadashiv Kolpe and Prof. S. R. Gulhane
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