Static complementary CMOS logic circuits have the following properties: 1) They are robust and have high noise immunity since their output is connected to either VDD or GND through a low-resistance path except during switching. 2) They have low power consumption and high speed. 3) They use both NMOS and PMOS transistors - the NMOS transistors (M1 and M2) pull the output low, while the PMOS transistors (M3 and M4) pull the output high. The load is the total parasitic capacitance (Cload).

1. Combinational MOS Logic Circuit
IV-1
ENEE 359a Digital VLSI Design Transistor Sizing & Logical Effort by Prof. Bruce Jacob University
of Maryland ECE Dept.

2. Topics
• CMOS Logic Circuit

3. Static Complementary CMOS
• Definition:
Static CMOS circuit is a CMOS circuit that its
output is connected to either VDD or GND via a
low-resistance path, except during switching.
• Advantages:
i. Robust (low sensitivity to noise – high noise
margin)
ii. Good performance- low power consumption
- high speed

9. Static Complementary CMOS

10. Static Complementary CMOS

11. Static Complementary CMOS

12. M1 and M2 NMOS
M3 – Vdd and M4

13. Static Complementary CMOS

14. Cload= sum of all parasitic capacitances

15. Static Complementary CMOS

17. Design Steps :
1. Start with specifying a VOL (i.e. maximum VOL ) value.
2. Use the given value of VOL to first find (W/L)load and (W/L)driver for an equivalent
inverter.
3. Identify all worst case scenario in the ckt.
4. Find driver and load transistor sizes i.e. (W/L)load and (W/L)driver so that the complex
logic gate achieves the specified VOL even in worst case.

18. Static Complementary CMOS

19. Static Complementary CMOS

20. Static Complementary CMOS

21. Static Complementary CMOS

24. Static Complementary CMOS

25. Source
Drain

26. Properties Complementary CMOS Logic Gates