This document discusses sources of variation in integrated circuit manufacturing and design. It covers variations that can occur during the front-end-of-line and back-end-of-line manufacturing processes, as well as variations due to operating conditions like voltage, temperature, and aging over time. The document also discusses approaches for modeling and accounting for variations, such as using timing corners in sign-off analysis and parametric on-chip variation modeling in the standard cell library.

1. Study of Inter and Intra Chip
Variations
Rajesh Mekala

2. Outline
● Motivation
● Chip Manufacturing
○ FEOL
○ BEOL
● PVT variations
○ Metal variations
○ Clocks
● Corners
● Modeling OCV
○ POCV
● Misc. variations
● Margins
● Appendix

3. Motivation
● Understand sources of variations
● Timing Corners
● Modeling on-chip variation
● Design Margining
● Sign-off criterion
* Embedded hyperlinks for an in-depth study

4. Manufacturing Stack

5. Manufacturing Process
● Crystal growth* → Ingot* (Silicon cylinder) → Wafers* → Chips

6. Manufacturing Stack
● FEOL* (Front End of Line)
○ First portion of IC fabrication
○ CMOS fabrication steps to form transistors:
■ Selecting type of wafer*
■ Cleaning of the wafer
■ Well formation
■ Gate, Drain and Source module formation
○ Manufacturing complexity increases with
FinFets
○ Base Tapeout (longer time to prepare the
masks)
■ Presents the opportunity for metal only
ECOs

7. Manufacturing Stack
● BEOL* (Back End of Line)
○ Second portion of IC fabrication
○ Devices get interconnected with wiring
○ PMD* module indicates beginning of BEOL
○ BEOL includes
■ Vias
■ Insulating layers (dielectrics)
■ Metal layers
■ Bonding sites (chip2package connections)
○ Double patterning (<16nm)
○ Metal Tapeout
■ Further changes are re-spins

8. From Sand to Silicon

9. FEOL variations

10. Transistor Manufacturing
Main Repetitive Steps:
1. Diffusion
2. Etching
3. Photolithography
4. Deposition

11. Types of Variations
● Parameters of transistors vary from:
○ Lot to lot (Inter process variation*)
○ Wafer to wafer (Inter process variation)
○ Die to die (Intra process variation)
○ Transistor to transistor (On Chip Variation)
● Systematic Variation
○ Possible to correct (e.g. OPC, fill)
● Random Variation
○ Stochastic* in nature
Aging with time
*RDF = Random Dopant Fluctuation
*LER = Line Edge Roughness
*NBTI = Negative Bias Temperature Instability
*HCI = Hot Carrier Injection
*TDDB = Time Dependent Dielectric Breakdown

12. FEOL Variations
Random variations in process parameters:
● Wgate
● Lgate
● RDF (Random Dopant Fluctuation - n+ and p+)
● Oxide thicknesses (tox)
● Diffusion Depths
These variations affect performance and power of the design

13. Process convention
Industry uses two-letters to describe corners:
● 1st letter → NMOS device
● 2nd letter → PMOS device
● 5 classic corners:
○ FF (fast fast)
○ SF (slow fast)
○ SS (slow slow)
○ FS (fast slow)
○ TT (typical typical)
● Process typically tuned to TT
● FF corner → skew both P and N devices to the fast
corner (Process tuning)
● Ring Oscillators to determine the process

14. BEOL variations

15. BEOL variations
● Chip area increasing (greater integration)
● Device dimensions scaled down
● Scaled wires are
○ Longer (chip area scaling)
○ Thinner (minimum dimension scaling)
○ Taller (Do not increase resistance)
● Wire delay* limiting performance
● Double patterning
● Via resistance variation
Processes affecting the FEOL and BEOL are
completely orthogonal (uncorrelated parameters)

16. BEOL variations
● Line Edge Roughness
○ Random variation* in:
■ Lithography
■ Photoresist
■ Etching
● Dishing and Erosion* during CMP
Resistance and Capacitance changes with
BEOL variations → Performance degradation
1. Time independent variations
2. AC-EM cause a shift in performance
over time

17. Reduce BEOL variations
● Manufacturability:
○ OPC
● Design
○ Metal fill
○ Shielding
○ NDR

18. Reduce BEOL variations
● Design:
○ Wire length histogram
○ Random Variation:
■ Timing derate
● Remove pessimism of derate by 2-sigma corners
● Modeling:
○ Extraction tool accuracy
○ Higher order Interconnect delay calculation

19. Corner Lots

20. Process corner lots
● Definition: Groups of wafers whose process
parameters are carefully tuned to known process
extremes
○ Characterize them at various temperatures
and voltages
● process lots = corner lots = split lots = skewed lots
● If characterization is within accepted limits →
mass manufacturing of chips begins
● Corner lots should be produced after tapeout and
before releasing to production
○ Process Qualification during chip
qualification

21. Voltage Variations

22. Voltage Variations
● Voltage Source is non-ideal
● DC static voltage drop
● AC transient variations
● Transistor delays are sensitive to swings in VDD and VSS

23. Voltage Variations
● VDD → IDS (drive) → tPHL → F
● Delay curve is nonlinear
● SVT devices → more sensitive to voltage change
● IP teams - choose operational voltage and clock
frequencies
○ Multi-mode operation (high perf, low power)

24. Mitigate Voltage Variations
Voltage
Time
Vsu = Non-ideal power supply voltage
Current Profile
Ptr = Voltage at gate
Leakage current (min/max)
● STA at minimum voltage (capture worst
case)
● Validate library models* for the corners
● Static IR drop < 10% VDD (characterized
library)
○ 10% worst case IR drop from the
power supply to the PG pins of
transistor (can be budgeted)
○ Sense it on-chip to feedback to VR
● DCAP for dynamic IR drop
● Capacitance with low resistive/inductive
paths to the gates

25. Temperature Variations

26. Temperature Variations
Cause:
● Work load (application) → Switching activity →
Power dissipation → Heat → Temperature
increase
Mitigation:
● Worst case analysis:
○ Gate dominant ?
○ Wire dominant ?
○ Depending on the technology node
○ Lower VDD, Lower T (Setup)
■ Gate dominant, temperature
inversion
○ Higher VDD, Higher Temp (Hold)
○ Mixed corners to cover skewed affects
● Low Power Design
● Cooling solutions

27. Summary

28. Categorization
Variation
Static Dynamic
On-Chip
D2D, W2W
Random Correlated
RDF Leff
Weff Mobility
RSD Rwire
Cwire
Litho CMP
Random Systematic
Misc.
Process
Litho Effects
Systematic
Layout
Effects
Stress
Process
Device
Process
Tem
p
Vdd Jitter SI MIS
Circuit
BTI SER
HCI TDDB
Reliability

29. History of Focus Areas
● Key physical design focus area with shrinking technology nodes

30. Clocks

31. Clock Skew and Jitter
Skew = ‘static’ time difference between any 2 electrical
nodes
Sources: placement distribution (local skew)
Jitter = ‘dynamic’ time difference of a signal with respect to
an ideal signal
Sources: PLL source, clock network jitter, SI
Clock overhead* = setup time, hold time requirements of
sequential cells
L1
L2

32. Sources of Clock Variation
● Skew:
○ Clock buffers drive strength and channel lengths
○ Static voltage drop
○ Local Hot spots
○ Process variation (Leff)
○ Routes RC mismatch
○ BEOL variations
● Jitter
○ Switching activity → Power supply variations
with time
○ PLL source Jitter
○ Temperature Gradient
○ Clock network jitter (dynamic voltage drop)
○ Wire coupling capacitance
■ Data change in different cycles

33. Strategies: Reduce Clock Tree OCV
● Minimize clock* divergence
● Choose PLL with least clock source jitter
● Balance cell and net delays
● Inverters - minimize DCD
● Minimize clock tree latency
● LVT cells, same channel length
○ Minimize cross corner delay variation
● NDR, shielding
○ Minimize coupling (spatial + temporal)
● Specific metal layers to minimize BEOL process variations
● Clock tree optimized std_cells in clock path
● Robust PG network
● Global clock tree buffers with embedded DCAP

34. Timing Corners

35. Timing Corners
● Corner Definition:
○ A point in the PVT/RC space where cell/net delays have extreme values (all cell delays are the max or
min and all net delays are the max or min independently)
● Timing Sign-off (STA) focuses on Corners [Worst Case Analysis]
Design Space
Process
Voltage
Temperatur
e

36. Timing Corners
*(Generally Ignored) Vias {max/min/typ cap/resistance}
● All Combinations: 3 * 3 * 5 * 5 = 225
● Chosen Corners: ~50
Voltage
Min
Typ
Max
Tem
p
Min
Typ
Max
FEOL
SS
TT
FF
SF
FS
BEOL
Cw
Cb
RCw
RCb
RCtyp

37. Corner explosion
Modes of operation:
● func
● test
○ shift
○ capture
*Create additional
corners
Multi Voltage Domains:
● Vmem
● Vlogic
*Create additional
corners
Aging Degradation:
● NBTI
● HCI
● TDDB
*Derated libraries like
EOL and BOL (or)
sign-off derate
Analysis Overhead:
● Temperature Inversion
● DPT corners
● Via variations
● Over drive mode
● Confidence bounds (3-
sigma/2-sigma)
*Create additional corners

38. Corner Specifications (Example)
Mode Voltage FEOL
process
BEOL
process
Temperature
(Junction)
Variation
Model
Purpose*
func 0.9 * VDDlogic
0.9 * VDDmem
ss cw_ccw -30c aocv Timing Specification (conservative)
func VDDlogic
VDDmem
tt ctyp 25c aocv Timing Specification (Typical/Binning)
func 1.1 * VDDlogic
1.1 * VDDmem
ff cb_ccb 125c aocv Race conditions, Hold timing, Noise
func 0.9 * VDDlogic
0.9 * VDDmem
ss cb_ccb 125c aocv Race of gates against wires
func 1.1 * VDDlogic
1.1 * VDDmem
ff cw_ccw -30c aocv Race of wires against gates

39. Modeling Variations

40. Modeling variations
Global OCV (flat-derate):
- Easier with a lot of pessimism
SSTA:
- SSTA libs, STA tool support, large compute time
Advanced OCV:
- Reduce pessimism from GOCV taking
advantage of path depth and spatial correlation
Cell Based AOCV:
- Std_cell specific AOCV tables
Parametric OCV:
- LVF characterization of standard cells
- Representative of SSTA

41. Parametric OCV
● POCV timing analysis*:
Instead of timing windows (minimum and maximum delays) for each timing arc, calculate the delay as
a function of a Gaussian normal distribution P
delay = nominal_delay + σ * P
nominal_delay, σ are part of library
● POCV characterization is embedded into standard cell library
○ Slew and load dependant variation
● Close to Statistical STA

42. Modeling and analysis errors
● Error in gate delay models (model-to-hardware)
○ Library to Silicon
● std_cell characterization test bench accuracy
○ SI optimism/pessimism
● Delay calculation errors
○ Delay estimation interpolation and extrapolation
○ max/min trans/cap within lib characterization bounds
● Nonlinear delay scaling across PVT corners
● Extraction tool accuracy
○ Lumped v.s. Distributed RC models
○ 3D modeling

43. Industry Margining Process
Foundry and EDA tools/vendors
● Extremely important to
monitor different margins
using in the design cycle
● STA sign-off involves
interaction with many teams
for coming to consensus

44. What is golden/sign-off ?
● Abstraction reduces accuracy
○ Floorplanning doesn’t need sign-off timing
● Models (.libs, etc.) → SPICE → Silicon* (Hardware)
● Margins feedback from synthesis to bring-up and process data
● Test chips to study lithography issues, transistor model correlation, statistical properties of
the process
● Robust clock tree design (Cell selection, NDRs, shielding, Mesh)
● Exhaustive checks across timing corners
● Robust IR drop analysis

45. OCV margins
Phase of the design Setup Hold max_trans/max_
cap
Synthesis flat uncertainty number to account for:
1. Clock: skew + jitter + OCV + SI
2. Data: OCV, SI
3. Tools miscorrelation (including delay
calculation, analysis differences)
4. Virtual to Actual route differences
5. Model mismatches (CCS, NDM etc.)
6. Blanket setup margin (Other margins
and RTL feedback)
7. Top to Block miscorrelation
8. Library guardband
flat margin (no optimization in synthesis) flat number
Implementation Placement: all the margins in synthesis
CTS: all except clock skew, clock SI
Route: all except clock skew, clock and data SI,
miscorrelation
flat uncertainty number accounting for:
1. Clock: uncertainty
2. Top to Block miscorrelation for
IPs
3. Route, model differences, extra
guardband
Margin w.r.t. each
scenario and clock
frequency
Sign-off Sign-off timing tool (PBA) with accurate margins
(no pessimism) - ignoring guardband margins.
(Dependant on clock frequency, VT-type, corner)
Sign-off timing tool with accurate
margins ignoring guardband margins
(Dependant on clock frequency, VT-
type, corner)
Sign-off criterion w.r.t.
Each scenario and clock
frequency

46. Appendix

47. Reading material
Good reads for in-depth analysis:
● Variability Modeling and Statistical Parameter Extraction for CMOS Devices (**)
● History of Timing Closure (*)
● Layout variation effects (*)
● Corner-based Timing Signoff and What Is Next (***)
● Clocking for high-performance circuits (**)
● Methodology to close timing with hundreds of MCMM scenarios (***)
● How to deal with large process variations (*)
● Parameter variation tolerance (*)
● Multi Input Switching (**)
● CMOS VLSI Design (**)
● Process Technology Variation (***)

48. Sources of Variations
Random distribution of identically drawn devices is
caused by variations in process parameters such as:
● Impurity concentration densities
● Oxide thicknesses
● Diffusion Depths
● Many other physical aspects of a transistor
All of these variations affect cell delay, threshold current
=> impacts performance and power
Changes in these parameters cause electrical
parameters to vary such as threshold voltage, Weff,
Leff, etc.
Parameters affecting the FEOL and BEOL are
completely orthogonal (uncorrelated)
Variations in the dimensions of the devices: Limited
resolution of the photolithographic process which
causes W/L variations in MOS transistors.

49. BEOL variations
What can we model deterministically?
● Optical and etching environment
● CMP etching as function of location on a wafer
● Feature size as a function of position in optical field

50. BEOL variations
● With double patterning in metal layer masks
beyond 20nm technologies, interconnect
modeling corners increased

52. The saturation current of a cell depends on the power supply. The
delay of a cell is dependent on the saturation current. In this way,
the power supply inflects the propagation delay of a cell.
Throughout a chip, the power supply is not constant and hence the
propagation delay varies in a chip. The voltage drop is due to
nonzero resistance in the supply wires. A higher voltage makes a
cell faster and hence the propagation delay is reduced. The
decrease is exponential for a wide voltage range.
● Best case: fast process,
highest voltage and lowest
temperature
● Worst case: slow process,
lowest voltage and highest
temperature

53. Summary of Variations
● Manufacturing variations
○ Leff: random and systematic components
○ Metal thickness variations due to chemical-mechanical
polishing (CMP)
○ Random dopant effects which cause random Vt variations
○ Line-edge roughness effects
● Voltage variations
○ IR drop across surface of chip, in different voltage islands
○ IR drop from cycle to cycle
● Temperature variations
○ Across surface of chip
○ From cycle to cycle
● Electrical reasons
○ Coupling noise which may or may not occur in any given
cycle
○ Pre-charging of internal nodes
○ History effect in SOI circuits
○ Simultaneous switching
● Aging at different rates
○ Hot electrons, NBTI/PBTI, electromigration

54. Interpolated voltage variation model

55. Solving BEOL variations
Litho Etching CMP Location
in field
Location
on wafer
Fab Random
variations
Compensat
e later
OPC Metal fill
Reduce
uncertainty
Shielding Metal fill
Reduce
impact
OPC Clock
Mesh
Statistical
analysis
Worst case
analysis

56. Margins at different stages
PHASE TOOL SETUP Comment HOLD Comment MAX_TRANS
synthesis DC ? blanket setup margin for all blocks, 1 corner (primary setup) ? ? 100pS
DCT ? blanket setup margin for all blocks, 1 corner (primary setup) ? ? 100pS
clock_tree_margin skew + noise + Jsrc + Jmn + Jcts
placement Innovus ? blanket setup margin for all blocks, 1 corner (primary setup) ? ? ?
CTS Innovus 0% ? ?
post-CTS Innovus Jsrc + Jmn + Jcts + (skew = 0) + (noise = 0)
route Innovus 0% ? ?
post-route Innovus
signoff PT 0% ? ?
minSA ? ? global speed up
POCV On Chip Variations
MIS for hold POCV On Chip Variations