8. A deep dive into a chip
Packaged chip Silicon die (100-400 mm2)
Die cross-section
Transistor (FET)
6-15 metal layers (wires)
8
9. MOSFET Intro
Nearly all digital systems are built using field effect
transistors, which are voltage-controlled switches.
FETs come in two varieties: nFET and pFET
9
A high voltage at gate creates
conducting path between
source and drain
A low voltage at gate creates
conducting path between
source and drain
10. MOS Structure & operation
10
Polysilicon Gate
Silicon Dioxide (SiO2) Insulator
P-type Body
Depletion region
Inversion region
Depletion region
12. MOS Transistor Operation
12
Liner Mode:
As Vgs > Vt the inversion region
created a channel between source &
drain.
If Vgd = Vgs ; Vds = 0 Ids =0
If Vds ↑ Ids ↑
Linear
14. I-V Characteristic
In Linear region, Ids depends on
✗ How much charge is in the channel?
✗ How fast is the charge moving?
14
15. Channel Charge
MOS structure looks like parallel
plate capacitor while operating in
inversions:
Gate – oxide – channel
Qchannel = CV
C = Cg = eoxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt
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n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-
drain
Vds
channel
-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, eox
= 3.9)
polysilicon
gate
Cox = eox / tox
16. Carrier Velocity
Charge is carried by e-
Electrons are propelled by the lateral electric
field between source and drain:
𝐸 = ൗ
𝑉𝑑𝑠
𝐿
Carrier velocity v proportional to lateral E-field :
𝑣 = 𝜇𝐸 ∴ 𝜇 called mobility
Time for carrier to cross channel:
𝑡 = Τ
𝐿
𝑣
16
c
17. nMOS Linear I-V
Now we know:
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
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𝐼𝑑𝑠 =
𝑄𝑐ℎ𝑎𝑛𝑛𝑒𝑙
𝑡
= 𝜇𝐶𝑜𝑥
𝑊
𝐿
𝑉
𝑔𝑠 − 𝑉𝑡 − ൗ
𝑉𝑑𝑠
2 𝑉𝑑𝑠
= 𝛽 𝑉
𝑔𝑠 − 𝑉𝑡 − ൗ
𝑉𝑑𝑠
2 𝑉𝑑𝑠
∴ 𝛽 = 𝜇𝐶𝑜𝑥
𝑊
𝐿
18. nMOS Saturation I-V
If 𝑉𝑔𝑑 < 𝑉𝑡, channel pinches off near drain
When 𝑉𝑑𝑠 > 𝑉𝑑𝑠𝑎𝑡 = 𝑉
𝑔𝑠 − 𝑉𝑡
Now drain voltage no longer increases
current
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𝐼𝑑𝑠 = 𝛽 𝑉
𝑔𝑠 − 𝑉𝑡 − ൗ
𝑉𝑑𝑠
2 𝑉𝑑𝑠
=
𝛽
2
𝑉
𝑔𝑠 − 𝑉𝑡
2
c
19. nMOS I-V Summary
19
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V
= − −
−
22. C-V characteristic (Gate Capacitance)
Approximate channel as connected to source
𝐶𝑔𝑠 = 𝜀𝑜𝑥 ൗ
𝑊𝐿
𝑡𝑜𝑥
= 𝐶𝑜𝑥𝑊𝐿 = 𝐶𝑝𝑒𝑟𝑚𝑖𝑐𝑟𝑜𝑛𝑊
Cpermicron is typically about 2 fF/mm
22
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, eox
= 3.9e0
)
polysilicon
gate
23. C-V characteristic (Diffusion Capacitance)
Csb, Cdb
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
✗ Use small diffusion nodes
✗ Comparable to Cg for contacted diff
✗ ½ Cg for uncontacted
✗ Varies with process
23
24. DC Characteristic
Analyze DC Characteristics of CMOS
Gates by studying an Inverter
DC Analysis of CMOS Inverter
✗ Vin, input voltage
✗ Vout, output voltage
✗ single power supply, VDD
✗ Ground reference
✗ find Vout= f(Vin)
Voltage Transfer Characteristic (VTC)
✗ plot of Vout as a function of Vin
✗ vary Vin from 0 to VDD
✗ find Vout at each value of Vin
24
Idsn
Idsp
Vout
VDD
Vin
25. Inverter Voltage Transfer Characteristics
Output High Voltage, VOH
–maximum output voltage
.occurs when input is low (Vin= 0V)
•pMOS is ON, nMOS is OFF
•pMOS pulls Vout to VDD
. .VOH= VDD
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26. Inverter Voltage Transfer Characteristics
26
Output Low Voltage, VOL
–minimum output voltage
•occurs when input is high (Vin=VDD)
•pMOS is OFF, nMOS is ON
•nMOS pulls Vout to Ground
VOL= 0 V
28. Inverter Voltage Transfer Characteristics
28
Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
C
Vout
0
Vin
VDD
VDD
A B
D
E
Vtn
VDD
/2 VDD
+Vtp
30. CMOS Fabrication
Starting wafer is pure silicon crystal.
Multiple process steps deposit new materials and etch existing layers using
photolithography (light focused through masks).
Modern logic chips fabricated on 20cm (8”) wafers, ~100s chips/wafer.
Wafer sawed into separate chips after fabrication.
Chips then placed into packages (see packaging lecture later in course)
[6” wafer of T0 chips, 1.0mm, 2 Al layers, 1995]
One chip
31. Basic CMOS Fabrication Steps
31
Growing silicon dioxide to serve as an insulator
between layers deposited on the surface of the silicon
wafer.
Doping the silicon substrate with acceptor and donor atoms to
create p- and n-type diffusions that form isolating PN junctions
and one plate of the MOS capacitor.
Depositing material on the wafer to create masks,
wires and the other plate of the MOS capacitor.
Etching deposited materials to create the
appropriate geometric patterns.
Figures are from W. Maly, Atlas of IC Technologies: An Introduction to VLSI Processes.
(ignore dimensions in figures – they are quite out-of-date!)
34. Design Rules
Design rules are an abstraction of the fabrication process that specify various
geometric constraints on how different masks can be drawn.
Design rules can be absolute measurements (e.g., in nm) or scaled to an abstract
unit, the lambda. Lambda-based designs are scaled to the appropriate absolute
units depending on the manufacturing process finally used.
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35. Lambda-based Design Rules
One lambda (l)= one half
of the “minimum” mask
dimension.
Typically, the length of a
transistor channel is 2l.
Usually all edges must be
“on grid”, e.g., in the
MOSIS scalable rules, all
edges must be on a
lambda grid.
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36. Technology related CAD
Big companies, lots of money, 40 years of integrated circuit
design experience, conferences, journals, powerful PCs… what’s
the problem?
IC CAD tools are difficult to use
✗ Written by electrical engineers (not professional programmers)
✗ Incredibly buggy
✗ Not documented
✗ Rely on ancient, outdated file formats for interoperability
✗ Still mostly rely on command-line interfaces
✗ Utilize outdated, primitive, buggy APIs for GUIs
✗ Inherently required to solve hard problems
■ Place components, route wires
■ Must utilize advanced heuristics that are only as good as
fabrication process technology information and user input
(garbage-in, garbage-out)
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37. Technology related CAD
Cadence tools
✗ “IC-Tools” => IC5141 package (Linux)
✗ Collection of tools managed by Design Framework II (dfII)
■ Virtuoso schematic/layout editor
■ Analog Environment
■ Spectre simulator
■ Diva DRC, EXT, LVS
Other Cadence tools
✗ SignalStorm => TSI42 package (Linux)
✗ Abstract Generator => DSMSE54 (Solaris)
✗ First Encounter => SOC42 package (Linux)
Synopsys
✗ Design Compiler (Linux)
Mentor
✗ HDL Designer (Linux)
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