3D packaging stacks separate chips in a single package to save space without integrating the chips. Monolithic 3D ICs build components in layers on a single wafer then dice it, avoiding alignment and bonding issues. Multi-wafer 3D ICs build components on separate wafers, which must be aligned, bonded, and thinned with vertical connections added through silicon vias. 3D ICs promise benefits like reduced cost from improved yield, lower power from shorter wires, and new design possibilities from added connectivity, but challenges include heat dissipation, design complexity, and testing of independent dies.

2. 3D packaging saves space by stacking
separate chips in a single package. This
packaging, known as System in
Package (SiP) or Chip Stack MCM, does
not integrate the chips into a single circuit.
The chips in the package communicate
using off-chip signaling, much as if they
were mounted in separate packages on a
normal circuit board.

4. Monolithic
• Electronic components and their connections (wiring) are
built in layers on a single semiconductor wafer, which is
then diced into 3D ICs. There is only one substrate, hence
no need for aligning, thinning, bonding, or through-silicon
vias. A recent breakthrough overcame the process
temperature limitation by partitioning the transistor
fabrication to two phase. A high temperature phase which is
done before layer transfer follow by a layer transfer use ion-cut,
also known as layer transfer that has been the
dominant method to produce SOI wafers for the past two
decades. Multiple thin (10s–100s nanometer scale) layers
of virtually defect free Silicon can be created by utilizing low
temperature (<400C) bond and cleave techniques, and
placed on top of active transistor circuitry.

5.  Electronic components are built on two or more semiconductor
wafers, which are then aligned, bonded, and diced into 3D
ICs. Each wafer may be thinned before or after bonding.
Vertical connections are either built into the wafers before
bonding or else created in the stack after bonding. These
"through-silicon vias" (TSVs) pass through the silicon
substrate(s) between active layers and/or between an active
layer and an external bond pad. Wafer-on-wafer bonding can
reduce yields, since if any 1 of N chips in a 3D IC are
defective, the entire 3D IC will be defective. Moreover, the
wafers must be the same size, but many exotic materials (e.g.
III-Vs) are manufactured on much smaller wafers than CMOS
logic or DRAM (typically 300 mm), complicating
heterogeneous integration.

7.  Traditional scaling of semiconductor chips also improves
signal propagation speed. 3-D integrated circuits were
invented to address the scaling challenge by stacking 2-
D dies and connecting them in the 3rd dimension. This
promises to speed up communication between layered
chips, compared to planar layout.[9] 3D ICs promise many
significant benefits, including:
Cost:
 Partitioning a large chip into multiple smaller dies with 3D
stacking can improve the yield and reduce the fabrication
cost if individual dies are tested separately.[10][11]

8. Power
Keeping a signal on-chip can reduce its power consumption by 10–100
times. Shorter wires also reduce power consumption by producing
less parasitic capacitance.Reducing the power budget leads to less heat
generation, extended battery life, and lower cost of operation.
Design
The vertical dimension adds a higher order of connectivity and offers new
design possibilities.
Circuit security
The stacked structure complicates attempts to reverse engineer the circuitry.
Sensitive circuits may also be divided among the layers in such a way as to
obscure the function of each layer.

10. Heat-Heat building up within the stack
must be dissipated. This is an inevitable
issue as electrical proximity correlates with
thermal proximity. Specific thermal
hotspots must be more carefully managed.
 Design complexity-Taking full advantage of
3D integration requires sophisticated
design techniques and new CAD tools.

11. . Testing-
 To achieve high overall yield and reduce costs, separate testing
of independent dies is essential.[3][19] However, tight integration
between adjacent active layers in 3D ICs entails a significant
amount of interconnect between different sections of the same
circuit module that were partitioned to different dies. Aside from
the massive overhead introduced by required TSVs, sections of
such a module, e.g., a multiplier, cannot be independently tested
by conventional techniques. This particularly applies to timing-critical
paths laid out in 3D.
Yield-
 Each extra manufacturing step adds a risk for defects. In order for
3D ICs to be commercially viable, defects could be repaired or
tolerated, or defect density can be improved.

12. Gate-level integration
 This style partitions standard cells between multiple dies. It promises
wirelength reduction and great flexibility. However, wirelength
reduction may be undermined unless modules of certain minimal
size are preserved.
Block-level integration
 This style assigns entire design blocks to separate dies. Design
blocks subsume most of the netlist connectivity and are linked by a
small number of global interconnects.

13. 3DS (three dimensional stack) is a new IC
packaging technology which uses the die stacking technique.
The digital electronics market requires a higher
density semiconductor memory chip in order to cater to
recently released CPUcomponents, and the multiple die
stacking technique has been suggested as a solution to this

14. Expanded memory capacity
Load reduction ; Higher frequency
Bus turn around time will reduce (Improved
bus efficiency)
Active termination power reduction ; Lower
power consumption

16. Higher cost
• Drill holes/Fill plug by metal/Put bumps
• Thinning
• Handling/Align
• 2 types of die (Master and Slave)