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Technology Trends: Moore’s Law
2X transistors/Chip Every 1.5 years
Called “Moore’s Law”
Moore’s Law
Microprocessors have
become smaller, denser,
and more powerful.
Gordon Moore (co-founder of
Intel) predicted in 1965 that the
transistor density of
semiconductor chips would
double roughly every 18 months.
Societal Scale Information Systems
Scalable, Reliable,
Secure Services
MEMS for
Sensor Nets
Internet
Connectivity
Clusters
Massive Cluster
Gigabit Ethernet
Databases
Information Collection
Remote Storage
Online Games
Commerce
…
•The world is a large parallel system
–Microprocessors in everything
–Vast infrastructure behind them
People-to-Computer Ratio Over
Time
•Today: Multiple CPUs/person!
From David Culler
ManyCore Chips: The future is here
•“ManyCore” refers to many processors/chip
–64? 128? Hard to say exact boundary
•How to program these?
–Use 2 CPUs for video/audio
–Use 1 for word processor, 1 for browser
–76 for virus checking???
•Parallelism must be exploited at all levels
Intel 80-core multicore chip (Feb 2007)
80 simple cores
Two floating point engines /core
Mesh-like "network-on-a-chip“
100 million transistors
65nm feature size
Frequency Voltage Power Bandwidth
Performance
3.16 GHz 0.95 V 62W 1.62 Terabits/s 1.01 Teraflops
5.1 GHz 1.2 V 175W 2.61 Terabits/s 1.63 Teraflops
5.7 GHz 1.35 V 265W 2.92 Terabits/s 1.81 Teraflops
Another Challenge: Power Density
•Moore’s Law Extrapolation
–Potential power density reaching amazing levels!
•Flip side: Battery life very important
–Moore’s law can yield more functionality at equivalent
–(or less) total energy consumption
Computer System Organization
•Computer-system operation
–One or more CPUs, device controllers connect
through common bus providing access to shared
memory
–Concurrent execution of CPUs and devices
competing for memory cycles
Functionality comes with great
complexity!
Proc
Caches
Busses
Memory
I/O Devices:
Controllers
adapters
Disks
Displays
Keyboards
Networks
Pentium IV Chipset
Sample of Computer Architecture
Topics
Instruction Set Architecture
Pipelining, Hazard Resolution,
Superscalar, Reordering,
Prediction, Speculation,
Vector, Dynamic Compilation
Addressing,
Protection,
Exception Handling
L1 Cache
L2 Cache
DRAM
Disks, WORM, Tape
Coherence,
Bandwidth,
Latency
Emerging Technologies
Interleaving
Bus protocols
RAID
VLSI
Input/Output and Storage
Memory
Hierarchy
Pipelining and Instruction
Level Parallelism
Network
Communication
Other Processors
Increasing Software Complexity
From MIT’s 6.033 course
Example: Some Mars Rover
(“Pathfinder”) Requirements
•Pathfinder hardware limitations/complexity:
–20Mhz processor, 128MB of DRAM, VxWorks OS
–cameras, scientific instruments, batteries,
–solar panels, and locomotion equipment
–Many independent processes work together
•Can’t hit reset button very easily!
–Must reboot itself if necessary
–Always able to receive commands from Earth
•Individual Programs must not interfere
–Suppose the MUT (Martian Universal Translator Module) buggy
–Better not crash antenna positioning software!
•Further, all software may crash occasionally
–Automatic restart with diagnostics sent to Earth
–Periodic checkpoint of results saved?
•Certain functions time critical:
–Need to stop before hitting something
–Must track orbit of Earth for communication
How do we tame complexity?
•Every piece of computer hardware different
–Different CPU
–Pentium, PowerPC, ColdFire, ARM, MIPS
–Different amounts of memory, disk, …
–Different types of devices
–Mice, Keyboards, Sensors, Cameras, Fingerprint readers
–Different networking environment
–Cable, DSL, Wireless, Firewalls,…
•Questions:
–Does the programmer need to write a single program that performs
many independent activities?
–Does every program have to be altered for every piece of hardware?
–Does a faulty program crash everything?
–Does every program have access to all hardware?

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Technology trends Moore’s law

  • 1. Technology Trends: Moore’s Law 2X transistors/Chip Every 1.5 years Called “Moore’s Law” Moore’s Law Microprocessors have become smaller, denser, and more powerful. Gordon Moore (co-founder of Intel) predicted in 1965 that the transistor density of semiconductor chips would double roughly every 18 months.
  • 2. Societal Scale Information Systems Scalable, Reliable, Secure Services MEMS for Sensor Nets Internet Connectivity Clusters Massive Cluster Gigabit Ethernet Databases Information Collection Remote Storage Online Games Commerce … •The world is a large parallel system –Microprocessors in everything –Vast infrastructure behind them
  • 3. People-to-Computer Ratio Over Time •Today: Multiple CPUs/person! From David Culler
  • 4. ManyCore Chips: The future is here •“ManyCore” refers to many processors/chip –64? 128? Hard to say exact boundary •How to program these? –Use 2 CPUs for video/audio –Use 1 for word processor, 1 for browser –76 for virus checking??? •Parallelism must be exploited at all levels Intel 80-core multicore chip (Feb 2007) 80 simple cores Two floating point engines /core Mesh-like "network-on-a-chip“ 100 million transistors 65nm feature size Frequency Voltage Power Bandwidth Performance 3.16 GHz 0.95 V 62W 1.62 Terabits/s 1.01 Teraflops 5.1 GHz 1.2 V 175W 2.61 Terabits/s 1.63 Teraflops 5.7 GHz 1.35 V 265W 2.92 Terabits/s 1.81 Teraflops
  • 5. Another Challenge: Power Density •Moore’s Law Extrapolation –Potential power density reaching amazing levels! •Flip side: Battery life very important –Moore’s law can yield more functionality at equivalent –(or less) total energy consumption
  • 6. Computer System Organization •Computer-system operation –One or more CPUs, device controllers connect through common bus providing access to shared memory –Concurrent execution of CPUs and devices competing for memory cycles
  • 7. Functionality comes with great complexity! Proc Caches Busses Memory I/O Devices: Controllers adapters Disks Displays Keyboards Networks Pentium IV Chipset
  • 8. Sample of Computer Architecture Topics Instruction Set Architecture Pipelining, Hazard Resolution, Superscalar, Reordering, Prediction, Speculation, Vector, Dynamic Compilation Addressing, Protection, Exception Handling L1 Cache L2 Cache DRAM Disks, WORM, Tape Coherence, Bandwidth, Latency Emerging Technologies Interleaving Bus protocols RAID VLSI Input/Output and Storage Memory Hierarchy Pipelining and Instruction Level Parallelism Network Communication Other Processors
  • 9. Increasing Software Complexity From MIT’s 6.033 course
  • 10. Example: Some Mars Rover (“Pathfinder”) Requirements •Pathfinder hardware limitations/complexity: –20Mhz processor, 128MB of DRAM, VxWorks OS –cameras, scientific instruments, batteries, –solar panels, and locomotion equipment –Many independent processes work together •Can’t hit reset button very easily! –Must reboot itself if necessary –Always able to receive commands from Earth •Individual Programs must not interfere –Suppose the MUT (Martian Universal Translator Module) buggy –Better not crash antenna positioning software! •Further, all software may crash occasionally –Automatic restart with diagnostics sent to Earth –Periodic checkpoint of results saved? •Certain functions time critical: –Need to stop before hitting something –Must track orbit of Earth for communication
  • 11. How do we tame complexity? •Every piece of computer hardware different –Different CPU –Pentium, PowerPC, ColdFire, ARM, MIPS –Different amounts of memory, disk, … –Different types of devices –Mice, Keyboards, Sensors, Cameras, Fingerprint readers –Different networking environment –Cable, DSL, Wireless, Firewalls,… •Questions: –Does the programmer need to write a single program that performs many independent activities? –Does every program have to be altered for every piece of hardware? –Does a faulty program crash everything? –Does every program have access to all hardware?