Easiest Monolithic 3D IC

MonolithIC 3D Inc. Patents Pending 1
Monolithic 3D –
The Most Effective Path for
Future IC Scaling

Agenda:
 Semiconductor Industry is reaching an inflection point
 Monolithic 3D IC – The next generation technology driver
 Monolithic 3D – Game Change, using existing transistor process !
 Heat removal
 The MonolithIC 3D Advantages
 Summary

Martin van den Brink -EVP & CTO, ASML
ISSCC 2013 & SemiconWest 2013

The Current 2D-IC is Facing Escalating Challenges
 On-chip interconnect is
 Dominating device power consumption, performance and cost
B. Wu, A. Kumar, Applied Materials

3D and EDA need to make up for
Moore’s Law, says Qualcomm*
 “Qualcomm is looking to monolithic 3D and smart circuit architectures to
make up for the loss of traditional 2D process scaling as wafer costs for
advanced nodes continue to increase. .. Now, although we are still
scaling down it’s not cost-economic anymore”
 “Interconnect RC is inching up as we go to deeper technology. That is a
major problem because designs are becoming interconnect-dominated.
Something has to be done about interconnect. What needs to be done is
monolithic three-dimensional ICs.”
 “TSV...are not really solving the interconnect issue I’m talking about.
So we are looking at true monolithic 3D. You have normal vias
between different stacks.”
* Karim Arabi Qualcomm VP of engineering, DAC 2014 Key Note
<http://www.techdesignforums.com/blog/2014/06/05/karim-arabi-monolithic-3dic-dac-2014/>

Monolithic 3D Qualcomm SoCs by 2016*
*EE Times 3/31/2015 <http://www.eetimes.com/document.asp?doc_id=1326174&piddl_msgid=338050#msg_338050>
 “3DV, enables die size to be shrunk in half, while simultaneously increasing yields,“
 Qualcomm's motivation, according to Arabi, is market share in the 8 billion
smartphones that he predicts will be produced from 2014 to 2018
6
In the fabrication process of front-to-back (F2B) 3DVs (a) the bottom tier is created the same way as 2D-
ICs. (b,c,d) To add another layer, first a thin layer of silicon is deposited on top of the bottom tier. (e) This
front-end-of-line (FEOL) process of the top tier permits the addition of normal vertical vias and top-tier
contacts. (f) Finally back-end-of-line (BEOL) processing creates the top-tier. (Source:Qualcomm)

Even Intel Agrees – 7nm is the Limit for Silicon
ISSCC 2015

“Bohr predicted that Moore's Law will not come to
an abrupt halt, but will morph and evolve and go in
a different direction, such as scaling density by
the 3D stacking of components rather than
continuing to reduce transistor size.”
*http://www.v3.co.uk/v3-uk/news/2403113/intel-predicts-moores-law-to-last-another-10-years
”Intel’s Bohr agrees that 3D structures will become
more important. He said the kind of through-
silicon vias used for today’s chip stacks need
to improve in their density by orders of
magnitude.”
**http://www.eetimes.com/document.asp?doc_id=1326336&page_number=5

“Samsung spent several years developing
its 14nm technology and debating which
process node it would invest in after
28nm. Low expects that 28nm will still be
a popular process node for years to come
because of its price…The cost per
transistor has increased in 14nm FinFETs
and will continue to do so, Low said, so an
alternative technology such as 28nm SOI
is necessary.”*
*http://www.eetimes.com/document.asp?doc_id=1326369

Conclusions:
 Dimensional Scaling (“Moore’s Law”) is already exhibiting diminishing
returns
 The path beyond 2017 (7nm) is unclear
 While the research community is working on many interesting new
technologies (see below), none of them seem mature enough to replace
silicon for 2019
- Carbon nanotube - Indium gallium arsenide - 2D (MoS2, etc.) transistors
- Graphene - Spintronics
- Nanowire - Molecular computing
- Photonics - Quantum computing
 3D IC is considered, by all, as the near-term solution, Monolithic 3D IC is
well positioned to be so, as it uses the existing infrastructure!
 It is safe to state that Monolithic 3D is the only alternative that could be
ready for high volume in 2019 !!

11
MONOLITHIC
10,000x the Vertical Connectivity of TSV

12
 Processing on top of copper interconnects should not make the
copper interconnect exceed 400oC
 How to bring mono-crystallized silicon on top at less than 400oC
 How to fabricate state-of-the-art transistors on top of copper interconnect and keep
the interconnect below at less than 400oC
 Misalignment of pre-processed wafer to wafer bonding step used to
be ~1µm
 How to achieve 100nm or better connection pitch
 How to fabricate thin enough layer for inter-layer vias of ~50nm
The Monolithic 3D Challenge
Why is it not already in wide use?

MonolithIC 3D – Innovative Flows
 RCAT (2009) – Process the high temperature on generic structures prior
to ‘smart-cut’, and finish with cold processes – Etch & Depositions
 Gate Replacement (2010) (=Gate Last, HKMG) - Process the high
temperature on repeating structures prior to ‘smart-cut’, and finish with
‘gate replacement’, cold processes – Etch & Depositions
 Laser Annealing (2012) – Use short laser pulse to locally heat and
anneal the top layer while protecting the interconnection layers below
from the top heat
Game Change, using existing transistor process !
 Modified ELTRAN (2015) – Use ELTRAN for low cost, No
defects, Existing transistor flow
 Precise Bonder (2014) – Use new precise bonders, offering
low cost flow with minimal R&D

ELTRAN® - Epitaxial Layer TRANsfer
Originated, developed and produced at Canon Inc.

ELTRAN® - Epitaxial Layer TRANsfer

M3D Leveraging the ELTRAN Idea
 Both donor and carrier wafer could be pre-processed
Donor wafer:
Carrier wafer:
 No impact on processed layer or on device processing
 Donor and Carrier could be easily recycled – reused
 Minimal incremental cost per layer (porous + epi <$20)
porous ‘cut’ layer
epi. layer
Base wafer - reused
porous ‘cut’ layer
oxide layer
Base wafer - reused

17
~700 µm
Donor Wafer
Use standard flow to process “Stratum 3”
- using ELTRAN donor wafer (through silicidation)
MonolithIC 3D Inc. Patents Pending
Stratum 3
porous layer
PMOSNMOS
Silicon
Poly
Oxide
STI
epi

18
~700µm Donor Wafer
Silicon
Bond to a ELTRAN carrier-wafer
~700µm Carrier Wafer
STI
oxide to
oxide
bond
porous layer

19
~700µm Donor Wafer
‘Cut’ Donor Wafer off
~700µm Carrier Wafer
Transferred ~100nm Layer
- Stratum 3
Silicon
Silicon
STI

20
Etch Off the Porous Silicon and Smooth
~700µm
Carrier Wafer
~100nm STI
Silicon
Oxide
porous layer

21
Use standard flow to process “Stratum 2”
Note: High Temperature is OK
~100nm Layer
~700µm
Carrier Wafer
Silicon
Porous ‘cut’ layer
STI
High Performance
Transistors Oxide
Stratum 2
Stratum 3
Need to set
vertical isolation

22
Add at least one interconnect layer
~700µm
Carrier Wafer
~100nm
Transferred Layer
Stratum-2 copper
interconnection layers
Stratum 2
Stratum 3
For some applications such as
Image Sensor, this could be it !

MonolithIC 3D Inc. Patents Pending 23
Transfer onto Final carrier
~700µm
Carrier Wafer
Oxide-oxide bond
Transferred
Layer (Stratum 2
+Stratum 3)
Final Carrier
porous
‘cut layer

Remove carrier-wafer
Oxide-oxide bond
Transferred
Layer (Stratum 2
+Stratum 3)
Final Carrier

Add Stratum-3 Interconnections
Oxide-oxide bond
Transferred
Layer (Stratum 2
+Stratum 3)
Final Carrier

Precise Bonder – Multi-Strata M3D
Utilizing the existing front-end process !!!
<200 nm (3σ)
 Achieving 10,000x vertical connectivity as the upper
strata will be thinner than 100 nm
Mix – Sequential/Parallel M3D
Low manufacturing costs

Transfer onto Pre-Processed Wafer
~700µm
Carrier Wafer
Oxide-oxide bond
Transferred
Layer (Stratum 2
+Stratum 3)
Base Wafer
PMOSNMOS

Remove Carrier Wafer
Oxide-oxide bond
Transferred
Layer (Stratum 2
+Stratum 3)
Base Wafer
PMOSNMOS

Connect to Stratum 1
Oxide-oxide bond
Transferred
Layer (Stratum 2
+Stratum 3)
Base Wafer
PMOSNMOS

Add Metal Layers
Oxide-oxide bond
Transferred
Layer (Stratum 2
+Stratum 3)
Base Wafer
PMOSNMOS

Monolithic 3D using ELTRAN &
Precise Bonder
 Utilizes existing transistor process
 Could help upgrade any fab (leading or trailing)
 Very competitive cost structure
 Better power, performance, price than a node of
scaling at a fraction of the costs !!!
 Allows functionality that could not be attained by
2D devices

The Operational Thermal Challenge
 Upper tier transistors are fully surrounded by oxide and
have no thermal path to remove operational heat
Good Heat Conduction
~100 W/mK
Poor Heat Conduction
~1 W/mK

The Solution
 Use Power Delivery (Vdd, Vss) Network (“PDN”)
also for heat removal
 Add heat spreader to smooth out hot spots
 Add thermally conducting yet electrically non-
conducting contacts to problem areas such as
transmission gates

Cooling Three-Dimensional Integrated Circuits
using
Power Delivery Networks (PDNs)
Hai Wei, Tony Wu, Deepak Sekar*, Brian
Cronquist*, Roger Fabian Pease, Subhasish Mitra
Stanford University, Monolithic 3D Inc.*
3
IEDM 2012 Paper

Monolithic 3D Heat Removal Architecture
(Achievable with Monolithic 3D vertical interconnect density)
 Global power grid shared among multiple
device layers, local power grid for each
device layer
 Local VDD grid architecture shown above
 Optimize all cells in library to have low
thermal resistance to VDD/VSS lines (local
heat sink)
px
py
Patented and Patent Pending Technology
20
60
100
140
0 10 20 30 40
Temperature(ºC)
× 100 TSVs /mm2
Monolithic 3D IC
Without Power Grid
With Power Grid
Signal
wire
Heat sink

1. Reduction die size and power – doubling transistor count -
Extending Moore’s law
Monolithic 3D is far more than just an alternative to 0.7x scaling !!!
2. Significant advantages from using the same fab, design tools
3. Heterogeneous Integration
4. Multiple layers Processed Simultaneously - Huge cost reduction (Nx)
5. Logic redundancy => 100x integration made possible
6. 3D FPGA prototype, 2D volume
7. Enables Modular Design
8. Naturally upper layers are SOI
9. Local Interconnect above and below transistor layer
10. Re-Buffering global interconnect by upper strata
11. Others
A. Image sensor with pixel electronics
B. Micro-display
The Monolithic 3D Advantage

Reduction of Die Size & Power – Doubling Transistor Count
Extending Moore’s law
 Reduction of Die Size & Power
IntSim v2.0 free open source >600 downloads
 Repeater count increases exponentially with scaling
 At 45nm, repeaters >50% of total leakage power of chip [IBM].
 Future chip power, area could be dominated by interconnect
repeaters [Saxena P., et al. (Intel), TCAD, 2004]

Only Monolithic 3D (TSV size ~0.1 µm) would
Provide an Alternative to Dimensional Scaling
*IEEE IITC11 Kim

IV. Heterogeneous Integration
 Logic, Memories, I/O on different strata
 Optimized process and transistors for the function
 Optimizes the number of metal layers
 Optimizes the litho. (spacers, older node)
 Low power, high speed (sequential, combinatorial)
 Different crystals – E/O

V. Multiple Layers Processed Simultaneously
- Huge Cost Reduction (Nx) –”BICS”
 Multiple thin layers can be process simultaneously,
forming transistors on multiple layers
 Cost reduction correlates with number of layers being
simultaneously processed (2, 4, 8, 16, 32, 64, 128, ...)

3D DRAM 3.3x Cost Advantage vs. 2D DRAM
Conventional stacked
capacitor DRAM
Monolithic 3D DRAM with
4 memory layers
Cell size 6F2 Since non self-aligned, 7.2F2
Density x 3.3x
Number of litho steps 26
(with 3 stacked cap. masks)
~26
extra masks for memory layers, but no
stacked cap. masks)

VI. Logic Redundancy => 100x Integration
Made Possible
 It is well known the more we can integrate on one chip with
reasonable yield, the better the cost & performance – Moore’s Law
 Yield is the dominating criterion when to use PCB rather than on-chip
integration

Innovation Enabling ‘Wafer Scale Integration’
– 99.99% Yield with 3D Redundancy
 Swap at logic cone granularity
 Negligible design and power penalty
 Redundant 1 above, no performance penalty
Gene Amdahl -“Wafer
scale integration will only
work with 99.99% yield,
which won’t happen for
100 years” (Source: Wikipedia)
Server-Farm in a Box
Watson in a Smart Phone
…

FPGA Achilles’ Heel – PIC (Programmable Interconnect)
>30x Area vs. Antifuse/Masked Via
Average area ratio of connectivity element >30
Current FPGAs use
primarily pass
transistors with a driver.
Via
Pitch - 0.2 
.2 x .2= 0.04 2
Area: 0.04 2
SRAM FPGA connectivity
elements @ 45 nm
Via connectivity element
@ 45 nm
.2
SRAM
bit
SRAM
bit
SRAM
bit
SRAM
bit
Bidi buffer
Area  4 2
Ratio to AF  100
TS buffer
Area  2 2
Ratio to AF  50
Pass gate
Area  .5 2
Ratio to AF  12
4X
10X
4X
4X
.2
Via/AF

The Twin -
Field-programmable & via-configurable fabric
Prototype Phase Production Phase
• Prototype volumes
• Prototype costs
• Std. logic w/mono-3D
• OTP till design &
functions stabilized
• Specific foundry
• Production volumes
• Production costs
• Standard logic process
• 1-Mask customization
• Backup-foundry capable
Anti-fuses
HV Programming
TransistorsVp

VII. Enables Modular Design
 Platform-based design could evolve to:
 Few layers of generic functions like compute, radios, and one
layer of custom design
 Few layers of logic and memories and one layer of FPGA
 ...

VIII. Naturally Upper Layers are SOI
 SOI wafers provides many benefits with one major
drawback: cost of the blank wafer.
 In monolithic 3D – all the upper strata are naturally SOI

IX. Local Interconnect - Above and
Below Transistor Layer
 Increased complexity requires increased connectivity.
Adding more metal layer increases the challenge of
connecting upper layers to the transistor layer below.
Intel March, 2013

X. Re-Buffering Global Interconnect by
Upper Strata
 Global interconnect is done at the upper and thicker
metal layers. It would increase efficiency if these layers
could re-buffer instead of connecting to base layer using
multiple vias and blocking multiple metal tracks.
Use the layers above for re-buffering.

XI. Others
A. Image Sensor with Pixel Electronics
 With rich vertical connectivity, every pixel of an image
sensor could have its own pixel electronics underneath

XI. Others
B. Micro-display
 Use of three crystal layers to form RGB LED arrays with
drive electronics underneath

Current Status
 70 Fundamental Patents have been Granted
67 Fundamental Patents have already been issued
 >100 Applications have been filed
NuPGA-15 US 8,273,610 was issued Sept 25,2012 (880 pages !)

Monolithic 3D Provides an
Attractive Path to…
3D-CMOS: Monolithic 3D Logic Technology
3D-FPGA: Monolithic 3D Programmable Logic
3D-GateArray: Monolithic 3D Gate Array
3D-Repair: Yield recovery for high-density chips
3D-DRAM: Monolithic 3D DRAM
3D-RRAM: Monolithic 3D RRAM
3D-Flash: Monolithic 3D Flash Memory
3D-Imagers: Monolithic 3D Image Sensor
3D-MicroDisplay: Monolithic 3D Display
3D-LED: Monolithic 3D LED
Monolithic 3D
Integration with Ion-
Cut Technology
Can be applied
to many market
segments
LOGIC
MEMORY
OPTO-
ELECTRONICS

Summary
 We have reached an inflection point
 Multiple practical paths to monolithic 3D exist
 Heat removal of monolithic 3D could be designed in
 Breaking News – The process barriers are now
removed
=> Monolithic 3D – The Most Effective Path for
Future IC Scaling

Smart Alignment
200nm
200nm
Through Layer Via connected
by landing pad of 200x200 nm²

61
‘Smart-Alignment’
Bottom
layer
layout
Landing
pad
Vertical connection
1 for 200nmx200nm
Vertical connection
200nm/metal pitch ~ 20
for 200nmx200nm
 ~20X better vertical connectivity
 Minimum abstraction for routing
‘Smart-Alignment’
Patents Pending

Easiest Monolithic 3D IC

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