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Three Dimensional Silicon
Integration
Presented To:
• Prof. Mohamed Aboudina
Presented By:
• Mohamed Ashraf Atwa
• Mohamed Badr
Content
• Intoduction
• History
• Benefits and challenges
• TSVs
• Wafer Thinning
• References
Definition
• Integrated Circuit manufactured by
stacking silicon wafers and/or dies and
interconnecting them vertically
using Through-Silicon Vias (TSVs).
History
• Moore’s Law:
Why ?!
• Footprint
• Cost
• Heterogeneous
Integration
• Shorter Interconnects
• Power Efficiency
• Design
• Bandwidth
• Noise
TSV (Through Silicon Vias)
• Critical Component
• Joins two separate wafers
• Cylindrical structure composed of copper, aluminum, tungsten or
polysilicon.
• Introduced early 1950s by William Shockley then an exponential
growth by 1990s
• Industrial leaders
• 5 Major to form TSVs
• Mechanical grinding with mesh size #325 then #2000
• About 20% of the TSV fabrication cost
• The BOX acts an etch stop while thinning
• Improves the alignment of layers.
Wafer Thinning
References
• http://www.researchgate.net/publication
• http://www.digitaltrends.com/computing/intel-3d-nand-10tb-solid-
state-drive/#/2

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Three dimensional silicon integration