SPICE LEVEL I/LEVEL II/LEVEL III AND BSIM MODELS SPICE introduction working adaptions detailed discussion on each models SPICE Modeling in BSIM features bulk voltage on large signal model velocity saturation weak inversion operation impact ionization

1. 15E014 - VLSI DESIGN
ASSIGNMENT PRESENTATION
SPICE LEVEL I/LEVEL II/LEVEL III
AND BSIM MODELS
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2. What is SPICE ?
• SPICE (Simulation Program with Integrated Circuit Emphasis) is a
general-purpose, open source analog electronic circuit simulator. It is
a program used in integrated circuit and board-level design to check
the integrity of circuit designs and to predict circuit behavior. It is
used in transistor level design.
• It is obviously impractical to breadboard IC’s before manufacturing.
Again since the cost of manufacturing an IC is pretty high it becomes
an essential thing to make them perfect before manufacturing. That is
where simulation circuits come in. SPICE is one of the oldest and most
popular simulating softwares to do it.
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3. HISTORY
• As with most popular technologies SPICE draws its origin to the wars.
• SPICE1 was mostly based on CANCER(Computer Analysis of Nonlinear
Circuits Excluding Radiation).
• Before SPICE there were other simulating softwares like BIAS,SLIC but
SPICE was robust.
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4. The three levels of spice:
• Level 1:
-developed in 1973
-was originally written in FORTRAN.
-Though rarely used can be used for quick estimates when accuracy is not a concern.
-It used nodal analysis and fixed step transient analysis which were creating problems
and hence an improved version called SPICE level 2 came into picture.
• Level 2:
-was released 2 years later
-was written in FORTRAN as well.
-was capable of doing many things like AC analysis, DC analysis, noise analysis , DC transfer
curve analysis, Transfer function analysis, Transient analysis.
-Analysis at various temperatures was done by automatically updating semiconductor model
parameters for temperature, allowing the circuit to be simulated at temperature extremes.
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-SPICE2 included many semiconductor device compact models: three
levels of MOSFET model, a combined Ebers–Moll and Gummel-Poon
bipolar model, a JFET model, and a model for a junction diode. In
addition, it had many other elements: resistors, capacitors, inductors
(including coupling), independent voltage and current sources, ideal
transmission lines, active components and voltage and current controlled
sources.
• Level 3:
• -was released in 1989.
• -was written in C.
• -more sophisticated MOSFET models.
• -it had a command line feature.

6. BSIM:
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• Commercial and industrial SPICE simulators have added many other
device models as technology advanced and earlier models became
inadequate.
• To attempt standardization of these models so that a set of model
parameters may be used in different simulators, an industry working
group was formed, called the Compact Model Council to choose,
maintain and promote the use of standard models. The BSIM family
of models are some of the standard models .HSpice ,Spectra etc. are
based on these.

7. Adoptions:
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• LTSpice owned by Linear technologies
• TINA owned by TI.
• HSpice owned by Synopsys.
• Power spice owned by IBM.
• TITAN by Infineon.
• MultiSim by National Instruments.

8. How does SPICE work?
For a given circuit, KCL and KVL equations can be written and these
equations can be solved using Matrix math
SPICE does the same thing, except on the front-end it is able to take
the entered circuit and create the KCL/KVL equations for us
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9. Contd…
• This can also be extended to AC analysis since the matrix math can handle Complex
numbers
We can create Bode Plots by sweeping the frequency (i.e., running a simulation at
each frequency)
SPICE can also perform transient simulations by performing numerical integration
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10. • The source file for a SPICE simulation is called a DECK
• The DECK can be thought of as a text net list of the circuit.
• Even when using a graphical entry tool for the schematic, the first thing the tool does when you click “simulate”, is create a
text-based DECK that is plugged into the SPICE engine.
• The first letter of a component instantiation in the DECK tells SPICE what the component is.
devices are then followed by the net names they connect to followed by their parameters
• Example :
• R1 n1 n2 VALUE=75 /* resistor*/
L1 n2 n3 VALUE=1n /* inductor */
C1 n3 n4 VALUE=1p /* capacitor */
V1 n4 n5 DC=1v /* DC voltage source*/
I1 n5 n6 ACmag=1 /* AC current source*/
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11. Level 1 Modelling
“Electrical Parameters”
- there are 5 parameters that fully characterize the base model
- these will have default values in the model based on the fab process
- we can overwrite these from the DECK if we want to perform
sensitivity analysis
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PARAMETER DESCRIPTION
KP k’, transconductance
VTO VT0, zero substrate bias
threshold
GAMMA γ, substrate-bias coefficient
PHI |2F|, surface potential
LAMBDA λ, channel length modulation
coefficient

12. “Physical Parameters”
- there are parameters that describe the shape and material properties of the device
Parameter Description
U0 un, electron mobility
TOX tox, oxide thickness
NSUB NA, doping concentration
LD LD, lateral diffusion
• notice that these parameters are redundant with the Electrical parameters since these quantities
are used to calculate k’, VT0, γ, |2F|, and λ these allow you to get further into the details of the
fabrication to see its effect on performance
• However, the “Electrical Parameters” OVERRIDE the “Physical Parameters”
• this means you wouldn’t supply both if you really want to see the effect of a physical parameters
on the performance of the device.
• You would need to remove the electrical parameter.
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13. “Parasitic Parameters”
- these are the capacitances and resistances of the
material
Parameter Description
CJ CJ0, zero-bias bulk capacitance per area
CJSW CJ0sw, zero-bias sidewall capacitance per
area
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14. Level 1 model
• Level 1 model is also known as SHICHMAN and
HODGES model
• It uses the element listed above and based on
equations into 2 regions
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15. • This model does not include subthreshold conduction or any short
channel effects
• We note that if that device operates at edge of the saturation and
thus the capacitances value varies continously from one region to
another
• Thus level 1 model maintain a reasonable I/V accuracy for channel
length as small as roughly 4μm. But it still predict the output
impedance of transistors in saturation quite poorly
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16. Level 2 SPICE Modeling
Level 2 adds the following behavior to the Level 1 model
1) Variation of the bulk depletion charge
dependence on the channel voltage (we assumed it was
constant in Level 1
2) Variation of electron mobility (un) with the
applied E-field
3) Variation of effective Channel Length in
Saturation model
4) Carrier Velocity Saturation
5) Sub-threshold Conduction
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• We also have the ability to indicate which level we want to use. For
example, you can have a
Level 2 model, but in the initalization you say:
M1 D G S B NMOD (Level=1 L=1U W=10U)
This will tell the simulator to ignore all the parameters associated with
Level 2 or higher accuracy.
We can also put the “Level=1” as the first parameters in the model

18. MOS device level 2 model
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• The level 1 model began to manifest its shortcomings and channel
length fall below app. 4μm
• So these models are developed to represent higher order effects

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• An assumption we made in square law characteristics is the constant
threshold voltage along the channel . This assumption is not correct
even for long channel devices because charge in depletion layer varies
according to the local voltage

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• Performing integration varying threshold voltage yields

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• In level 2 implementation, if λ is not specified it is obtained by
calculating the width of the depletion region b/w pinch off point and
edge of the drain. For depletion region of a pn junction we can write
• The principal difficulty in the above approach is that both the drain
current and derivative are discontinous at the edge of triode region

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• To resolve this issue, ∆L is actually obtained by a “fixed up equation”
• An attribute the o/p conductance of a transistor varies as Vds
increases, an effect not represented by the first order model using a
constant λ
• Thus level 2 model also includes the degradation of the mobility with
vertical field in the channel

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• Level 2 models represents two other short channel phenomenon :
variation of Vth and L & velocity saturation
• Finally level 2 models provide a reasonable I/V accuracy for wide,
short devices in saturation with L≈0.7μm but it suffers from
substantial errors in representing the op impedance & transition
points in between saturation and triode regions.
• For narrow or long devices the model is quite inaccurate

24. SPICE Modeling (Level 3)
Level 3 was developed to specifically address small geometry
effects.
- instead of trying to come up with an expression for each and
every bump and wiggle on the IV curve, Level 3 instead moves
toward a more empirical approach.
- curve-fitting parameters are added to the IV equations from Level
1 and Level 2.
- these parameters are dialed-in based on measurement data from
a test run of transistors.
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25. SPICE Modeling in BSIM
• Berkeley Short-Channel IGFET Model
• This is the most commonly used model for accurate simulations.
• This is a totally empirical model which reduces the curve fitting
parameters
• This actually reduces simulation time over the Level 3 models.
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26. BSIM series
• In the previous models (level 1-3)the device behaviour is expressed by
means of equation that originated from physical operation.
• But nowadays the transistors are scaled to submicron levels, so
became difficult to introduce physical equations that is both accurate
and computationally efficient.
• It uses numerical empirical parameters so as to simplify the equations
by compromising with actual device operations
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27. Feature of BSIM
• It uses a simple equation to represent the geometry dependence of
many of the device parameters.
• The general expression is,
𝑃 = 𝑃0 −
𝛼 𝑃
𝐿 𝑒 𝑓𝑓
−
𝛽 𝑃
𝑤𝑒 𝑓𝑓
Where P0 is value of the parameter for a long wide transistor
(P=P0 when Leff & Weff  inf) 𝛼p & 𝛽 𝑃 are fitting factors
µ = µ0 −
𝛼µ
𝐿 𝑒 𝑓𝑓
−
𝛽µ
𝑤𝑒 𝑓𝑓
• But this formulation becomes less accurate at small dimensions
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28. BSIM Model Features
• channel length modulation
• carrier velocity saturation
• drain-induced barrier lowering
• Substrate current flow
• non-uniform doping profile for ion-implanted devices
• subthreshold conduction
• geometric dependence of electrical parameters
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33. Results
• On a 0.7 µm technology indicates that BSIM avoids gross errors in the
I/V characteristics for various device dimensions, but its accuracy for
short, narrow transistors is poor(i.e. channel length below 0.8 µm).
• Eg. At large VDS BSIM predicts negative output resistance for saturated
mosfets
• In triode mode it exhibits slight discontinuties in drain current
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34. BSIM 2
• It requires 70 parameters & employs new expression for mobility,
drain current and subthreshold conduction.
• It also represents the o/p impedence more accurately by
incorporating channel length modulation and drain induced barrier
lowering.
• Overall accuracy is marginally higher than BSIM
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35. Trends in BSIM1 and BSIM
• Expressing the device behaviour by means of empirical equations only
posses a little relationship with physical phenomena, eventually
created difficulties in modelling short channel devices
• Also parameter extraction, modelling process variations, and need for
extensive use of polynomials made generation and application of
these model quite difficult
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36. BSIM 3
• BSIM3 uses both physical principles of device operation while
maintaining most of the features of its previous versions.
• It utilizes about 180 parameters
• For channel lengths as low as 0.25µm this model provides reasonable
accuracy for subthreshold and strong inversion operation.
• But it still suffers from large errors in predicting the output
impedance.
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37. Other models
• HSPICE Level 28
• Mos9 and
• EKV- EnzKrummenacher-Vittoz
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38. Reference
• Behzad Razavi-Design of Analog CMOS Integrated Circuits-McGraw
Hill Higher Education (2003)
• Wikipedia
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Thank you!!!