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Analog vlsi


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Analog vlsi

  1. 1. Analog VLSI Design Nguyen Cao Qui
  2. 2. Introduction to the course <ul><li>Name: “ Analog VLSI Design ” </li></ul><ul><li>Instructor: Nguyen Cao Qui </li></ul><ul><li> email: [email_address] </li></ul><ul><li>Goals: </li></ul><ul><li>The goal of this course is to introduce the principles of operation, design and technology of Analog Integrated Circuits to Electrical Engineering students at Senior level. VLSI technology and analog integrated circuit design is covered with an emphasis on CMOS Technology. CMOS layout design and analog simulation tools (Microwind) are demonstrated and used. Students will do a design project and final exam at the end. </li></ul>
  3. 3. Introduction to the course <ul><li>Number of credits : 3 </li></ul><ul><li>(1: theory ; 2: homework + project +Seminar) </li></ul><ul><li>Textbooks: </li></ul><ul><li>“ CMOS: Circuit Design, Layout, and Simulation” </li></ul><ul><li>R. Jacob Baker </li></ul><ul><li>Other Books: </li></ul><ul><li>&quot;CMOS Analog Circuit Design&quot; </li></ul><ul><li>Phillip E. Allen and Douglas R. Holdberg </li></ul>
  4. 4. Introduction to the course <ul><li>Course Policies: </li></ul><ul><li>* Homework + Project : 40% </li></ul><ul><li>* Final Test :60% </li></ul>C onversion 10 ‘ Scale ABCB 0.0 F 4.0 D 4.5 D+ 5.0 C 6.0 C+ 7.0 B 7.8 B+ 8.5 A
  5. 5. CONTENTS <ul><li>Chapter 1: Introduction to CMOS Design </li></ul><ul><li>Chapter 2: The Well </li></ul><ul><li>Chapter 3: The Metal Layers </li></ul><ul><li>Chapter 4: The Active and Poly Layers </li></ul><ul><li>Chapter 5: CAD Tools (Microwind) </li></ul><ul><li>Chapter 6: Resistors, Capacitors, MOSFETs </li></ul><ul><li>Chapter 7: Models for Analog Design (IC Course) </li></ul><ul><li>Chapter 8: The Inverter (IC Course) </li></ul><ul><li>Chapter 9: VLSI Layout Examples </li></ul><ul><li>Chapter 10: Current Mirrors </li></ul><ul><li>Chapter 11: Amplifiers </li></ul><ul><li>Chapter 12: Differential Amplifiers </li></ul><ul><li>Chapter 13: Operational Amplifiers I </li></ul><ul><li>Chapter 14: Voltage References </li></ul><ul><li>Chapter 15: Data Converter Fundamentals (ADC) </li></ul><ul><li>Chapter 16: Data Converter Fundamentals (DAC) </li></ul>
  6. 6. Chapter 1 Introduction to CMOS Design <ul><li>CMOS (complementary metal oxide semiconductor) </li></ul><ul><li>CMOS is used in most very large scale integrated (VLSI) or ultra-large scale integrated (ULSI) </li></ul><ul><li>&quot;VLSI&quot; : chips containing thousands </li></ul><ul><li>or millions of MOSFETs. </li></ul><ul><li>&quot;ULSI&quot; : containing billions, or more, MOSFETs. </li></ul><ul><li>We focus simply on analog CMOS circuit design </li></ul>
  7. 7. Introduction to CMOS Design <ul><li>1. The CMOS IC Design Process </li></ul>
  8. 9. The CMOS IC Design Process <ul><li>1.1 Fabrication </li></ul><ul><li>CMOS integrated circuits are fabricated silicon wafers. </li></ul><ul><li>Each wafer contains chips or &quot;die&quot; </li></ul><ul><li>The most common wafer size is 300 mm </li></ul>
  9. 13. 2. CMOS Background <ul><li>CMOS circuit design was invented in 1963 by Frank Wanlass </li></ul><ul><li>Circuit could be made with discrete complementary MOS devices, an NMOS and a PMOS </li></ul>NMOS PMOS
  10. 14. 2. CMOS Background <ul><li>* Ex: CMOS Inverter </li></ul>
  11. 15. 2. CMOS Background <ul><li>Advantages of CMOS: </li></ul><ul><li>Low power </li></ul><ul><li>Layout on small area </li></ul><ul><li>Can be fabricated with few defects and low cost. </li></ul>95% of ICs are fabricated in CMOS
  12. 16. 3. Technology Scale Down <ul><li>* The Moore’s Law : Doubling every 18 months </li></ul>
  13. 17. 3. Technology Scale Down
  14. 18. Chapter 2: The Well <ul><li>* Studying the well to: </li></ul><ul><li>Understanding CMOS integrated circuit layout and design. </li></ul><ul><li>Understanding the performance limitations and parasitics. </li></ul><ul><li>Understanding the details of each fabrication (layout) layer. </li></ul>
  15. 19. Chapter 2: The Well <ul><li>* The Substrate (The Unprocessed Wafer) </li></ul><ul><li>CMOS circuits are fabricated on and in a silicon wafer </li></ul><ul><li>N-type wafer: doping with donor atoms, exp: phosphorus </li></ul><ul><li>P-type wafer: doping with acceptor atoms, exp: boron </li></ul><ul><li>P-type wafer: the most common substrate used </li></ul><ul><li>NMOS are fabricated directly in the p-type wafer </li></ul><ul><li>PMOS are fabricated in an &quot;n-well.&quot; </li></ul>
  16. 20. Chapter 2: The Well <ul><li>* A Parasitic Diode </li></ul>
  17. 21. Chapter 2: The Well <ul><li>* Using the N-well as a Resistor </li></ul>
  18. 22. 2.1 Patterning <ul><li>CMOS integrated circuits are formed by patterning different layers on and in the silicon wafer. </li></ul>
  19. 23. 2.1 Patterning
  20. 24. 2.1 Patterning
  21. 25. 2.1.1 Patterning the N-well
  22. 26. 2.2 Laying Out the N-well
  23. 27. 2.2.1 Design Rules for the N-well
  24. 28. 2.3 Resistance Calculation
  25. 29. 2.3 Resistance Calculation
  26. 30. 2.3 Resistance Calculation <ul><li>* Layout of Corners </li></ul>
  27. 31. 2.4. PN Junction Physics - Capacitance
  28. 32. 2.4. PN Junction Physics - Capacitance
  29. 33. 2.5. Design Rules for the Well
  30. 34. Chapter 3: The Metal Layers <ul><li>The metal layers: connect circuit elements (MOSFETs, capacitors, and resistors). </li></ul><ul><li>There are several metal layers when layout </li></ul><ul><li>These levels of metal are named metal1 (M1), metal2 (M2)… </li></ul>
  31. 35. 3.1 The Bonding Pad <ul><li>The interface between the die and the package </li></ul>
  32. 36. 3.1.1 Laying Out the Pad
  33. 37. Capacitance of Metal-to-Substrate
  34. 38. Insulator - Overglass layer
  35. 39. 3.2 Design and Layout Using the Metal Layers <ul><li>3.2.1 Metal1 and Via1 </li></ul>
  36. 40. An Example Layout
  37. 41. 3.2.2 Parasitics Associated with the Metal Layers
  38. 42. Intrinsic Propagation Delay <ul><li>The velocity </li></ul>The delay of the metal line Where
  39. 43. 3.2.3 Design Rules for the Metal Layers
  40. 44. A Layout Trick for the Metal Layers
  41. 45. 3.2.4 Contact Resistance
  42. 46. 3.4 Layout Examples
  43. 47. 3.4 Layout Examples
  44. 48. 3.4 Layout Examples
  45. 49. 3.4 Layout Examples
  46. 50. 3.4 Layout Examples
  47. 51. Chapter 4: The Active and Poly Layers <ul><li>The active, n-select, p-select, and poly: form n-channel and p-channel MOSFETs. </li></ul><ul><li>Metal layers can make an contact to the substrate or well. </li></ul><ul><li>The n-select layers indicate where to implant n-type. </li></ul><ul><li>The p-select layers indicate where to implant p-type. </li></ul>
  48. 52. Chapter 4: The Active and Poly Layers <ul><li>The active defines an opening in the oxide. </li></ul><ul><li>The active and select layers are always used together. </li></ul><ul><li>The poly layer forms the gate of the MOSFETs. </li></ul><ul><li>Poly is a short name for polysilicon. </li></ul>
  49. 53. 4.1 Layout using the Active and Poly Layers <ul><li>The Active Layer </li></ul>
  50. 54. The P- and N-Select Layers
  51. 55. The P- and N-Select Layers
  52. 56. The Poly Layer <ul><li>The poly layer is used for MOSFET formation. </li></ul><ul><li>The gate of the MOSFET is formed with the polysilicon. </li></ul><ul><li>The source and drain of the MOSFET are formed with the n+ implant. </li></ul>
  53. 57. Layout and cross-sectional views of a MOSFET.
  54. 58. Layout and cross-sectional views of a MOSFET.
  55. 59. Layout and cross-sectional views of a MOSFET.
  56. 60. The Poly Wire <ul><li>The poly layer can also be used, as a wire. </li></ul><ul><li>Poly is routed on top of the FOX. </li></ul><ul><li>The main limitation when using the poly layer for interconnection is its sheet resistance. </li></ul><ul><li>The sheet resistance of the metal layers is approximately 0.1 Ohm/square ; The poly layer: 200 Q/square . </li></ul><ul><li>The delay through a poly line can be considerably longer than a metal line. </li></ul>
  57. 61. The Poly Wire
  58. 62. 4.1.1 Process Flow
  59. 63. 4.1.1 Process Flow
  60. 64. 4.2 Connecting Wires to Poly and Active
  61. 65. 4.2 Connecting Wires to Poly and Active
  62. 66. Connecting the P-Substrate to Ground
  63. 67. Layout of an N-Well Resistor
  64. 68. Layout of an NMOS Device
  65. 69. Layout of a PMOS Device
  66. 70. Design Rules
  67. 71. Design Rules