Vlsi giet


Published on

GIET, Satya Prakash Das, VLSI PPT

Published in: Education, Business, Technology
  • Be the first to comment

  • Be the first to like this

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide
  • Datapath is the “computational unit” of a processor Digital Signal Processing (DSP) chips are used all over the place: audio, image processing, satellite applications, etc. Memory performance always behind CPU speed, greater need for more capacity, bandwidth Network processors: low-cost, versatile, fast designs needed for the increasing internet applications, protocols, etc.
  • introduced in 1971 versus 8086 introduced in 1978 1 MHz clock rate 10 MHz clock rate 5volt VDD (?) 5volt VDD 10 micron (?) 3 micron 5K transistors (?) 29K transistors
  • P5 introduced in 1994 versus P6 (Pentium Pro) in 1996 75 to 100 MHz clock rate 150 to 200 MHz clock rate 91 mm**2 196 mm**2 3.3M transistors 5.5M transistors (1M in cache) (external cache) 0.35 micron 0.35 micron 4 layers metal 4 layers metal 3.3volt VDD 3.3volt VDD >20W typical power dissipation 387 pins
  • Vlsi giet

    1. 1. VLSI
    2. 2. • What is VLSI? – “Very Large Scale Integration”• Single Transistor-----------------------------1958• SSI – Small-Scale Integration (0-102)---1960• MSI – Medium-Scale Integration (102-103)---1967• LSI – Large-Scale Integration (103-105)---1972• VLSI – Very Large-Scale Integration (105-107)---1978• ULSI – Ultra Large-Scale Integration (>=107)---1989• GSI _ Giant Scale Integration (>=109)---2000*Where these are given as no of transistors.
    3. 3. ENIAC - The first electronic computer (1946)Digital Integrated Circuits Introduction © Prentice Hall 1995
    4. 4. Integration Level Trends Obligatory historical Moore’s law plot
    5. 5. Example: Intel Processor SizesSilicon Process 1.5µ 1.0µ 0.8µ 0.6µ 0.35µ 0.25µTechnology Intel386TM DX Processor Intel486TM DX Processor Pentium® Processor Pentium® Pro & Pentium® II Processors Source: http://www.intel.com/
    6. 6. Why monolithic Integration?•Less area/volume, compact size•Less power consumption•Less testing requirement at sys level•Higher reliability, due to improved on chipinterconnects & elimination of solderedjoints.•Higher speed, reduced int length & abs ofparasitic capacitance.•Less cost and easy to handle
    7. 7. IC Products• Processors – CPU, DSP, Controllers• Memory chips – RAM, ROM, EEPROM• Analog – Mobile communication, audio/video processing• Programmable – PLA, FPGA• Embedded systems – Used in cars, factories – Network cards• System-on-chip (SoC) Images: amazon.com
    8. 8. What is an IC?• It is a miniature, low cost electronic device consisting of active and passive components those are irreparably joined together on a single crystal chip.
    9. 9. What is “CMOS VLSI”?• MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)• Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate. We call this “poly” or just “red stuff” to distinguish it from the body of the chip, the substrate, which is a single crystal of silicon.• We do use metal (aluminum) for interconnection wires on the surface of the chip.
    10. 10. • Integrated Circuits/MEMs Hierarchy of various technology Semiconductor process Silicon GaAsBipolar Unipolar Bipolar Unipolar ECL NMOS PMOS CMOS TTL
    11. 11. • Selection of processing technology is a trade off among Operating speed, Chip area, Power dissipation.• 1980------2mic.m tech-------64Kb per chip• 1990------.5---------------------16Mb• 1995------.25--------------------256Mb• 2000------.18--------------------1Gb• 2005------.15--------------------4Gb• 2010------.08---------------------64Gb
    12. 12. VLSI Design Methodology• Full custom Design style• Semi custom Design style• Frontend Designer• Backend Designer
    13. 13. VLSI design flow--Y chart (D.GJASKI)
    14. 14. Top-down & bottom-up approach SYSTEM MODULE + GATE CIRCUIT DEVICE G S D n+ n+Digital Integrated Circuits Introduction © Prentice Hall 1995
    15. 15. FLOW CHART FOR VLSI DESIGN FLOW Functional design Fun verification Logic design Logic verification Ckt design Ckt verification
    16. 16. Layout designLayout verification Fabrication & Testing
    17. 17. Chips• Integrated circuits consist of: – A small square or rectangular “die”, < 1mm thick • Small die: 1.5 mm x 1.5 mm => 2.25 mm 2 • Large die: 15 mm x 15 mm => 225 mm 2 – Larger die sizes mean: • More logic, memory • Less volume • Less yield – Dies are made from silicon (substrate) • Substrate provides mechanical support and electrical common point
    18. 18. Advancements over the years• © Intel 4004 • © Intel P4 Processor Processor• Introduced in • Introduced in 2000 1971 • 40 Million• 2300 Transistors Transistors• 108 KHz Clock • 1.5GHz Clock
    19. 19. Intel 4004 Microprocessor
    20. 20. Intel Pentium (IV) Microprocessor
    21. 21. System Design Pyramid
    22. 22. Photolithography and Patterning• Photo-litho-graphy: latin: light-stone-writing• Photolithography: an optical means for transferring patternsonto a substrate.• Patterns are first transferred to a photoresist layer.•Typically a wafer is about 8-10 inches in diameter.Individual ICs are placed inside it.
    23. 23. Photoresist is a liquid film that is spread out onto asubstrate, exposed with a desired pattern, anddeveloped into a selectively placed layer for subsequentprocessing.• Photolithography is a binary pattern transfer: there isno gray-scale, color, nor depth to the image.
    24. 24. Steps• Photo resist Coating (covering)A light sensitive organic polymer (plastic)• Mask/ Reticle formation• Exposure to light (UV/X-RAY/E-BEAM)
    25. 25. WHAT IS A PHOTOMASK?Photomasks are high precision plates containing microscopicimages ofelectronic circuits. Photomasks are made from very flat piecesof quartz or glass with a layer of chrome on one side. Etchedin the chrome is a portion of an electronic circuitdesign. This circuit design on the mask is also calledgeometry.
    26. 26. The ResistThe first step is to coat the Si/SiO2 wafer with a film of alight sensitive material, called a resist. Solvent EvaporatesA resist must also be capable of high fidelity recording of thepattern (resolution) and durable enough to survive laterprocess steps
    27. 27. Photolithography Energy Mask + Aligner Photoresist WaferEnergy - causes (photo)chemical reactions that modify resistdissolution rateMask - blocks energy transmission to some areas of the resistAligner- aligns mask to previously exposed layers of the overall designResist - records the masked pattern of energy
    28. 28. Next Generation LithographyIn 1996, five technology options were proposed for the130 nm gate length technology: •X-ray proximity Lithography (XPL) •Extreme Ultraviolet (EUV) •Electron Projection Lithography (EPL) •Ion Projection Lithography (IPL) •Direct-write lithography (EBDW).These options were referred to as the next generationlithography.
    29. 29. MOSFET Design Rules• Lambda based design Rule• Micron Rule
    30. 30. Minimum width and SpacingLayer ValuePoly 2LActive 3LN select 3LMetal 3L
    31. 31. Stick DiagramsMetal poly ndiff pdiff Can also draw in shades of gray/line style.
    32. 32. • Wiring Tracks• A wiring track is the space required for a wire – 4 λ width, 4 λ spacing from neighbor = 8 λ pitch• Transistors also consume one wiring track
    33. 33. • Well spacing• Wells must surround transistors by 6 λ – Implies 12 λ between opposite transistor flavors – Leaves room for one wire track
    34. 34. Stick Diagrams Basic Circuit Layout VDD VDD X Xx x x x Stick Diagra X m X Gnd Gnd
    35. 35. Stick Diagrams Layout Diagrams VDD VDD X Xx x x x X X Gnd Gnd
    36. 36. Example: Inverter
    37. 37. MOSFET Arrays and AOI Gates A B C x y A B C y x
    38. 38. Parallel Connected MOS Patterning x x A B A B X X X y y
    39. 39. Alternate Layout Strategy x x X XA B A B X X y y
    40. 40. MOSFET Arrays and AOI Gates NAND2 Layout Vp Vp X X X a.bGnd a.b a b X X a b Gnd
    41. 41. NOR2 Layout Vp Vp X X a+ b a a +b a b XGnd X X b Gnd
    42. 42. Stick Diagrams Power A Out C B Ground
    43. 43. Cells, Libraries, and Hierarchical Design• Creation of a Cell Library VDD X Xx X x X x x X X X X X Gnd
    44. 44. VDD X X X Xa xX X a.b X X X X a.b b Gnd
    45. 45. VDD X X X x X a+b a X a +b X X X X bGnd
    46. 46. • Cell Placement• System Hierarchy (MOSFET-Gates-F/Fs- Registers-Networks-Systems)• Floorplans and Interconnect Wiring• Y= (# of Good Chips/Total No)*100%• Y=Yield• ‘Y’ depends on total area=A, and no of defects=D, − AD• Y=e *100%
    47. 47. Interconnects• Place and Route Algorithm.• Wiring Delay• td=kl2• l=length of inter connect. td