1. IC Fabrication and Technologies
Presented by:
Dr. Vasudeva Bevara
Assistant Professor
Department of ECE
10-10-2023 1
2. Outline of IC Fabrication and Technologies
1. IC Fabrication:
• Steps in Fabrication-Oxidation
• Lithography
• Diffusion
• Ion implantation
• Encapsulation and Metallization.
2. IC Technologies
• Review of Enhancement and Depletion MOS transistors,
• NMOS, PMOS & CMOS fabrications
• Comparison of NMOS, CMOS & BiCMOS technologies.
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6. Fabrication Processes
The basic fabrication processes of
the Integrated Circuits
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• Fabrication is the process of constructing
an industrial product. We can also define
it as a set of methods to manufacture an
electronic device or product.
• For example, silicon semiconductor chips,
etc. In the case of metals, fabrication is a
process used to convert the raw materials
into the finished product.
7. Wafer Preparation
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• The wafer preparation is the first step for IC fabrication. It
involves cutting, shaping, and polishing the wafer material
to make it suitable for further fabrication. Some wafers are
modified because of their sharp edges, irregular surface,
and shape to convert them to the required wafer.
• A wafer is a thin material used for making various
Integrated circuits and transistors. Wafer acts as a base for
such devices. The material of a wafer is the semiconductor,
especially crystalline silicon. The silicon crystals used for
the wafer manufacturing are highly pure. The process of
extracting pure metal from the melt is known as a boule.
The impurities are further added to the molten state of
the material in a specific amount to make it n-type or p-
type.
8. Oxidation – Create Oxide Film on Wafer Surface.
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• Oxidation is the process of adding oxygen. In a
semiconductor, the oxygen and the silicon react to
form silicon dioxide. The oxidation is carried out in
furnaces at high temperatures up to 1250 degrees
Celsius. Oxidation is classified as wet oxidation or dry
oxidation. Both processes are widely used and have
their own advantages and disadvantages. Wet
oxidation is fast, while dry oxidation has good
electrical properties.
• Wet oxidation is also known as steam. Both types of
oxidation have excellent electrical insulation
properties. The deposition of silicon dioxide on the
silicon wafer protects from many impurities. The
dopants can be applied only to areas not covered with
the SiO2.
9. Photolithography – Draw Circuit Design on Wafer
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• Next step is to draw a circuit design onto a wafer which is called the photolithography
process. It is also called “photo” for short because it is similar to developing a photo
taken on a film camera with semiconductors.
• A photo mask functions as the film. A photo mask is a glass substrate with a computer
designed circuit pattern.
• In order to draw the circuit on the wafer, the photoresist, a material that responds to
light is applied thinly and evenly on the oxide film previously placed on the wafer.
• Now, when light transfers the patterned photo mask, the circuit is drawn on the wafer
surface. Just like developing a photo, a circuit pattern is imprinted on the wafer by
spraying, developer and removing unlit areas from the areas that are exposed to light.
10. Diffusion
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• Diffusion is a process of adding impurities atoms from a region with high concentration
to a region of low concentration. The dopants or impurity atoms are added to the
silicon (semiconductor material), which changes its resistivity. The process of diffusion is
highly dependent on the temperature. The high doping concentration improves the
conductivity of a metal.
• The dopants can be of any state, solid, liquid, or gas. The preferred dopants are
pentavalent impurities or n-type, such as antimony, phosphorous pentoxide, and arsine
(gas). The trivalent impurities or p-type are gallium, indium, boron, etc.
• The diffusion cannot be used at the later stages. It is because the number of layers
formed at the successive stages of the fabrication process might not be able to resist
such high temperatures.
For example,
• The boron or indium (trivalent impurities) diffusion on the n-type substrate forms a p-n
junction.
• Diffusion is also a part of the process used to fill the lattice gap in the solids.
11. Etching – Remove Unnecessary Materials
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• Now it is time to remove unnecessary
materials from the wafer surface so
that only the design pattern remains.
• This is done using a liquid or gas
etching technique. All unnecessary
materials are selectively removed to
draw the desired design.
• Wet Etching: When chemical solutions are used for etching, it is called wet etching.
• Dry Etching: When gas or plasma is used, it is called dry etching.
12. Deposition and Ion Implementation (Ion implantation)
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• Coating the thin film at a desired molecular or atomic level onto a wafer is called
deposition. Since the coating is so thin, precise and sophisticated technology is
required to uniformly apply the thin film on a wafer to give the semiconductor
electrical characteristics. Ion implementation / Ion implantation is also required.
• A semiconductor made of silicon does not conduct electricity but adding impurities. It
conducts current and has conductive properties.
13. Encapsulation
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• The “encapsulation process”, which encapsulates packages, is a step where a semiconductor
chip is wrapped with a certain material to protect it from the external environment.
• It is also a step that reveals the characteristics of “light, thin, short, and small”, which
packages aim for.
14. Metallization(Metal Wiring)
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• Metallization is also used to interconnect various components that form an Integrated
circuit. The components can be resistors, capacitors, transistors, relays, etc. The metal layer
is first deposited on the surface of the silicon wafer, as discussed above. After that, the
required pattern or area for interconnected is etched.
• Metallization is defined as the process of
coating a metal layer on the metallic
surface or non-metallic surface. The
coating can be of aluminum, zinc, or
silver. The metal coating in CMOS
fabrication is aluminum, which protects
the surface from external environmental
factors, as dust, air, water, etc.
15. Packaging
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• This is the last process, the packaging process. The wafer completed through the previous
steps are cut into individual semiconductor chips that can be loaded on an electronic
semiconductor device.
• An individual chip must have a path to exchange electrical signals with the outside and
have a form to protect it from various external elements.
• The wafer is cut into individual chips and the diced or saw chips are placed on the PCB
board.
• In the bonding step, the contact point of the semiconductor chip placed on a substrate is
connected with the contact point of the substrate. Then molding finishes the chip package
to its desired shape.
• After final test, sealing and labeling the product name, the semiconductor chip we
commonly see is completed.
17. MOSFETs
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• MOSFETs have characteristics similar to JFETs and additional characteristics that make
them very useful.
• There are 2 types:
1. Depletion-Type MOSFET
2. Enhancement-Type MOSFET
18. Depletion-Type MOSFET Construction
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• The Drain (D) and Source (S) connect to the to
n-doped regions. These N-doped regions are
connected via an n-channel.
• This n-channel is connected to the Gate (G) via
a thin insulating layer of SiO2.
• The n-doped material lies on a p-doped
substrate that may have an additional terminal
connection called SS.
21. Enhancement-Type MOSFET Construction
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• The Drain (D) and Source (S) connect to the to n-
doped regions. These n-doped regions are
connected via an n-channel.
• The Gate (G) connects to the p-doped substrate via
a thin insulating layer of SiO2. There is no channel.
• The n-doped material lies on a p-doped substrate
that may have an additional terminal connection
called SS.
22. Basic Operation and Characteristics
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• If VGS is set at 0 V and a voltage applied between the drain and source of the device, the absence of an n-
channel (with its generous number of free carriers) will result in a current of effectively zero amperes—
quite different from the depletion- type MOSFET and JFET where ID = IDSS.
• It is not sufficient to have a large accumulation of carriers (electrons) at the drain and source (due to the
n-doped regions) if a path fails to exist between the two.
• If both VDS and VGS is set at some positive voltage greater than 0 V, then the positive potential at the gate
will pressure the holes (since like charges repel) in the p-substrate along the edge of the SiO2 layer to
leave the area and enter deeper regions of the p- substrate.
• However, the electrons in the p-substrate (the minority carriers of the material) will be attracted to the
positive gate and accumulate in the region near the surface of the SiO2 layer. The SiO2 layer and its
insulating qualities will prevent the negative carriers from being absorbed at the gate terminal.
23. Continued…
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• As VGS increases in magnitude, the concentration of
electrons near the SiO2 surface increases until
eventually the induced n-type region can support a
measurable flow between drain and source. The level of
VGS that results in the significant increase in drain
current is called the threshold voltage and is given the
symbol VT.
• Since the channel is non existent with VGS=0 V and
“enhanced” by the application of a positive gate-to-
source
• voltage, this type of MOSFET is called an enhancement-
type MOSFET.
24. Continued…
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• As VGS is increased beyond the threshold level, the density of free carriers in the
induced channel will increase, resulting in an increased level of drain current.
• However, if we hold VGS constant and increase the level of VDS, the drain current will
eventually reach a saturation level The levelling off of ID is due to a pinching-off process
depicted by the narrower channel at the drain end of the induced channel
• By applying KVL we get -
• If VGS is held fixed at some value such as 8 V and VDS is increased from 2 to 5V, the
voltage will drop from -6 to -3 V. This reduction in gate-to-drain voltage will in turn
reduce the attractive forces for free carriers (electrons) in this region of the induced
channel, causing a reduction in the effective channel width.
• Eventually, the channel will be reduced to the point of pinch-off and a saturation
condition will be established.
27. Transistors as Switches
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• We can view MOS transistors as electrically controlled switches
• Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF
49. CMOS Fabrication
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• CMOS transistors are fabricated on silicon wafer
• Lithography process similar to printing press
• On each step, different materials are deposited or etched
• Easiest to understand by viewing both top and cross-section of wafer
in a simplified manufacturing process
50. Inverter Cross-section
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• Typically use p-type substrate for nMOS transistors
• Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
51. Well and Substrate Taps
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• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor connection called
Shottky Diode
• Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
Y
GND VDD
n+
p+
substrate tap well tap
n+ p+
52. Inverter Mask Set
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• Transistors and wires are defined by masks
• Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
53. Detailed Mask Views
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• Six masks
• n-well
• Polysilicon
• n+ diffusion
• p+ diffusion
• Contact
• Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
54. Fabrication Steps
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• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
• Cover wafer with protective layer of SiO2 (oxide)
• Remove layer where n-well should be built
• Implant or diffuse n dopants into exposed wafer
• Strip off SiO2
p substrate
56. Photoresist
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• Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light
p substrate
SiO2
Photoresist
58. Etch
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• Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist
59. Strip Photoresist
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• Strip off remaining photoresist
• Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step
p substrate
SiO2
60. n-well
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• n-well is formed with diffusion or ion implantation
• Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
• Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si
n well
SiO2
61. Strip Oxide
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• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps
p substrate
n well
62. Polysilicon
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• Deposit very thin layer of gate oxide
• < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substrate
n well
64. Self-Aligned Process
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• Use oxide and masking to expose where n+ dopants should be
diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well contact
p substrate
n well
65. N-diffusion
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• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates because it
doesn’t melt during later processing
p substrate
n well
n+ Diffusion
68. P-Diffusion
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• Similar set of steps form p+ diffusion regions for pMOS source and
drain and substrate contact
p+ Diffusion
p substrate
n well
n+
n+ n+
p+
p+
p+
69. Contacts
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• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Contact
70. Metalization
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• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Metal
71. Comparison of NMOS, CMOS & BiCMOS technologies
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NMOS (N-channel Metal-Oxide-Semiconductor), CMOS (Complementary Metal-Oxide-
Semiconductor), and BiCMOS (Bipolar-CMOS) are three different semiconductor technologies
used in integrated circuits. They each have their own characteristics, advantages, and
disadvantages. Let's compare these technologies in various aspects:
1.Transistor Types:
1. NMOS: Uses only N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).
2. CMOS: Combines both N-channel and P-channel MOSFETs to achieve complementary logic.
3. BiCMOS: Integrates bipolar transistors (BJTs) along with CMOS transistors.
2.Power Consumption:
1. NMOS: Consumes more power when idle due to leakage current.
2. CMOS: Consumes less static power because it doesn't have a direct path from VDD to
ground when idle.
3. BiCMOS: Consumes more power than pure CMOS due to the presence of bipolar
transistors.
72. Comparison of NMOS, CMOS & BiCMOS technologies
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3.Speed:
1. NMOS: Faster switching compared to CMOS but slower than BiCMOS.
2. CMOS: Slower switching than NMOS but more power-efficient.
3. BiCMOS: Faster switching than both NMOS and CMOS.
4.Noise Margin:
1. NMOS: Lower noise margin due to its higher susceptibility to noise.
2. CMOS: Offers good noise immunity due to complementary operation.
3. BiCMOS: Similar noise immunity to CMOS.
5.Integration Density:
1. NMOS: Lower integration density due to larger transistor sizes and higher power
consumption.
2. CMOS: Offers high integration density and is widely used in modern VLSI circuits.
3. BiCMOS: Has a moderate integration density.
73. Comparison of NMOS, CMOS & BiCMOS technologies
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6.Complexity and Cost:
1. NMOS: Simple to fabricate but consumes more power.
2. CMOS: Cost-effective due to its widespread use and low power consumption.
3. BiCMOS: More complex and costly to manufacture than pure CMOS.
7.Standby Power Consumption:
1. NMOS: High standby power consumption.
2. CMOS: Low standby power consumption.
3. BiCMOS: Moderate standby power consumption, better than NMOS but not as low as
CMOS.
8.Applications:
1.NMOS: Older technology, less common today, used in some specific analog and mixed-signal
applications.
2.CMOS: Ubiquitous in digital and mixed-signal ICs, such as microcontrollers, processors, and
memory.
3.BiCMOS: Used in applications that require a combination of high-speed analog and digital
circuitry, like RF and high-frequency mixed-signal designs.
