The document outlines a course on microprocessor programming and interfacing, covering key objectives such as basic microprocessor architecture, assembly programming for x86 processors, and peripheral interfacing. It includes details about the course schedule, evaluation scheme, textbooks, and lab attendance requirements. The teaching team comprises Vipin Kizheppatt as the instructor and several other supporting instructors.

1. Microprocessor Programming
and
Interfacing
Introduction
Vipin Kizheppatt 10/01/2024

2. Course Administration
2
Schedule
Lecture: Mon, Wed 9:00 - 9:50 AM, Thu 2:00-2:50 PM
Tutorial: Thu 8:00-8:50 PM
Lab: Mon 11:00-12:50 PM, Sat 11:-12:50 PM at CC Lab
Teaching Team
IC: Vipin Kizheppatt (D212, Ph: +91-832-2580-383
email: kizheppattv@goa.bits-pilani.ac.in)
Instructors: Amalin Prince A, Manish Gupta, Arun Raman

3. Course Objectives
3
1. Describe the basic architecture of microprocessors.
2. Able to write simple to moderately complex assembly level
programs for x86 processors.
3. Able to interface different peripherals (such as DMA
controller, ADC, DAC etc.) with 8086 microprocessor and
control them through software.
4.Interface interrupt controller with 8086 microprocessor and
write interrupt service routine for the peripherals.
Text Book: Barry B Brey, The Intel Microprocessors.Pearson,
Eight Ed. 2009
Reference Book: Douglas V Hall, Microprocessor and
Interfacing, TMH, Second Edition

4. Evaluation Scheme
4
Component Duration Weightage
(%)
Date & Time OB/CB
Midsem Exam 90 Mins 25% 15/03/24
11:00AM-
12:30PM
CB
Quizzes 4 quizzes with
10 mins each.
Best 3 will be
considered for
grading
15% Feb 9-12
March 1-4
March 29- April
1
April 19-22
CB
Evaluated Labs 4 evaluated
labs, each one
1.5 hrs. Best 3
will be
considered for
grading
15% Feb 9-12
March 1-4
March 29- April
1
April 19-22
OB
Lab Compre 1.5 hrs 10% April 26-April 29 OB
Comprehensive
Examination
3 hrs 35% 10/05/24 (AN) OB+CB
NB: 80% lab attendance is required to appear for lab compre

5. CPU vs MicroProcessor
5
AGC prototype of Apollo (Image source: Wikipedia)
Motherboard of an early 2000 computer

6. Why to
study an
obsolete
processor?
6

7. CPU Architecture
Microprocessor Architecture
7
ALU
Control Unit

8. ALU Design
8
Circuit diagram
Abstracted symbol
4 bit adder by cascading four 1 bit adders
Full Adder

9. ALU Design
9
Adder/Subtractor
4
4
4
Multiplier
4
4
4
Comparator
4
4
Complement 4
4
4

10. The ALU
10
Add/Sub
4
4
4
Multiplier
4
4
4
Comparator
4
4
Complement
4
4
4
4
:1
Mux
Control The multiplexer (MUX) chooses
the output of a particular circuit
based on the control signal
4
ALU
data_in1
data_in2
data_out
Abstract Model
Control
4
4
2
4

11. The ALU
11
ALU
data_in1
data_in2
data_out
Abstract Model
Control
4
4
2
4
• ALU requires some data to operate on
• It requires some control signals also to specify the type
of operation to perform

12. Registers
12
• But for ALU to process data it should be stored somewhere
• Output of ALU needs to be stored somewhere so that it can
process new data
• That is where registers are useful
• A register is a bunch of flip-flops storing different bits of
same data
D Q
CLK
En
D Q
CLK
En
D Q
CLK
En
D Q
CLK
En
A 4-bit register

13. Registers
13
En
DataIn
DataOut
Control Unit
Reg 1
Reg 2
Result
ALU
Microprocessor Architecture
4
4

14. Register File
14
Reg 1
Reg 0
Reg 2
Reg 31
.
.
.
Address
Decoder
Write Register
Address
RegWriteEn
En
En
En
En

15. Register File
15
Reg 1
Reg 0
Reg 2
Reg 31
.
.
.
Address
Decoder
Write Register Data
Write Register
Address
RegWriteEn

16. Register File
16
Reg 1
Reg 0
Reg 2
Reg 31
.
.
.
Address
Decoder
MUX
MUX
Read Register
Data 2
Read Register
Data 1
Read Register Address 1
Read Register Address 2
Write Register Data
Write Register
Address
RegWriteEn

17. Register File
Control Unit
ALU
Microprocessor Architecture
17
Read
address 1
Read
address 2
Write
address
Write
data
Read
data 2
Read
data 1
Register File
RegWriteEn
RegFile
• Registers store data temporarily
• Register file require control signals to specify in which register
data should be stored, which register value should be
propagated to ALU etc.

18. Stored Program Computer Model
18
Processor Memory
• In this model a computer has a fixed hardware architecture
but can perform a variety of operations through
program/software
• Software is composed of code and data
• Software is stored in memory and the processor fetches
instructions from the memory in a sequential manner and
executes them

19. Software
19
Assume you need to add two variables and find the result
c = a + b
data
code

20. Software
20
• We know ultimately addition will be performed by ALU
• a, b and c should be mapped to some registers
• Assume a is mapped to register 0 (reg address 0), b to register
1 and c to register 2 (reg address 2)
Read
address 1
Read
address 2
Write
address
Write
data
Read
data 2
Read
data 1
Register File
RegWriteEn
ALU
data_in1
data_in2
data_out
Abstract Model
Control
4
4
2
4

21. Software
21
Read
address 1
Read
address 2
Write
address
Write
data
Read
data 2
Read
data 1
Register File
RegWriteEn
ALU
data_in1
data_in2
data_out
Abstract Model
Control
4
4
2
4
0 to choose register-0
1 to choose register-1 2 to choose register-2
0 to choose addition operation

22. Software
22
Read
address 1
Read
address 2
Write
address
Write
data
Read
data 2
Read
data 1
Register File
RegWriteEn
ALU
data_in1
data_in2
data_out
Abstract Model
Control
4
4
2
4
Control logic

23. Software
23
• Assume there are 8 registers in the processor hence 3 bits to
specify the register address
• Combined signals from CU might look like this
00 000 001 010
Indicate add operation
Register 0
Register 1 Register 2
• Writing in binary is cumbersome, so usually prefer
hexadecimal
0x00A or 00AH

24. Software
24
• So 00AH can be called as an instruction to add the contents of
register0 and register1 and store in register2 for our
hypothetical processor
• As humans, it is quite difficult and error prone to
memorize/write programs using instructions even in
hexadecimal
• Hence we use symbolic English like mnemonics to write
programs
Eg: ADD r2,r1,r0
• Later will use tools such as an assembler to convert these
mnemonic representation into numbers which the actual
processor understands!!
• Since we are using stored program model, we need a memory
model now to interface with processor. Let’s build it next

25. Memory Abstract Model
25
Memory
Address [a1:a0]
Data[3:0]
WE#
RE#

26. Sample assembly program and
machine code
• Aim  Add 20H and 30H and store the result in memory
location 000AH
• Assembly Code Hex Code
• MOV A,#20H 3E 20
• MOV B,#30H 06 30
• ADD A,B 80
• MOV [000AH],A 32 0A 00
• HLT 76
26

27. 27
Program Execution
PC
XXXX
Control logic
ALU
XX
Acc
XX
XX XX
B C D
MUX
XX
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
Somehow got the
programme in the
memory
RD#
WR#

28. 28
PC
0000H
Control logic
ALU
XX
Acc
XX
XX XX
B C D
MUX
XX
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
Somehow got the
programme in the
memory
RD#
WR#
0000H
0
Program Execution

29. 29
PC
0000H
Control logic
ALU
XX
Acc
XX
XX XX
B C D
MUX
XX
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
0000H
0
3EH
Program Execution

30. 30
PC
0000H
Control logic
ALU
XX
Acc
XX
XX XX
B C D
MUX
XX
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
Control logic decodes
instruction, realizes
need to read another
data and store in A.
starts next read cycle
3EH
Program Execution

31. 31
PC
0002H
Control logic
ALU
XX
Acc
XX
XX XX
B C D
MUX
XX
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
0001H
0
Program Execution

32. 32
PC
0002H
Control logic
ALU
XX
Acc
XX
XX XX
B C D
MUX
XX
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
0001H
0
20H
Program Execution

33. 33
PC
0002H
Control logic
ALU
XX
Acc
XX
XX XX
B C D
MUX
XX
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
20H
Control logic stores
the data in the A
register. Increments
the PC
Program Execution

34. 34
PC
0004H
Control logic
ALU
20H
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
Similarly stores 30H in
B register
Program Execution

35. 35
PC
0004H
Control logic
ALU
20H
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
0004H
0
Program Execution

36. 36
PC
0004H
Control logic
ALU
20H
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
0004H
0
80H
Program Execution

37. 37
PC
0005H
Control logic
ALU
20H
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
Control logic decodes
instruction, realizes it
needs add the
contents of A and B
and store the result in
A
80H
Program Execution

38. 38
PC
0005H
Control logic
ALU
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
50H
Program Execution

39. 39
PC
0005H
Control logic
ALU
50H
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
0005H
0
Program Execution

40. 40
PC
0005H
Control logic
ALU
50H
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
0005H
0
32H
Program Execution

41. 41
PC
0008H
Control logic
ALU
50H
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
Control logic decodes
instruction, realizes it
store the content of A
register back to
memory. Address
where it has to be
stored has to be taken
from the memory
itself!!
32H
Program Execution

42. 42
PC
0008H
Control logic
ALU
50H
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
This is the address
were result has to be
stored
000AH
Program Execution

43. 43
PC
0008H
Control logic
ALU
50H
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
XX
RD#
WR#
000AH
0
0050H
Program Execution

44. 44
PC
0008H
Control logic
ALU
50H
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
50
RD#
WR#
000AH
0
0050H
Program Execution

45. 45
PC
0008H
Control logic
ALU
50H
Acc
XX
XX XX
B C D
MUX
30H
F
Reset#
Latch
Memory
Data Bus
Address Bus
A15 -A0
D7 –D0
0
1
2
3
4
5
6
7
8
9
A
CPU
00111110 (3EH)
00100000 (20H)
00000110 (06H)
00110000 (30H)
10000000 (80H)
00110010 (32H)
00000000 (0AH)
10000101 (00H)
01110110 (76H)
XX
50
RD#
WR#
When the processor
sees HALT instruction,
it stops execution and
the PC no longer
increments
76H
Program Execution