unit 5, IC Technology, RTU 8th sem ECE. isolation techniques (juntion, oxide, LOCOS, trench), bird's beak problem, planarisation, metallisation, CMP (chemical mechanical polishing), SOI (silicon on insulator)

1. VLSI PROCESS
INTEGRATION
Neha Sharma
Assistant Professor
Department of Electronics and Communication Engineering
Engineering College Jhalawar (Rajasthan)

2. SYLLABUS
■ INTRODUCTION TO IC TECHNOLOGY- Semiconductor Substrate- Crystal defects,
Electronic Grade Silicon, Czochralski Growth, Float Zone Growth, Characterization &
evaluation of Crystals; Wafer Preparation- Silicon Shaping, Etching and Polishing, Chemical
cleaning.
■ DIFFUSION & OXIDATION - Ficks diffusion Equation in One Dimension, Atomic model,
Analytic Solution of Ficks Law, correction to simple theory, Diffusion in SiO2. Ion Implantation
and Ion Implantation Systems. Oxidation Growth mechanism and Deal-Grove Model of
oxidation, Linear and Parabolic Rate co-efficient, Structure of SiO2, Oxidation techniques and
system, Oxide properties.
■ CHEMICAL VAPOUR DEPOSITION AND EPITAXIAL LAYER GROWTH- CVD for
deposition of dielectric and polysilicon thick Layer – a simple CVD system, Chemical
equilibrium and the law of mass action, Introduction to atmospheric CVD of dielectric, low
pressure CVD of dielectric and semiconductor. Epitaxy-Vapour Phase Expitaxy, Defects in
Epitaxial growth, Metal Organic Chemical Vapor Deposition, Molecular beam epitaxy.
■ PATTERN TRANSFER & ETCHING - Introduction to photo/optical lithography, Contact/
proximity printers Projection printers, Mask generation, photo resists. Dry & Wet etching,
methods for anisotropic etching, Plasma etching, Reaction ion etching (RIE).
■ VLSI PROCESS INTEGRATION- Junction and Oxide Isolation, LOCOS methods, Trench
Isolation, SOI; Metallization, Planarization. Fundamental consideration for IC Processing,
NMOS IC Technology, CMOS IC Technology, Bipolar IC Technology. Fault diagnosis and
characterization techniques.

3. DEVICE ISOLATION
TECHNIQUES
(junction and oxide isolation, LOCOS, trench isolation)

4. Device Isolation
Why it is required?
■ To prevent undesired
conducting paths;
■ To avoid creation of
inversion layers
outside the channels;
■ To reduce leakage
currents.
What is isolation ?
VLSI consists of several active
and passive components
interconnected within a
monolithic block of
semiconductor material. Each
component must be electrically
separated from each other to
allow design flexibility.

5. Types
■ Junction isolation
■ Oxide isolation
■ LOCOS (local
oxidation)
■ Trench Isolation

6. pn Junction
isolation
• Pn junction formed by the diffusion in
the semiconductor substrate of opposite
impurity type is isolated from others if it
is reversed or not biased.
• The reverse biased pn junction would act
as the electrical isolation between
adjacent devices.
• Self isolation

7. This is an older technology and has some
demerits specially with reduced dimensions
in today’s need for fast speed devices.
■ It becomes more difficult to control isolation tub width
■ The capacitance associated with these junctions, i.e
the collector isolation capacitance affects the speed of
the transistors.

8. Oxide / dielectric
isolation
• Devices are created in dedicated
regions called active areas.
• Each active area is surrounded by
thick oxide barrier called field oxide.
• Silicon dioxide used as dielectric
• Each active area is surrounded by
thick oxide barrier called field oxide.

9. LOCOS(local
oxidation)
• Local Oxidation of Silicon (LOCOS) is the
traditional isolation technique.
• At first a very thin silicon oxide layer is
grown on the wafer, the so-called pad oxide.
• Then a layer of silicon nitride is deposited
which is used as an oxide barrier.
• The pattern transfer is performed by
photolithography.
• After lithography the pattern is etched into
the nitride.
• The result is the nitride mask which defines
the active areas for the oxidation process.

10. • The next step is the main part of
the LOCOS process, the growth of
the thermal oxide. After the
oxidation process is finished,
• the last step is the removal of the
nitride layer.
• The advantage
of LOCOS fabrication are the
simple process flow and the high
oxide quality, because the
whole LOCOS structure is
thermally grown.

11. Bird's beak
problem
■ The main drawback of this technique is the so-called bird's beak
effect and the surface area which is lost to this encroachment
■ The LOCOS process utilizes the different rates of oxidation of silicon
and silicon nitride, which is used for local masking.
■ The silicon nitride masks regions where no oxidation should occur, the
oxide only growths on the bare silicon. Since silicon and silicon nitride
have different coefficients of thermal expansion, a thin oxide layer -
the pad oxide - is deposited between the silicon and the silicon nitride
to prevent strain due to temperature changes.

12. This extension has the shape of a bird's beak whose length
depends on the length of the oxidation process and the
thickness of the pad oxide and the nitride as well.

13. Trench Isolation
■ In a trench isolation, A trench is cut in the semiconductor and then the
trench is filled with non-conducting material.
■ The Shallow Trench Isolation process starts in the same way as
the LOCOS process.
■ a shallow trench is etched into the silicon substrate,
■ After underetching of the oxide pad, also a thermal oxide in the
trench is grown, the so-called liner oxide
■ But unlike with LOCOS, the thermal oxidation process is stopped after
the formation of a thin oxide layer, and the rest of the trench is filled
with a deposited oxide (see
■ Next, the excessive (deposited) oxide is removed with chemical
mechanical planarization. At last the nitride mask is also removed.
The price for saving space with STI is the larger number of different
process steps.

15. Advantages
• Consumes less space
• No bird’s beak problem
• Provides isolation between p and
n channel devices to prevent
latch-up in CMOS circuits.
• Improves packaging density.
• Can be used to form storage
capacitors in high-density DRAM
applications.

16. Planarization
• Planarization is a process of achieving a flat
profile on the wafer surface.
• Most deposition process produce a surface
with a finite roughness which usually increases
with increased deposition rate and thickness.
Problems with non-planarized
structures
• Breaks in the continuity of fine
lines
• Inability to image fine-line
patterns over the wafer
Planarization techniques
• Local planarization
• Chemical mechanical
polishing (CMP)

17. Chemical
mechanical
polishing
Chemical mechanical polishing or
global planarization technique is a
process of smoothing surfaces
with the combination of chemical
and mechanical forces. It can be
thought of as a hybrid of chemical
etching and free abrasive
polishing.

18. Chemical mechanical polishing
■ In planarization, the wafer is mounted on a rotating platen.
■ It is then polished using a polishing pad and a slurry containing abrasive particles.
The abrasive particles attack the wafer surface and remove small particles.
■ The polishing pad and platen rotate in opposite directions and the slurry carries
away the small particles. This removal is the mechanical polishing part.
■ The slurry material is chosen such that it can also dissolve or etch the surface
material away.
■ This constitutes the chemical removal part and hence, the technique is called CMP.
■ Typically, the polishing pad is made of polyurethane foam, while the slurry depends
on the material to be removed.
■ For metals, usually alumina is used, while etchants like KOH and NH4OH are used
for silicon oxide polishing. After CMP, there is a post cleaning step that involves
cleaning the wafers with de-ionized water and then N2 blow drying. This removes
any excess slurry particles from the wafer surface.

20. SILICON ON INSULATOR
(SOI)

21. It uses layered silicon–insulator–silicon substrate in place
of conventional silicon substrates in semiconductor
manufacturing
The choice of insulator depends on
application
• Sapphire is used for high-
performance radio frequency (RF)
and radiation-sensitive
applications.
• Silicon dioxide is used for
diminished short channel effects in
microelectronics devices. SOI
Technology.

22. SOI
TECHNOLOGIES
1. Silicon on sapphire (SOS)
2. Separation by implanted oxygen (SIMOX)
3. Bond and Etch back SOI (BESOI)

23. SOI fabrication process
■ In this process, a thin layer of single-crystal silicon can be produced on
top of a thermal SiO2 layer on a silicon wafer.
■ Strips of oxide are produced by patterning the oxide layer using
photolithography.
■ a thin layer of silicon is then deposited on the wafer.
■ It will be polycrystalline in the regions where the deposited silicon
layer overlays the oxide and it will be single crystal in the regions
where there is direct contact with silicon substrate.
■ In the next step we will directionally recrystalise the silicon layer, which
in turn recrystallises the substrate to act as the nucleation centre
■ As the heated zone is scanned across the wafer the crystal growth,
propagates from these nucleation regions to the regions of the silicon
film on top of the oxide islands or strips.
■ Thus we form a complete single crystal layer of silicon.

24. Advantages
■ Lower parasitic capacitance due to isolation from the bulk silicon,
which improves power consumption at matched performance.
■ Resistance to latch up due to complete isolation of the n- and p-well
structures.
■ 50 % faster than conventional bulk silicon.
■ Reduced temperature dependency due to no doping.
■ Better yield due to high density, better wafer utilization.
■ Lower leakage currents due to isolation thus higher power efficiency.
■ No latch up problem in CMOS structure.
■ Inherently radiation hardened ( resistant to soft errors ), thus reducing
the need for redundancy

26. METALLIZATION
The “wiring” of the various components together to get a functioning
circuit.

27. Metallization
■ Definition: Metallization is the process that makes accessible the IC to
the outside world through conducting pads.
■ Doped silicon conduct electricity but have large resistance and lack
interconnecting facility.
■ Thin conductive metal films (Al, Cu, Au, Ag etc) are used as
interconnects between Si and external leads.

28. There are a variety of techniques for
depositing metal layers in a IC.
■ Sputtering is a physical vapor deposition process mainly
used for Al and its alloys e.g. Al-Cu alloys
■ Chemical vapor deposition (CVD) is mainly used for poly Si
(for gate in MOSFET) and tungsten (metal plugs for trench
filling). It is also used for depositing barrier layers (silicides
and nitrides) between Si and Cu.
■ Electroplating is used for Cu deposition (dual-damascene
process)

30. CHOICE OF MATERIAL

31. PROBLEMS IN METALLISATION