In today’s world, there is an ever-increasing demand for SOC speed, performance, and features. To cater to all those needs, the industry is moving toward lower technology nodes. The current market has become more and more demanding, in turn forcing complex architectures and reduced time to market. The complex integrations and smaller design cycle emphasize the importance of floorplanning, i.e., the first step in netlist-to-GDSII design flow. Floorplanning not only captures designer’s intent, but also presents the challenges and opportunities that affect the entire design flow, from design to implementation and chip assembly. A typical SOC can include many hard- and soft-IP macros, memories, analog blocks, and multiple power domains. Because of the increases in gate count, power domains, power modes, and special architectural requirements, most SOCs these days are hierarchical designs. The SOC interacts with the outside world through sensors, antennas, displays, and other elements, which introduce a lot of analog component in the chip. All of these limitations directly result in various challenges in floorplanning. Floorplanning includes macro/block placement, design partitioning, pin placement, power planning, and power grid design. What make the job more important is that the decisions taken for macro/block placement, partitioning, I/O-pad placement, and power planning directly or indirectly impact the overall implementation cycle. Lots of iterations happen to get an optimum floorplan. The designer takes care of the design parameters, such as power, area, timing, and performance during floorplanning. These estimations are repeatedly reviewed, based on the feedback of other stakeholders such as the implementation team, IP owners, and RTL designers. The outcome of floorplanning is a proper arrangement of macros/blocks, power grid, pin placement, and partitioned blocks that can be implemented in parallel. In hierarchical designs, the quality of the floorplan is analyzed after the blocks are integrated at the top level. That can results in unnecessary iterative work, wasted resource hours, and longer cycle times, which could mean missed market opportunities. This underscores the importance of floorplanning. In this paper, we will discuss some of the good practices, techniques, and complex cases that arise while floorplanning in an SOC. The first rule of thumb for floorplanning is to arrange the hard macros and memories in such a manner that you end up with a core area (to be used for SOG placement) square in shape. This is always not possible, however, because of the large number of analog-IP blocks, memories, and various other requirements in design.

1. Intro Floor
FloorPlanning
How to Plan your own chip
Ahmed Abdelazeem
Faculty of Engineering
Zagazig University
RTL2GDSII Flow, February 2022
Ahmed Abdelazeem ASIC Physical Design

2. Intro Floor
Table of Contents
1 Introduction
2 Floorplanning
Ahmed Abdelazeem ASIC Physical Design

3. Intro Floor Overall setup Intro Appendix A
Table of Contents
1 Introduction
2 Floorplanning
Ahmed Abdelazeem ASIC Physical Design

4. Intro Floor Overall setup Intro Appendix A
Overall Design Flow
Ahmed Abdelazeem ASIC Physical Design

5. Intro Floor Overall setup Intro Appendix A
The Big Picture...
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6. Intro Floor Overall setup Intro Appendix A
Data Setup
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7. Intro Floor Overall setup Intro Appendix A
Logical Libraries
Provide timing and functionality information for all
standard cells (and, or, flipflop, ...)
Provide timing information for hard macros(IP,
ROM, RAM, ...)
Define drive/load design rules:
Max fanout
Max transition
Max/Min capacitance
Are usually the same ones used by Syntheis during
synthesis
Ahmed Abdelazeem ASIC Physical Design

8. Intro Floor Overall setup Intro Appendix A
Timing Constraints
“Timing Constraints” are required to communicate the
design’s timing intentions to PnR Tool
They should be the same ones used for synthesis with
Synthesis Tool (preferably SDC)
Ahmed Abdelazeem ASIC Physical Design

9. Intro Floor Overall setup Intro Appendix A
Physical Libraries
Contain physical information of
standard, macro and pad cells,
necessary for placement and routing
Define placement unit tile
Height of placement rows
Minimum width resolution
Preferred routing directions
Pitch of routing tracks
Ahmed Abdelazeem ASIC Physical Design

10. Intro Floor Overall setup Intro Appendix A
Technology File (.tflef file)
Tech File is unique to each technology
Contains metal layer technology parameters:
Number and name designations for each layer/via
Dielectric constant for technology
Physical and electrical characteristics of each layer/via
Design rules for each layer/Via (Minimum wire widths and
wire-to-wire spacing, etc.)
Units and precision for electrical units
Colors and patterns of layers for display
....
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11. Intro Floor Overall setup Intro Appendix A
Example of a Technology File
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12. Intro Floor Overall setup Intro Appendix A
Timing is Based on Cell and Net Delays
PnR tool calculates delay for every cell and every net
To calculate delays, tool needs to know each net’s parasitic Rs
and Cs
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13. Intro Floor Overall setup Intro Appendix A
RC Models
Tool calculates C and R using the net
geometry and the TLU+ look-up
tables
UDSM process effects modeled
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14. Intro Floor Overall setup Intro Appendix A
Mapping file
The Mapping File maps the .tf (lef technology file) layer/via
names to Star-RCXT .itf layer/via names.
Ahmed Abdelazeem ASIC Physical Design

15. Intro Floor Overall setup Intro Appendix A
Calculating Cell and Net Delay
Now that R and C are known from TLU+, the delays
can be calculated
For Cell Delays, only Ctotal / Ceff is needed
Calculating Net Delay is done using Delay Calculation
algorithms: Elmore, Arnoldi
Ahmed Abdelazeem ASIC Physical Design

16. Intro Floor Overall setup Intro Appendix A
PreRoute Delay Calculation Algorithm
Prior to routing, net geometry is estimated based on a
Virtual Route
Since Virtual Routing is only an estimate,an Elmore
model is used for delay calculation
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17. Intro Floor Overall setup Intro Appendix A
PostRoute Delay Calculation Algorithms
After routing, detailed nets are available and extraction
can be more accurate
By default, Elmore is still used
Arnoldi can be turned on for postroute calculations
Ahmed Abdelazeem ASIC Physical Design

18. Intro Floor Overall setup Intro Appendix A
What is a Standard Cell Library?
A Standard Cell is a predesigned layout of
one specific basic logic gate
Each cell usually has the same standard
height.
A Standard Cell Library contains a varied
collection of standard cells
Libraries are usually supplied by an ASIC
vendor or library group
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19. Intro Floor Overall setup Intro Appendix A
“Layout” vs. “Abstract” Views
A standard cell library also contains a corresponding abstract
view for each layout view
Abstract views contain only the minimal data needed for
Place & Route
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20. Intro Floor Overall setup Intro Appendix A
What Does “Place and Route” Do?
Layout is built with three types of reference cells:
Macro cells (ROMs, RAMs, IP blocks)
Standard cells (nand2, inv, dff, ...)
Pad cells (input, output, bi-dir, Vdd, Vss pads)
You have to define Macro and Pad cell locations during the
Floorplanning stage, before Placement and Routing
Location of all Standard Cells is automatically chosen by the
tool during Placement, based on routability and timing
Pins are then physically connected during Routing, based on
timing
Ahmed Abdelazeem ASIC Physical Design

21. Intro Floor Overall setup Intro Appendix A
Timing-Driven Placement
Standard cells are placed in “placement rows”
Cells in a timing-critical path are placed close together to
reduce routing-related delays, which is Timing-Driven
Placement
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22. Intro Floor Overall setup Intro Appendix A
Abutted Rows
Placement rows are commonly abutted to reduce core area
Cell orientations in abutted rows are flipped
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23. Intro Floor Overall setup Intro Appendix A
Vias: Connecting Metal to Metal
Connecting between metal layers requires one or more vias.
Example
Connecting a signal from Metal 1 to Metal 3 requires two vias and
an intermediate Metal 2 connection
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24. Intro Floor Overall setup Intro Appendix A
Preferred Routing Directions
Metal layers have preferred routing
directions
Default preferred direction:
Metal 1 – Horizontal
Metal 2 – Vertical
Metal 3 – Horizontal, etc
Why is this beneficial?
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25. Intro Floor Overall setup Intro Appendix A
Preferred Routing Directions
Metal layers have preferred routing
directions
Default preferred direction:
Metal 1 – Horizontal
Metal 2 – Vertical
Metal 3 – Horizontal, etc
Why is this beneficial?
preferred routing directions
Having preferred routing directions greatly reduces the amount of
metal layer “jumping” the router may need to do to connect any
two pins, which reduces resistance and therefore propagation delay,
as well as run time.
Ahmed Abdelazeem ASIC Physical Design

26. Intro Floor Overall setup Intro Appendix A
Routing Tracks
Metal routes must meet minimum width and spacing “design
rules” to prevent open and short circuits during fabrication
In gridded routers these design rules determine the minimum
center-to-center distance for each metal layer, a.k.a. grid or
track spacing
Congestion occurs if there are more wires to be routed than
available tracks
Ahmed Abdelazeem ASIC Physical Design

27. Intro Floor Overall setup Intro Appendix A
Timing-Driven Routing
Routing along the timing-critical path is given priority:
Creates shorter, faster connections
Non-critical paths are routed around critical areas:
Reduces routability problems for critical paths
Does not adversely impact timing of non-critical paths
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28. Intro Floor Overall setup Intro Appendix A
Logic Optimization
What if critical paths do not meet timing/drive requirements, even
with timing-driven placement or routing?
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29. Intro Floor Overall setup Intro Appendix A
What is a Gate in “Gate-level Netlist”?
Gate: Basic Logic Component
Other Gates:
Buffer, Nand, Nor, Xor, AOI, Mux, D-FF, Latch, etc
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30. Intro Floor Overall setup Intro Appendix A
Transistor or Device Representation
CMOS Inverter Example
Gates are made up of active devices or transistors.
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31. Intro Floor Overall setup Intro Appendix A
Basic Devices and Interconnect
Integrated circuits are built out of active and passive
components, also called devices:
Active devices:
Transistors
Diodes
Passive devices:
Resistors
Capacitors
Devices are connected together with polysilicon or metal
interconnect:
Interconnect can add unwanted or parasitic capacitance,
resistance and inductance effects
Device types and sizes are process or technology specific:
The focus here is on CMOS technology
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32. Intro Floor Overall setup Intro Appendix A
What is “Physical Layout”?
CMOS Inverter Example
Physical Layout – Topography of devices and interconnects,
made up of polygons that represent different
layers of material.
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33. Intro Floor Overall setup Intro Appendix A
Process of Device Fabrication
Devices are fabricated vertically on a silicon substrate wafer by
layering different materials in specific locations and shapes on
top of each other
Each of many process masks defines the shapes and locations
of a specific layer of material (diffusion, polysilicon, metal,
contact, etc)
Mask shapes, derived from the layout view, are transformed to
silicon via photolithographic and chemical processes
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34. Intro Floor Overall setup Intro Appendix A
Wafer Representation of Layout Polygons
Example of complimentary devices in 0.25 um CMOS
technology or process.
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35. Intro Floor Overall setup Intro Appendix A
What is Meant by “0.xx um Technology”?
Gate or Channel Dimensions (L and W)
0.xx um Technology
In CMOS Technology the um or nm dimension refers to the
channel length, a minimum dimension which is fixed for most
devices in the same library.
Current flow or drive strength of the device is proportional to
W/L; Device size or area is proportional to W x L.
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36. Intro Floor Overall setup Intro Appendix A
Comparing Technologies
The drive strength of both devices is the same: W/L = 6.
The diffusion area (5xLxW) of A is 4x that of B.
Which is preferred?
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37. Intro Floor Overall setup Intro Appendix A
Relative Device Drive Strengths
Drive Strengths
To double the drive strength of a device, double the channel width
(W), or connect two 1X devices in parallel. The latter approach
keeps the height at a fixed or “standard” height.
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38. Intro Floor Overall setup Intro Appendix A
Gate Drive Strength Example
Gate Drive
Each gate in the library is represented by multiple cells with
different drive strengths for effective speed vs. area optimization.
Ahmed Abdelazeem ASIC Physical Design

39. Intro Floor Overall setup Intro Appendix A
Drive/Buffering Rules: Max Transition/Cap
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40. Intro Floor Floor Macro PAD
Table of Contents
1 Introduction
2 Floorplanning
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41. Intro Floor Floor Macro PAD
What Is Floorplanning?
Definition
Floorplanning is the process of deriving the die size, allocating
space for soft blocks, planning power, and macro placement.
With a top-level netlist, you can
start to floorplan the chip.
Define Die Size.
Place the IOs.
Perform macro placement.
Perform power planning.
Power domain definition
Flip-chip bump placement
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42. Intro Floor Floor Macro PAD
Floorplanning
Floorplanning consists of defining the Core Placement area,
the Periphery area and the Power/Ground grid.
The Core Placement area consists of Placement Rows where
standard cells and macro cells are placed.
A placement row consists of a row of “unit tile” cells (part of
the standard cell library, width defined by the minimum metal
pitch). Standard cells are placed in the core of a chip and
occupy specific tile(s) within the placement rows. A standard
cell may occupy a single or multiple tiles.
The pad cells (input, output, bi-dir, power and ground pads)
are placed in the Periphery Area, which is defined by the area
around the outside boundary of the core, usually separated by
a “core-to-pad” spacing distance.
Ahmed Abdelazeem ASIC Physical Design

43. Intro Floor Floor Macro PAD
What Are Sites and Rows?
A site is the minimum unit of placement. It represents a slot where
a cell can be placed. Rows are multiples of sites and define
locations where the placement tool places cells.
Placement tools place cells in locations defined by the cell’s
description in the LEF file. If a cell is of type CORE, then it can
only be placed in a CORE rows. If a cell is of type IO, it can only
be placed in IO rows
Ahmed Abdelazeem ASIC Physical Design

44. Intro Floor Floor Macro PAD
Core and IO Region
From:
A gate level netlist
Relevant physical libraries
Default or user specified aspect ratio and utilization.
Calculate the area of all macro cells and leaf cells
Generate bounding shapes and cell placement rows
Place IO PADs
Signal pads
Filler and corner pads
Bump or flip-chip IO pads
Utilization =
(Total Std Cell+Macro Cell Area)
Core Area
* 100% (1)
Ahmed Abdelazeem ASIC Physical Design

45. Intro Floor Floor Macro PAD
Utilization: A Factor in Determining Core Size
Core “utilization” is the
percentage of the core that
is used by placed std cells
and macros
Ideally would like to achieve
100% utilization at tape-out.
In practice range is 80-85
Recommended starting
netlist utilization should not
exceed 60-75optimizations
and DFM
Utilization =
(Total Std Cell+Macro Cell Area)
Core Area
* 100% (2)
Ahmed Abdelazeem ASIC Physical Design

46. Intro Floor Floor Macro PAD
Aspect Ratio: A Factor in Determining Core Size
Aspect ratio is the ratio between vertical routing resources to
horizontal routing resources.
If you specify a ratio of 1.00, the height and width are the
same and therefore the core is a square.
If you specify a ratio of 2.00, the height is two times the
width.
Ahmed Abdelazeem ASIC Physical Design

47. Intro Floor Floor Macro PAD
Balance Routing Resources
If less vertical routing resources are available, make floorplan
wider (aspect ratio < 1) if possible, to increase vertical
routing resources
If less horizontal routing resources are available, make
floorplan taller (aspect ratio > 1) if possible, to increase
horizontal routing resources
Note
Balancing vertical/horizontal routing resources reduces overall
congestion
Ahmed Abdelazeem ASIC Physical Design

48. Intro Floor Floor Macro PAD
Pad-Limited Design
Question
If the utilization of a pad-limited design is too high during
floorplanning will reducing it affect die size?
Ahmed Abdelazeem ASIC Physical Design

49. Intro Floor Floor Macro PAD
Core-Limited Design
Question
If the utilization of a core-limited design is too high during
floorplanning will reducing it affect die size?
Ahmed Abdelazeem ASIC Physical Design

50. Intro Floor Floor Macro PAD
Hard Macro Placement
When placing large macros we must consider impacts on
routing, timing and power. Usually push them to the sides of
the floorplan.
Placement algorithms generally perform better with a single
large rectangular placement area
For wire-bond place power hungry macros away from the chip
center
After placing hard macros, mark them as FIXED.
Ahmed Abdelazeem ASIC Physical Design

51. Intro Floor Floor Macro PAD
Placement Blockages and Halos
Sometimes, we want to “help” the tool
put certain logic in certain regions or
cluster them together.
Place and Route tools define several types
of placement bounds:
Soft move bounds specify placement
goals, with no guarantee that the cells
will be placed inside the bounds.
Hard move bounds force placement of
the specified cells inside the bounds.
Exclusive move bounds force the
placement of the specified cells inside
the bounds. All other cells must be
placed outside the bounds.
Ahmed Abdelazeem ASIC Physical Design

52. Intro Floor Floor Macro PAD
Placement Blockages and Halos
Placement blockage halos are areas
that the tools should not place any
cells.
These, too, have several types:
Hard Blockage – no cells can be
placed inside.
Soft Blockage – cannot be used
during placement, but may be
used during optimization.
Partial Blockage – an area with
lower utilization.
Halo (padding) – an area
outside a macro that should be
kept clear of standard cells
Ahmed Abdelazeem ASIC Physical Design

53. Intro Floor Floor Macro PAD
Placement Blockages: Macro Keepout Margin (Padding)
Padding
A keepout margin is a region around the boundary of fixed macros
in the design in which no other cells are placed.
Ahmed Abdelazeem ASIC Physical Design

54. Intro Floor Floor Macro PAD
Placement Blockages: Adding or Modifying Global
Placement Blockages
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55. Intro Floor Floor Macro PAD
Placement Blockages: Routing Blockage (Route Guide)
Routing blockages are used to
prevent the route in a particular
area for the specific metal layer for
all nets or only signal nets or PG
nets.
Routing blockages – areas where
routing is not allowed
Ahmed Abdelazeem ASIC Physical Design

56. Intro Floor Floor Macro PAD
Guidelines for a good floorplan
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57. Intro Floor Floor Macro PAD
Pad Area
Pad area consists of:
Input/Output/InOut pads
Power pads and corner pads
Pad fillers
P/G rings
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58. Intro Floor Floor Macro PAD
Pin Alignment
Pin alignment is not less important than macros alignment.
In the case of macros, wire length is reduced, and the area is
increased. In the case of Pin alignment, wire length is
reduced, and the area remains the same
Ahmed Abdelazeem ASIC Physical Design

59. Intro Floor Floor Macro PAD
Hierarchical Approach
Chip is partitioned into smaller
blocks
Each block is P&R’ed
individually
Blocks are integrated back into
the chip
Ahmed Abdelazeem ASIC Physical Design

60. Intro Floor Floor Macro PAD
Chip has:
Pads (signal and P/G)
Block has:
Pins (signal and P/G)
Blocks can be rectangular
or rectilinear in shape.
Ahmed Abdelazeem ASIC Physical Design

61. Intro Floor Floor Macro PAD
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Ahmed Abdelazeem ASIC Physical Design