10. Signoff.pdf

Digital
Implementation
Design for Manufacturing
© Ahmed Abdelazeem. All rights reserved 1

Contents
After completing this unit, you should be able to:
❑ Perform key chip finishing and design for
• manufacturing steps required after the signal
• routing is complete: Fix antenna violations
• Modify the routing patterns to make them more
resistant to defects
• Add redundant contacts
• Perform metal filling and slotting
• Insert filler cells
• Run DRC and LVS operations
3/6/2024 2
© Ahmed Abdelazeem. All rights reserved

Facilities
Building Hours
Restrooms
Meals
Messages
Smoking
Recycling
Phones
Emergency EXIT
Please turn off cell phones and pagers
3
3/6/2024

Workshop Goal
Use IC Compiler II to perform placement, DFT,
CTS, routing and optimization, achieving timing
closure for designs with moderate to high design
challenges.
4
3/6/2024

Target Audience
ASIC, back-end or layout designers with
experience in standard cell-based automatic
Place&Route.
5
3/6/2024

High-Level IC Compiler Flow
Gate-level netlist
Synthesis
Design & Time Setup
Floorplan Definition
Placement & Optimization
CTS & Optimization
Routing & Optimization
Signoff
IC
Compiler
II
6
3/6/2024 © Ahmed Abdelazeem. All rights reserved
✓
✓

✓
✓
✓

Design Status, Completion of Routing Phase
3/6/2024 © Ahmed Abdelazeem. All rights reserved 7
❑ Placement - completed
❑ CTS – completed
❑ Power and ground nets – routed
❑ Signal and clock nets – routed
❑ Signal Integrity issues – fixed/acceptable
❑ Calculated timing – acceptable (>= 0ns slack)
❑ Logical DRC – max cap/transition – no violations
❑ Physical DRC – no violations

Signoff/DFM
❑ After route_opt has been completed, there are several tasks that are required and
some that might be required
❑ Required:
• Sign-off Extraction and STA, with possible ECO
• Sign-off DRC
• Filler cell insertion (fill gaps between standard cells)
• Metal Filling (fill metal layers for CMP)
❑ Possibly required:
• Functional ECO (pre- or post-freeze-silicon)

Manufacturability Issues
• IC Compiler II can address several issues to increase manufacturing yield:
• Gate Oxide integrity → antenna fixing
• Via resistance and reliability → extra contacts
• Random Particle defect → Wire spreading
• Metal erosion → metal slotting
• Metal liftoff → metal slotting
• Metal Over-Etching → metal fill

Problem: Random Particle Defects
❑ Random missing or extra material causes opens or shorts during the
fabrication process
• Wires at minimum spacing are most susceptible to shorts
• Minimum-width wires are most susceptible to opens
Critical
Areas
Conductive defects within critical area -
causing shorts
Non-conductive defects within critical area -
causing opens
Metal 3
Conductive defects outside critical area –
no shorts
Non-conductive defects outside critical area –
no opens

Solution: Wire Spreading + Widening
❑ Spread wires to reduce short critical area
• Push routes off-track by ½ pitch
• Will not push “frozen” nets
❑ Widen wires to reduce open critical area
Wire Tracks
Spreading
off-track
Widening

Problem: Metal Erosion
❑ The wafer is made flat (planarized) by a process called Chemical
Mechanical Polishing (CMP)
❑ Metals are mechanically softer than dielectrics:
• CMP leaves metal tops with a concave shape - dishing
• The wider the metal the more pronounced the dishing
• Wide traces with little intervening dielectric and can become quite thin –
dishing this severe is called erosion
❑ Process rules specify maximum metal density per layer to minimize
erosion

Problem: Metal Liftoff
❑ Conductors and Dielectrics have different coefficients of thermal
expansion:
• Stress builds up with temperature cycling
• Metals can delaminate (lift off) with time
• Wide metal traces are more vulnerable than narrow ones
❑ Maximum metal density rules also address this issue
Dielectric
Metal thermal expansion
Dielectric thermal expansion
Metal

Solution: Metal Slotting
❑ Slotting wide wires reduces the metal density
❑ Slots minimize stress buildup, reducing liftoff tendency
❑ Primarily used on Power and Ground traces:
• Can apply to any other net if wide enough
❑ Slotting parameters can be set layer by layer
OpenSlot SideSpace
EndSpace Length
SideClearance
Width

Problem: Metal Over-Etching
❑ A narrow metal wire separated from other metal receives a higher density of
etchant than closely spaced wires
❑ The narrow metal can get over-etched
❑ Minimum metal density rules are used to control this
Plasma Etchant etches away
un-protected metal
Less
etchant
per um2
of metal
Over-etching
due to high
etchant density

Solution: Metal Fill
❑ Fills empty tracks with metal shapes to meet the minimum metal
density rules
❑ Uses up most of the remaining routing resource:
• No further routing or antenna fixes can be done

Final Validation
From DFM steps
Write .spef file
Generate a
PARA view
Generate
output netlist
PrimeTime
IC
Validator
Signoff STA
Signoff
DRC & LVS
Output GDS2
Prove logical
equivalence after
ICC II optimizations
Timing
engine
ICC II Formality

Final Validation: Netlist Output
❑ Netlists for STA (Static Timing Analysis) do not require output of “Physical only cells”
like:
• Corner Pad Cells
• Pad/ Core Filler Cells
• Unconnected Cell instances
• Deselect unneeded instances in the write_verilog form
❑ Unconnected cell instances (spare cells) are needed for LVS
❑ By default, the top-level netlist generated from ICC II is flat
What if you need a hierarchical netlist?

Final Validation: GDS2 Output
❑ The GDS2 for external Physical verification can be generated from ICC II
❑ Require output of “Physical only cells” like:
• Corner Pad Cells
• Pad/ Core Filler Cells
• Unconnected Cell instances

That’s all Folks!

10. Signoff.pdf

Recommended

Recommended

More Related Content

Similar to 10. Signoff.pdf

Similar to 10. Signoff.pdf (20)

More from Ahmed Abdelazeem

More from Ahmed Abdelazeem (20)

Recently uploaded

Recently uploaded (20)

10. Signoff.pdf