5. Data and Timing Setup Introduction.pdf

Digital
Implementation
Data Setup
1
© Ahmed Abdelazeem

Contents
❑ Big Picture
❑ New Data Model
❑ Design Setup
❑ Time Setup
❑ Appendix A
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Facilities
Building Hours
Restrooms
Meals
Messages
Smoking
Recycling
Phones
Emergency EXIT
Please turn off cell phones and pagers
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Workshop Goal
Use IC Compiler II to perform placement, DFT,
CTS, routing and optimization, achieving timing
closure for designs with moderate to high design
challenges.
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Target Audience
ASIC, back-end or layout designers with
experience in standard cell-based automatic
Place&Route.
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High-Level IC Compiler Flow
Gate-level netlist
Synthesis
Design & Time Setup
Floorplan Definition
Placement & Optimization
CTS & Optimization
Routing & Optimization
Signoff
IC
Compiler
II
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Big Picture
Logic
Synthesis
Place and Route
RTL
Gate Level Netlist Placed and Routed Design
Moving from Logical to Physical
Behavioral, verified,
DFT friendly, and
synthesizable RTL
Verilog code
• Structural Verilog netlist consists
of connected cells from the used
SC library.
• Timing, power, and area
requirements are met under some
assumptions:
➢ Clock skew = 0!
➢ Ideal voltage is supplied to
all cells! [IR drop = 0]
➢ Estimated interconnect
parasitics, regardless of
actual placement and
routing!
• Timing, area, and power
requirements are met with signoff
criteria obtained from foundry
and customer.
• Design rules are met.
• LVS Clean
• IR drop and Electromigration
requirements are met.
Removing all ideal assumptions!
• Actual clock skew is
calculated and taken into
account for timing analysis.
• Actual interconnect
parasitics are calculated
after placement and routing.
• Actual IR drop is calculated
and checked. Design rules
are considered.
• Congestion and cell density
are considered
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Data Setup
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What Does “Place and Route” Do?
❑ Layout is built with three types of reference cells:
◦ Macro cells (ROMs, RAMs, IP blocks)
◦ Standard cells (nand2, inv, DFF, ...)
◦ Pad cells (input, output, bi-dir, VDD, VSS pads)
❑ You have to define Macro and Pad cell locations during the Floorplanning
stage, before Placement and Routing
❑ Location of all Standard Cells is automatically chosen by the tool during
Placement, based on routability and timing
❑ Pins are then physically connected during Routing, based on timing
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A Z
Z
A1
A2
Place the cells
Route wires between pins
OR2A3 INVA4
Z
A1
A2
OR2A3
Z
A
INVA4
Abstract Abstract

Timing-Driven Placement
❑ Standard cells are placed in “placement rows”
❑ Cells in a timing-critical path are placed close together to
reduce routing-related delays
→ Timing-Driven Placement
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BUF2B
VDD
VSS
MUX21
VDD
VSS
INV1
VDD
VSS
NOR3
VDD
VSS
XOR2
VDD
VSS
INV1
VDD
VSS
NA21
VDD
VSS
INV1
VSS
VDD
AND2
VSS
VDD
DFFSR1
VSS
VDD
AOI221
VSS
VDD
JKFF
VSS
VDD
Placement
Rows
Timing-critical cells placed together

Abutted Rows
◼ Placement rows are
commonly abutted to reduce
core area
◼ Cell orientations in abutted
rows are flipped
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BUF2B
VDD
VSS
MUX21
VDD
VSS INV1
VDD
VSS
NOR3
VDD
VSS
XOR2
VDD
VSS
INV1
VDD
VSS
NA21
VDD
VSS
INV1
VSS
VDD
AND2
VSS
VDD
DFFSR1
VSS
VDD
AOI221
VSS
VDD
JKFF
VSS
VDD
Non-abutted Rows
INV1
VSS
VDD
JKF
F
VSS
VDD
DFFSR1
VSS
VDD
AOI221
VSS
VDD
AND2
VSS
VDD
BUF2B
VDD
VSS
NOR3
VDD
VSS
NA21
VDD
VSS
INV1
VDD
VSS
INV1
VDD
VSS
XOR2
VDD
VSS
MUX21
VDD
VSS
Abutted Rows
Flipped Cells
❑ Cells are placed in rows, next to each other
❑ One cell structure continues the previous one
❑ Cells on neighbor rows are flipped so that
they can share the same supply

Vias: Connecting Metal to Metal
Connecting between metal layers requires one or more vias.
Example:
Connecting a signal from Metal 1 to Metal 3 requires
two vias and an intermediate Metal 2 connection.
Metal 1
Oxide
Metal 2
Oxide
Metal 3
Via23
Via12
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Preferred Routing Directions
❑ Metal layers have preferred routing
directions
❑ Default preferred direction:
◦ Metal 1 – Horizontal
◦ Metal 2 – Vertical
◦ Metal 3 – Horizontal, etc
Why is this beneficial?
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Routing Tracks (Wire Tracks)
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Minimum
width
Minimum
spacing
Metal Routing Tracks
Tracks
Failed connection
Layers have
perpendicular
directions
Routing is done on
tracks
Insufficient number of
tracks bring congestion
Metal pitch

Routing Tracks
❑ Metal routes must meet minimum width and spacing “design rules” to
prevent open and short circuits during fabrication
❑ In gridded routers these design rules determine the minimum center-to-
center distance for each metal layer, a.k.a. grid or track spacing
❑ Congestion occurs if there are more wires to be routed than available tracks
Design Rules: Minimum Spacing
Metal Routing Tracks
Minimum Width
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Timing-Driven Routing
❑ Routing along the timing-critical path is given priority:
◦ Creates shorter, faster connections
❑ Non-critical paths are routed around critical areas:
◦ Reduces routability problems for critical paths
◦ Does not adversely impact timing of non-critical paths
Critical Net
Non-Critical Net
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IC Compiler II Library Manager
❑ NDM Cell Library creation is performed using a stand-alone tool called ICC II Library Manager
Enables the quality of the library to be checked before implementation begins
ICC II does not need to check the library setup, which significantly improves runtime
❑ Both applications share a unified logic and physical data model, called NDM
Timing/Power (.db)
Physical
(.frame, GDS, LEF)
Technology
(tf)
IC Compiler II
Library Manager
(icc2_lm_shell)
NDM Cell
Library
Logic/
Physical/
Data Model
IC Compiler II
(icc2_shell)
Netlist
DEF
SDC
UPF
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IC Compiler II NDM Cell Library
❑ ICCII uses standard and macros cell libraries in NDM format, Called CLIBs.
❑ Each cell in a CLIB contains complete physical and logic/timing/power definitions
required for placement, routing, and optimization
• Logic/timing/power data is stored in timing view
➢ Originates from multiple .db files
• Physical data is stored in frame view
➢ Originates from GDS or LEF (not Milkway)
• CLIBs can optionally also contain
design and layout views
❑ CLIBs are associated with a specific technology (from the .tf file)
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Library and Technology Data Source
❑ Library Compiler Create:
• .db from liberty (.lib)
• .frame from GDS or LEF
❑ Library Manger Create CLIBs from:
• Logical /Timing from .db
• Physical NDM from .frame
• Tech-File
❑ IC Compiler use CLIBs
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Standard Cell Definitions in LIBs
cell ( OR2_4x ) {
area : 8.000 ;
pin ( Y ) {
direction : 2;
timing ( ) {
related_pin : "A" ;
timing_sense : positive_unate ;
rise_propagation (drive_3_table_1) {
values ("0.2616, 0.2711, 0.2831,..)
}
rise_transition (drive_3_table_2) {
values ("0.0223, 0.0254, ...)
. . . .
function : "(A | B)";
max_capacitance : 1.14810 ;
min_capacitance : 0.00220 ;
}
pin ( A ) {
direction : 1;
capacitance : 0.012000;
. . . .
Cell name
Cell Area
Design Rules for Pin Y
Electrical Characteristics
of Pin A
Pin Y Functionality
Y = A | B
t
A
B
Y
Example of a cell description in .lib format
Characteristic Curves
(OR)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.0 1.0 2.0
Input Transition (ns)
Cell
Delay
(ns)
.30
.10
.01
Load
2 = Output; 1 = Input
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Physical Libraries
❑ Contain physical information of
standard and macro cells necessary for
placement
❑ Define placement unit tile
• Height of placement rows
• Minimum width resolution
• Preferred routing directions
• Pitch of routing tracks
• …
reference point
(typically 0,0)
Dimension
“bounding box”
Pins
(direction, layer
and shape)
VDD
GND
A B
Y
NAND_1
Blockage
Symmetry
(X, Y, or 90º) F
Abstract View
Reference Libraries
(Milkyway)
FF
BUF
BUF
INV
NOR
unit tile
(site)
Double height cell

“CEL” vs. “Frame” Views
❑ A standard cell library also contains a corresponding abstract view for
each layout view
❑ Abstract views contain only the minimal data needed for Place & Route
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A B
Y
NAND_1
GND
VDD
Frame View
CEL View
B
VDD
GND
Y
A
origin
(typically 0,0)
Blockage
Symmetry
(X, Y, or 90º)
⌟
Pins
(direction, layer and
shape)
PR Boundary

Ease of Use: Tech-Only NDM Library
❑ The design library that will hold your design data during implementation must be
associated with technology information as well as RC parasitic models (TLU+)
❑ It is possible to create a technology-only NDM that is used as a container to store:
• Technology file
• RC parasitic model files (TLUPIus)
• Site symmetry and default site settings
• Routing track settings
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Technology File
❑ Tech File is unique to each technology
❑ Contains metal layer technology
parameters:
◦ Number and name designations for each
layer/via
◦ Dielectric constant for technology
◦ Physical and electrical characteristics of
each layer/via
◦ Design rules for each layer/Via
(Minimum wire widths and wire-to-wire
spacing, etc.)
◦ Units and precision for electrical units
◦ Colors and patterns of layers for display
◦ Via contact definitions
(lower/upper metal layers, metal
enclosure, etc.)
◦ Default via array rules
◦ Site definitions
Technology {
dielectric = 3.7
unitTimeName = "ns"
timePrecision = 1000
unitLengthName = "micron"
lengthPrecision = 1000
gridResolution = 5
unitVoltageName = "v"
}
...
Layer "m1" {
layerNumber = 16
maskName = "metal1"
pitch = 0.56
defaultWidth = 0.23
minWidth = 0.23
minSpacing = 0.23
...
abc_9m.tf
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Physical Technology Data
icc2_shell> check_physical_constraints
...
Physical Library: design_lib_orca
Routing layer : METAL width: 160 pitch: 410 space: 180
Routing Layer : METAL Resistance : 6.4e-05 Capacitance : 4.19e-05
Routing layer : METAL2 width: 200 pitch: 410 space: 210
Routing Layer : METAL2 Resistance : 3.7e-05 Capacitance : 2.23e-05
Routing layer : METAL3 width: 200 pitch: 515 space: 210
Routing Layer : METAL3 Resistance : 3.7e-05 Capacitance : 1.39e-05
...
pitch
width
spacing
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Timing is Based on Cell and Net Delays
❑ ICC calculates delay for every cell and every net
❑ To calculate delays, ICC needs to know each net’s parasitic Rs and Cs
Cell Delay = (Input Transition Time, Cnet + Cpin)
Net Delay = (Rnet, Cnet + Cpin)
0.5 ns
Cnet
Cpin
Rnet
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TLU+ Models
❑ IC Compiler calculates C and R using the
net geometry and the TLU+ look-up tables
❑ UDSM process effects modeled
TLU+
ICC, ICC II, FC
nxtgrd
Star-RCXT
UDSM Process Effects
▪ Conformal Dielectric
▪ Metal Fill
▪ Shallow Trench Isolation
▪ Copper Dishing:
• Density Analysis
• Width/Spacing
▪ Trapezoid Conductor
Single
Process File
(ITF)
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DSM Effects
UDSM Process Effects
▪ Conformal Dielectric
▪ Metal Fill
▪ Shallow Trench Isolation
▪ Copper Dishing:
• Density Analysis
• Width/Spacing
▪ Trapezoid Conductor
Conformal Dielectric
Chemical Mechanical Polishing (CMP)
STI - Not very relevant
for routing modeling
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Read TLU+ Models
❑ TLU+ models are generated by StarRC from itf
❑ The name (in this example maxTLU) is used in ICC II during implementation to associate the
model with the correct corner
❑ You can read and use as many TLU+ models as you like
• For example, emulation-fill TLU+, etc.
read_parasitic_tech -tlup abcl4_9T_Cmax.tluplus
-layermap abcl4_tf_itf.map -name maxTLU
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Mapping file
The Mapping File maps the .tf (ndm technology file) layer/via names to
Star-RCXT .itf layer/via names.
Layer "METAL" {
layerNumber = 14
maskName = "metal1"
…
DIELECTRIC cm_extra3 { THICKNESS=0.06 ER=4.2 }
CONDUCTOR cm { THICKNESS=0.26 WMIN=0.16 …}
DIELECTRIC diel1d { THICKNESS=0.435 ER=4.2 }
…
abc.itf
abc.tf
conducting_layers
poly poly
metal1 cm
metal2 cm2
…
abc.map
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Calculating Cell and Net Delay
❑ Now that R and C are known from TLU+,
the delays can be calculated
❑ For Cell Delays, only Ctotal / Ceff is needed
❑ Calculating Net Delay is done using Delay
Calculation algorithms: Elmore, Arnoldi
C1
R1
R2
R3
C3
C4
U2
U1
C2
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MACRO Symmetry
❑ A chip is divided into core rows in which standard cells are placed.
❑ The rows are usually placed in a flipped and abutted pattern, with alternating north (N), and
flipped south (FS) orientations.
❑ Standard cells are placed in the rows, in N or FS orientation, such that they share VDD rails and
VSS rails.
❑ Cells in the N row have the N orientation, whereas those in the FS row have FS orientation.
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Placement Sites and Symmetry
❑ The technology file does not contain information on:
• The symmetry requirements for cell placement
• The default site for floorplan initialization
❑ Set the site attributes as follows:
set_attribute [get_site_defs unit_st] symmetry {Y}
set_attribute [get_site_defs unit_st] is_default true
In the tech file:
Tile "unit__st" {
width = 0.152
height = 1.672
}
Tile "unit_hp" {
width = 0.174
height = 2.58
}
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Routing Direction and Track Offset
❑ The technology file does not contain the following routing information
• Preferred routing direction
• Routing track offset
❑ Specify the routing directions and track offsets:
set_attribute [get_layers {Ml M3 M5 M7}]
routing_direction horizontal
set_attribute [get_layers {M2 M4 M6 M8}]
routing_direction vertical
set_attribute [get_layers {Ml}] track_offset 0.03
set_attribute [get_layers {M2}] track_offset 0.04
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Track Offset Explained
❑ The track offset equals the distance from the standard cell edge to the center of the pin
• In the example below, the M1 track offset is the vertical distance between the cell’s
horizontal edge and the center of the closest M1 pin.
• The M2 track offset is the horizontal distance between the cell’s vertical edge and the
center of the closest M2 pin.

Tech Library Prep- icc2_lm_shell
create_workspace TECH_LIB -technology abcl4_9m.tf
read_parasitic_tech -tlup abcl4_9T_Cmax.tluplus -name maxTLU
read_parasitic_tech -tlup abcl4_9T_Cmin.tluplus -name minTLU
set_attribute [get_site_defs unit_st] symmetry Y
set_attribute [get_site_defs unit_st] is_default true
set_attribute [get_layers {Ml}] track_offset 0.03
set_attribute [get_layers {M2}] track_offset 0.04
set_attribute [get_layers {Ml M3 M5 M7}] routing_direction horizontal
set_attribute [get_layers {M2 M4 M6 M8}] routing_direction vertical
commit_workspace
Icc2_lm_shell
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Design Library
❑ Create a design library
• Specify the technology and cell libraries
• Created in memory only (by default)
lappend search_path ./x/y/libs ./x/y/tech
create_lib ORCA.dlib -technology abc14_9m_tech.tf
-ref_libs {hvt_std.ndm
svt_std.ndm
lvt_std.ndm
sram.ndm
ip.ndm
}
Design Library
OCRA.dlib
Technolo
gy
Standard
Cells
IP
cells
If –use_technology_lib is used, the technology library must be listed in –ref_libs
If you set lib.setting.on_disk_operation to true, create_lib writes to disk upon Creation
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Technology Information
❑ If using a technology library, you should ensure that it contains all the information that was
discussed in the NDM Part.
❑ If using a technology file, you need to apply TLU+, site, and routing track information in ICC II:
create_lib ORCA.dlib -technology abcl4_9m_tech.tf -ref_libs ..
read_parasitic_tech -tlup abcl4_9T_Cmax.tluplus -name maxTLU
read_parasitic_tech -tlup abcl4_9T_Cmin.tluplus -name minTLU
set_attribute [get_site_defs unit] symmetry Y
set_attribute [get_site_defs unit] is_default true
set_attribute [get_layers {Ml M2}] track_offset 0.03
set_attribute [get_layers {Ml M3 M5}] routing_direction horizontal
set_attribute [get_layers {M2 M4 M6}] routing_direction vertical
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Perform Automated Design Setup
❑ If You used DC for Synthesis, Consider using DC’s write_icc2_files to create all
necessary inputs for a seamless transfer of data to ICC II
(Verilog, UPF, floorplan, timing constraints, ...)
• The golden floorplan is the one created by ICC II write_floorplan –when specified, DC
only write incremental information (→ std cell placement, layer constraints)
• In ICC II, the following sets up the entire design:
dc_shell –topo> write_icc2_files –output ORCA_DC_icc2
-golden_floorplan ORCA_TOP.fp/floorplan.tcl
icc2_shell> source ORCA_DC_icc2/ORCA.icc2_script.tcl

Read the Netlist and Create a Design
Gate-Level Netlist
(Verilog)
Design Library
OCRA.dlib
Technolo
gy
Standard
Cells
IP
cells
lappend search_path ./x/y/netlist
read_verilog -top ORCA ORCA.v
link_block
Design View of the block,
Created when netlist is read in. ORCA.dlib:ORCA.design
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Load the Power Intent
❑ Unified Power Format (UPF) is an IEEE standard (1801)
❑ UPF defines the entire “power intent and structure” of a multi-voltage design
❑ The netlist that was read in will already contain multi-voltage (MV) components from
Synthesis, like level shifters (LS), isolation cells (ISO), retention registers
load_upf ORCA.upf
commit_upf

Timing Constraints
❑ “Timing Constraints” are required to communicate the design’s
timing intentions to IC Compiler
❑ They should be the same ones used for synthesis with Design Compiler
(preferably SDC)
create_clock –period 10 [get_ports clk]
set_input_delay 4 –clock clk
[get_ports sd_DQ[*]]
set_output_delay 5 –clock clk
[get_ports sd_LD]
set_load 0.2 [get_ports pdevsel_n]
set_driving_cell –lib_cell buf5
[get_ports pdevsel_n]
...
read_sdc timing_constraints.sdc
SDC = Synopsys Design Constraints

Specify Unused Routing Layers
❑ By default, ICC II uses all metal layers defined in the technology file
❑ If using fewer metal layers this can result in:
• Optimistic congestion analysis pre-route
• Inaccurate delay calculations due to inaccurate parasitic RC calculations
❑ Specify the unused or “ignored” layers for accurate congestion and timing analysis
before routing
set_ignored_layers -max_routing_layer M7
report_ignored_layers

Load Scan Chain Identification Information
❑ Load SCAN-DEF to help ICC II identify the scan chains and their re-ordering buckets
❑ Will be used during placement to re-order the scan chains to reduce congestion
read_def ORCA_scan.def
IN[0]
SCAN_IN
OUT[0]
SCAN_OUT
B D
IN[1] OUT[1]
E C A
F IN[0]
SCAN_IN
OUT[0]
SCAN_OUT
B D
IN[1] OUT[1]
E C A
F
Scan chain re-ordering
during placement

Connect PG Pins to Supply Nets
❑ Synthesis netlist has no P/G supply nets or
connections
❑ Must explicitly connect P/G pins to supply nets
• These are logical connections, not physical
metal routes
• P/G net names defined in UPF
➢ Use -net option with <port_pin_list> for
non-UPF designs
• This also connects tie-high/low pins to P/G
nets
1’b1
1’b0
Implicit Power/Ground
connections
Original netlist
representation
VDD
VSS
VDD
VSS
P/G connections
VDD
VSS
connect_pg_net
check_mv_design

Enable Use of Tie-High/Low Cells
❑ If tie-high/low inputs need
to be connected to tie-high/low cells,
enable this as shown here
❑ Tie-high/low cells will be inserted
during placement optimization
• The name of the reference library is determined by the library file name with the .ndm suffix
removed
⁃ E.g. std cell. ndm is named std cell: get_lib cells std cell/AND3*
set_dont_touch [get_lib_cells */TIE*] false
set_lib_cell_purpose -include optimization
[get_lib_cells */TIE*]
Tie-h/Tie-l pins connected
with VDD/GND
VDD
VSS

Multiple Modes and Corner
❑ Today’s chips must operate in multiple modes...
❑ ...and across multiple PVT corners
Test Mode
Hi-T Slow
Standby Mode
Functional Mode
High-Performance Mode Low Power Mode
Lo-T
Fast
Max
Leakage
Lo-T Slow Hi-T Fast

Concurrent MCMM Optimization
❑ ICC II allows concurrent optimization under multiple corner and mode combinations,
called scenarios
❑ Improves each violation in a scenario, while trying not to cause/increase a violation in
another scenario
FUNC
Mode
FUNC_SLOW
Scenario
= + +
Parasitic
View1
SLOW
Corner
Scenario 1
Scenario 2
Scenario 3
Scenario n
Scenario 4
Scenario 5
Concurrent MCMM optimization
Fixing setup
here ... ... will not cause a
hold violation here

Corners Shown Graphically
Delay
Operating Conditions
~ P / -V / T
Worst
PVT
Best
PVT
Setup and hold checks
performed here…
…and here
More PVTs (e.g., PVT 2,
PVT 3)
And on top of that, all
modes may be exercised
in every corner…

Creating Modes, Corners and Scenarios
❑ Define modes and corners first, then define scenarios, comprised of applicable
mode+corner combinations
❑ The last mode/corner/scenario created is, by default, the current one
create_mode func
create_mode test
create_corner ss125c ; # common corner to both modes
create_scenario -mode func -corner ss125c
create_scenario -mode test -corner ss125c
current_mode
test
current_corner
ss125c
current_scenario
test::ss125c
func test
ss125c
func::ss125c func::ss125c

Current Corner + Current Mode Current Scenario
❑ The current corner and mode determines
the current scenario, and vice versa:
• Switching the current corner or
mode changes the current scenario
• Switching the current scenario
changes current corner and/or mode
icc2_shell> current_corner
{ss_m40c}
icc2_shell> current_mode
{func}
icc2_shell> current_scenario
{func.ss_m40c}
icc2_shell> current_corner ff_125c
{ff_125c}
{func.ff_125c}
icc2_shell> current_scenario test.ff_m40c
{test.ff_m40c}
icc2_shell> current_mode
{test}
icc2_shell> current_corner
{ff_m40c}
The Current mode/corner/scenario affects
reporting and constraint loading only.
Optimization occurs concurrently among active
scenarios

Classifying Constraints
❑ Timing constraints are classified into four categories:
• Mode-specific
• Corner-specific
• Scenario-specific
• Global
Mode
Corner
Scenario
M1
C1
S1
G
L
O
B
A
L
Example:
M1 constraints:
create_clock
set_case_analysis
Global constraints:
set_ideal_network
C1 constraints:
set_operating_conditions
set_timing_derate
S1 constraints:
set_input_delay
set_driving_cell
set output delay

Commands Listed by Classification
Mode-Specific Corner-Specific Scenario-Specific Global
Constraints that define or
modify the topology of the
timing graph
Constraints that modify the
calculated delay on an object
Constraints that have a time,
load, resistance, or drive value,
and can refer to a modal object
(e.g. -clock)
Constraints that apply to all
corners, modes and
scenarios of a given netlist
create_clock
create_generated_clcck
group_path
set_case_analysis
set_cell_mode
set_clock_gating_check
set_clock_groups
set_clock_sense
set_data_check
set_disable_timing
set_false_path
set_latch_loop_breaker
set_max_delay
set_min_delay
set_multicycle_path
set_propagated_clock
Set_sense
set_aocvm_coef f icient
set_extraction_options
set_load
set_operating_conditions
set_parasitic_parameters
set_process_label
set_process_number
set_temperature
set_timing_derate
set_voltage
read_sdc
set_clock_latency
set_clock_trans.ition
set_clock_uncertainty
set_driving_cell
set_fanout_load
set_ideal_latency
set_ideal_transition
set_input_delay
set_input_transition
set-inax_capacitance
set_max_time_borrow
set-max_transition
set_min_capacitance
set_output_delay
set_path_margin
set_switching_activity
set_disable_clock_gating_check
set_dont_touch
set_dont_touch_network*
set_ideal_network
set_power_clock_scaling

Scenario Constraints
❑ PrimeTime, DC and ICC use only scenarios
• There is no concept of a mode or a corner
• Constraints are either scenario-specific or global
• Scenario constraints are typically in a single file
❖ Contains scenario, modal and corner timing constraints
❖ For example: Scenario funcss 125c: func_ssl25c.sdc
❑ ICC II has modes and corners, which are shareable among scenarios
❑ It is recommended to split SDC constraints into mode-, corner- and scenario-specific
constraint file
• Improves constraint loading efficiency (explained next), but is not required
❑ ICC II provides a few commands to simplify the transition to separate
scenario/mode/corner files

Loading Constraints
❑ For the most efficient scenario setup, you should split constraints into separate files
• These constraints are then loaded only once, even if shared across scenarios
• Faster load time with less memory required
❑ After the modes, corners, and scenarios are defined, populate them with constraints
• This ensures that no constraints are lost (put into default mode/corner/scenario)
current scenario Ml Cl current scenario M2 Cl
read sdc Cl corner.sdc read sdc M2 mode.sdc
read sdc Ml mode.sdc read sdc M2 Cl scenario.sdc
read_sdc Ml_Cl_scenario.sdc
read_sdc global_constraints.sdc

Use write_script to Separate Constraints
❑ If you inherit constraint files with mixed mode, corner and scenario constraints, use
write_script to help separate the constraints:
• Load the mixed constraint file for each scenario
• Execute write script, which creates a wscript directory, containing separate Tcl files for
each mode, corner, scenario and a file for global constraints
• When your netlist or floorplan changes, load the files during design setup
create mode Ml; create_mode M2;
create corner Cl; create_corner C2;
create scenario -name SI —mode Ml -corner Cl
create scenario -name S2 -mode Ml —corner C2
...
current_scenario SI
read_sdc SI.sdc
current_scenario S2
read sdc S2.sdc
...
write_script

Minimize Modes and Corners with Scenario Analysis
❑ If you do not know the correct corners and modes:
• Create unique modes and corners for each scenario
• Execute remove_duplicate_timing_contexts to find the minimum set of modes and
corners, remove the duplicates and re-assign the scenarios
• Execute write_script to capture the mode-, corner-, scenario-constraints
create mode Ml; create_mode M2;
create corner Cl; create_corner C2;
create scenario -name SI —mode Ml -corner Cl
create scenario -name S2 -mode Ml —corner C2
...
current_scenario SI
read_sdc SI.sdc
current_scenario S2
read sdc S2.sdc
...
remove_duplicate_timing_contexts
write_script
C1
S1
M1
C2
S2
M2
If M1 == M2
C1
S1
M1
C2
S2
M2

Check Timing Constraints
❑ The following commands are available for checking constraints:
• check_timing to check clock crossing, missing input/output delays, ...
• report_exceptions to identify paths with single-cycle timing exceptions: false paths,
multi-cycle paths, asynchronous min- or max-delay paths
• report_case_anaiysis to confirm the correct mode settings
• report_disabie_timing to identify paths with disabled timing arcs (these will not be
optimized for timing)
check_timing
foreach_in_collection mode [all_modes] {
current_mode $mode
report_exceptions
report_case_analysis
report_disable_timing
}

Reports Usually Apply to Current Scenario
icc2_shell> all_scenarios
{func.ff_125c func.ff_m40c ... test.ss_125c }
{func.ss_125c}
icc2_shell> report_case_analysis
Port/Pin Name User case analysis value
scan.enable 0
test_mode 0
icc2_shell> report_constraints -all__violators
late_timing
Endpoint Path Delay Path Required Slack Scenario
.../shift_reg[3][30]/D (SDFFARX2_LVT) 9.37 r 7.01 -2.35 func.ss_125c
icc2 shell> current_scenario test.ff__125c
{test.ff_125c}
icc2_shell> report_case_analysis
Port/Pin Name User case analysis value
occ_bypass 0
occ_reset 0
test_mode 1
icc2_shell> report_constraints -all_yiolators
early_timing
Endpoint Path Delay Path Required Slack Scenario
.../FIFO_RAM_1/A1[0] (SRAMLP2RW32x4) 0.10 f 0.16 -0.06 test.ff_125c

Controlling MCMM Timing Reports
❑ Report the single worst setup timing path among all path groups of all active setup-
enabled scenarios:
❑ Report the single worst setup timing path from among the listed and active corners,
modes or scenarios, respectively:
❑ Report the worst setup timing path for each and every active corner, mode, scenario or
path group respectively:
❑ Report the worst setup timing path for each listed and active corner, mode or scenario,
respectively:
report_timing
report_timing -corners "Cl C4"
report_timing -modes FUNC*
report_timing -scenarios "SI S2 S5 S6"
report_timing -report_by corner |mode|scenario|group
report_timing -report_by corner -corners "Cl C4"
report_timing -report_by mode -modes FUNC*
report_timing -report_by scenario -scenarios "SI 82 85 86"

Controlling Scenario Analysis / Optimization
❑ The create_scenario command creates a scenario, makes it active, and enables the
following analysis types:
• Setup and hold timing
• Leakage and dynamic power
• Max transition, max and min capacitance
❑ Placement, CTS and routing optimizations occur simultaneously on all active scenarios,
for their enabled analyses
❑ Use set_scenario_status to limit the analysis types or to make scenarios inactive before
compile
• See examples on next page

Examples: Modifying Scenario Status
create_scenario -mode mFUNC -corner cSLOW
create_scenario -mode mTEST -corner cSLOW
create_scenario -mode mFUNC -corner cFAST
create_scenario -mode mTEST -corner cFAST
# Disable setup timing analysis and optimization for the FAST corner scenarios;
# Disable leakage power analysis and optimization for the TEST mode scenarios:
set_scenario_status *cFAST -setup false
set_scenario_status mTEST* -leakage_power false
# For placement consider only SLOW corner scenarios:
set_scenario_status *cFAST -active false
place_opt
# For post-route analysis activate all scenarios and enable all analyses:
set_saenario_status * -active true -all
Without the -name switch,
scenarios are automatically
named mode::corner,e.g
mFUNC::cSLOW

Reporting Scenario Status Settings
icc2_shell> report_scenarios
...
Name Mode Corner Active Setup Hold Max_tran Max_cap Min_cap
------------------------------------------------------------------------------------------------
func.ff 125c * func ff 125c false false true true false true true true
func.ff_m40c * func ff m40c true false true true false true true true
func.ss 125c * func ss 125c true true true true true true true false
func.ss m40c * func ss m40c false true false true true true true false
test.ff 125c * test ff 125c false false true false false true true true
test.ss 125c * test ss 125c true true false false true true true false
------------------------------------------------------------------------------------------------
# Which scenarios will be optimized for setup timing?
icc2_shell> get_scenarios -filter active&&setup
{func.ss_125c test.ss_125c}
# Which scenarios will be optimized for hold timing?
icc2_shell> get_scenarios -filter active&&hold
{func.ff_m40c func.ss_125c}
# Which scenarios will be optimized for all DRCs?
icc2_shell> get_scenarios -filter active&&max_tran&&max_cap&&min_cap
{func.ff_m40c)0
Dynamic
Power
Leakage
Power

Defining Corner PVT by Operating Condition
❑ ICC II accepts set_operating_conditions to determine the PVT values for each
❑ This is an indirect method, relying on an operating condition model name to determine
the PVT numbers
set_operating_conditions ssOp95vl25c
Operating Condition
Name Process Temp Voltage Original DB Name Original DB Filename
-----------------------------------------------------------------------------------
ff0p95vn40c 1.01 -40.00 0.95 saed321vt_ff0p95vn40c saed321vt ff0p95vn40c.db
fflpl6vn40c 1.01 -40.00 1.16 saed321vt_fflpl6vn40c saed321vt_fflpl6vn40c.db
ff0p95vl25c 1.01 125.00 0.95 saed321vt_ff0p95vl25c saed321vt_ff0p95vl25c.db
fflpl6vl25c 1.01 125.00 1.16 saed321vt_fflpl6vl25c saed321vt_fflpl6vl25c.db
ss0p75vn40c 0.99 -40.00 0.75 saed321vt_ss0p75vn40c saed321vt_ss0p75vn40c.db
ss0p75vl25c 0.99 125.00 0.75 saed321vt_ss0p75vl25c saed321vt_ss0p75vl25c.db

Defining PVT Directly - Recommended
❑ It is recommended to use the direct method for clarity:
set_process_number 0.99
set_voltage 0.75 -object_list VDD
set_yoltage 0.95 -object_list VDDH
set_temperature 125
Operating Condition
-----------------------------------------------------------------------------------
ff0p95vn40c 1.01 -40.00 0.95 saed321vt_ff0p95vn40c saed321vt ff0p95vn40c.db
fflpl6vn40c 1.01 -40.00 1.16 saed321vt_fflpl6vn40c saed321vt_fflpl6vn40c.db
ff0p95vl25c 1.01 125.00 0.95 saed321vt_ff0p95vl25c saed321vt_ff0p95vl25c.db
fflpl6vl25c 1.01 125.00 1.16 saed321vt_fflpl6vl25c saed321vt_fflpl6vl25c.db

Reminder: NDM Cell Library Panes
❑ The CLIB merges logic and physical models
• Each .db characterized for a PVT Corner is represented as a "Pane“

Reporting Library Details: report lib
Full name: /global/files/ndm/saed32,ndm:saed32
File name: /global/files/ndm/saed32.ndm
Design count: 588
Timing data:
Power rails:
Index Name Type
0 <default> power
1 VDD power
2 VDDG power
3 VSS ground
Pane count: 2
Pane 0:
Process label: (none)
Process number: 0.99
Voltage for count: 3
Voltage for rail 0 (<default>) : 0 .75
Voltage for rail 1 (VDD) : 0.75
Voltage for rail 2 (VDDG): 0.75
Temperature: -40
Thresholds:
r/f InputDelay: 0.5/0.5 r/f OutputDelay: 0.5/0.5
1/h RiseTrans: 0.2/0,8 h/1 FallTrans: 0.8/0.2
TransDerate: 1
Source .db file: /global/files/NLDM/saed32hvt_ss0p75vn40c.db ...

VT Matching
❑ If the PVT does not match, the VT resolution function finds the closest VT match
between specified and available library panes
• As a result, if there is at least one timing model available for a cell instance,
whatever the nominal PVT, that cell instance will be timed
Four individual panes:
Closest VT match is selected
Note: It is not recommended
to tape out with anything but
exact PVT matches!

Use Process Labels to Help the Matching
❑ Use process labels to augment the PVT matching condition, for example when:
• Slow (ss) and fast (ff) process corners have the same P values
• Closest-match does not pick the PVT that you want (example shown next)
-----------------------------------------------------------------------------------
ff0p95vn40c 1 -40.00 0.95 saed321vt_ff0p95vn40c saed321vt ff0p95vn40c.db
ss0p95vn40c 1 -40.00 0.95 saed321vt_ss0p95vn40c saed321vt_ss0p95vn40c.db

Process Label Specification
❑ First, process labels are applied when Liberty libraries are loaded into Library Manager
❑ Next, process labels are specified as part of the design’s corner constraints
❑ The process label, when specified, supersedes the process number and limits VT
matching to only the set of panes with the specified label
icc2_im_shell> read_db -process_label fast saed32hvt_ff0p95vl25c.db
icc2_im_shell> read_db -process_label slow saed32hvt_ss0p95vl25c.db
icc2_shell> create_corner c_slow
icc2_shell> set_process_number -corner c_slow 1.0
icc2_shell> set_process_label -corner c_slow slow

Process Label Exercise
Pane Process
Number
Process
Label
Voltage Temperature Liberty File
0 1.0 slow 0.88 V 125 C .._slow_0p88v_125c.db
1 1.0 fast 0.90 V 125 C .._fast_0p90v_125c.db
2 1.0 slow 0.95 V 125 C .._slow_0p95v_125c.db
3 1.0 slow 1.00 V 125 C .._slow_lp00v_125c.db
4 1.0 fast 1.00 V 125 C .._fast_lp00v_125c.db
create_corner c_slow
set_process_number 1.0
set_voltage -object VDDG 0.9
set_temperature 125
create scenario -name s_func_slow -mode m_func -corner c_slow
Scenario s_func_slow will be used for setup optimization:
Which pane is selected?
## add a process label
set process label -corner c slow slow
Which pane is selected now?

Reporting ALL Corners with PVT Mismatches

Selective Library Loading
❑ In past ICC II releases, all timing panes were loaded into memory
• Libraries with high pane counts, even if unused, can use up considerable memory and
lead to slight runtime degradation
❑ With 2017.09, ICC II can now load just the required panes
• This allows your team to use “one-size-fits-all” cell libraries that
❑ support multiple projects, rather than project-specific libraries
• Requires that the cell libraries are built using ICC II Library Manager >= 2017.09

Using Selective Library Loading
❑ To use selective loading, use set_pvt_configuration to specify the PVTs you will use
across your defined corners
• For a given library, the tool loads only the matching panes
➢ The unused panes remain on disk
• If you have a 132-pane library but your configuration matches only 8 panes, your in-
memory library has just those 8 panes
# Configure PVTs before you open or create your design library
set_pvt_configuration -voltages {0.75 0.95} -temperatures {-40 125}
-process_numbers 1.0 -process_labels {slow fast}
create_lib -ref_libs {all_panes.ndm ...} ...
read_verilog ...
# Flow continues as usual. Library in ICC II appears to only contain the timing
# panes that match above PVT configuration

Specify TLUplus Parasitic RC Models
❑ Specify the appropriate TLUplus model for each corner
• TLUplus models must have been previously loaded into a technology-only library, or into
the design library .
# If the TLUplus models have not been loaded into a technology library,
# they can be loaded into the design library:
# read_parasitic_tech -tlup $TLUPLUS_MAX_FILE -name maxTLU
# read_parasitic_tech -tlup $TLUPLUS_MIN_FILE -name minTLU
# Specify the TLUplus model for each comer;
# If the TLUplus models were loaded into the tech lib use the -library option:
set_parasitic_parameters -corner c_slow
-library ${techlib} -early_spec maxTLU -late_spec maxTLU
set_parasitic_parameters -corner c_fast
-library ${techlib} -early_spec minTLU -late_spec minTLU

Restricting Cells in Specific Modules/Regions
❑ Specific modules or design regions may need to be restricted to use a sub-set of all
available reference library cells, for example:
• Only cells with a double site height
• Only high or low-speed cells
• No ultra-LVth cells allowed
❑ Use set_target_library_subset for these purposes
• See following example

Target Library Subset Example
❑ Sub-design Subl/suba is timing-critical and can use LVT cells in addition to SVT/HVT
cells, while the rest of the design uses only SVT/HVT cells
set_target_library_subset -top {lib_HVT lib_SVT}
set_target_library_subset -OBJECTS Sub1/suba {lib_HVT lib_SVT lib_LVT}
Pre-existing LVT cells at top are not affected unless they are optimized

On-Chip Variation
❑ On-Chip Variation (OCV) has different sources and types
❑ The impact on IC operation increases in parallel with shrinking IC technology
❑ It is critical and cannot be ignored
Intra-Die Intra-Cell
OCV
Purely random
Intra-Die Intra-Cell
Retical

Interconnects Variations
❑ In addition to device variations, the characteristics of interconnect
also vary significantly for 90nm and below technologies.
❑ Interconnect variations can be local and global. The figure shows
interconnects in different metal layers.
❑ Usually, local interconnects are realized by lower metal layers, and
global – higher.
❑ In the case of interconnect, OCV is related to variation in
interconnect height and width, resulting in variation in both
resistance and capacitance.
❑ Inter-layer Dielectric (ILD) thickness variations are also significant
in 90nm technologies, which contribute to the overall interconnect
electrical delay variations. The figure demonstrates variations in ILD
thickness across wafer and die. The variation in metal thickness and
oxide thickness contribute to coupling capacitance and plate
capacitance changes respectively.
❑ Since the delay attributed to the interconnect is becoming a more
dominant delay as geometries shrink, particular attention should be
paid to accurate modeling of interconnect variations.
Metal thickness
Metal width and
spacing
Metal resistivity
Dielectric thickness
Dielectric constant
Substrate
Er=3.9
GOX
FOX (0.1)
D1 (0.6)
D2 (0.6)
D3 (0.6)
D4 (0.6)
D5 (0.6)
D6 (0.6)
D7 (0.6)
D8 (0.6)
D9 (0.6)
PASS (3.00)
M1
M2
M3
M4
M5
M6
M7
M8
M9
Er=3.9
Er=3.9
Er=3.9
Er=3.9
Er=3.9
Er=3.
Er=3.9
Er=3.9
Er=3.9
Er=3.9
VIA1
VIA2
VIA3
VIA4
VIA5
VIA6
VIA7
VIA8
n+ n+
Gate
POLYCONT
DIFFCONT
MRDL
VIARDL

Increase of OCV Relative Impact
Tox (A) Tox (A) Tox/Tox Lg (nm) L (nm) L/L
130nm 22 1 4.5% 130 5 3.1%
90nm 16 1 6.3% 90 5 5.6%
65nm 12 1 8.3% 65 5 7.7%
45nm 10 1 10.3% 40 5 10.3%
32nm 8 1 12.3% 25 5 13.6%
L (nm) 250 180 130 90 65 45
Vt (mV) 450 400 330 300 280 200
-Vt (mV) 21 23 27 28 30 32
(-Vt)/Vt 4.7% 5.8% 8.2% 9.3% 10.7% 16%

On-Chip Variation
❑ It is known that constructing a cell on SoC is a
process that involves many variables. These
variables change in four ways.
• Some of the variables are fairly consistent for
the entire manufacturing process.
• Some of the variables vary from lot to lot but
are consistent across a single lot of wafers.
• Still other variables vary from wafer to wafer
but are consistent across a chip.
• And finally, some of the variations can occur
within a single chip.
❑ As a rule, many variables involved in the
manufacturing process mean the gate delay of
a cell is a Gaussian distribution with a mean
and standard deviation determined by the cell
design and these many variables. A randomly
chosen instance of a cell on a randomly chosen
chip could be running at any point within that
Gaussian distribution.
200 225 250 275 300 325 350
Gate Delay (ps)
Process
WC chip
BC chip

Necessity of OCV Consideration
DFF DFF
0.6/0.1 0.6/0.1 0.65/0.1 0.6/0.95
PLL
Smaller delay Larger delay
0.6/0.1 0.6/0.1 0.65/0.09 0.6/0.09
Thick Interconnect
(lowR)
Thin Interconnect
(highR)
W/L

Necessity of OCV Consideration (2)
❑ Here another example is illustrated that confirms that OCV can have a great impact on
the IC’s general characteristics. For example, this figure shows the arrival time
variation of connected buffers in the function of the number of stages.
❑ If each gate would vary completely independent of each other then according to the
statistics, the width of the real arrival distribution would increase with the square root of
the number of stages.
Arrival variation
1 2 3 4
Path stage
Real arrival
distribution

Worst slew variation
Parasitics variation
min max
Receiver pin cap variation
Slew variation Driver cell variation
Coupling cap variation
min max
Driver cell variation
Victim
Aggressor

ffb ffc
Clk
n2
W1
6 7 8 9
7 8 9 10
9 10 11 12
ffa
CP
Clk
Clk
n1
W2
W0

OCV Effects on Timing
❑ PVT variation across the die, or “on-chip variation” (OCV), causes timing variations
❑ OCV can cause real timing violations to be missed, if not considered during analysis and
optimization- consider the following extreme example:
❑ Process variations are
random in nature
• Can vary from transistor
to transistor
❑ Voltage and temperature
variations are systemic
• Increase with distance
between related cells

Modeling Variation
random
total
Variations
Deterministic models
=> predict variations
Deterministic models don’t exist.
Known min-max range or
distribution
Systematic Random
w/o systematic
e.g. T/V e.g. doping

Traditional Timing Derate Method for Modeling
OCV
• LATE derate: Slows down launch paths for setup, and capture paths for hold
• EARLY derate: Speeds up capture paths for setup, and launch paths for hold
• Can focus on data or clock logic, net or cell delays, etc.
Commonly only one library is available per SLOW or FAST corner
→Apply estimated derating to model the combined effects of PVT variations
set_timing_derate –late 1.04
set_timing_derate –early 0.92

Example: OCV Analysis with Timing Derate
# In the SLOW PVT Corner:
set_timing_derate –late 1.04
set_timing_derate –early 0.92
U6
_RESET
CLK1
CLK2
FF1
U1 U2
U3
U7
FF2
U4 U5
Launch Path
Capture Path
8% Faster
Slow corner
Fast corner
4% Slower
Delay
Operating Conditions
~ P / -V / T
8% Slower
4% Faster
Models an 8% speed-up and
a 4% slow-down from the
slow PVT corner
Setup
Launch uses late derate:
1.04 x slow corner delays
Capture uses early derate:
0. 92 x slow corner delays
Hold
Launch uses early derate:
Capture uses late derate:

Derate Factor in Timing Report
set_timing_derate -early 0.92
set_timing_derate -late 1.04
report_timing -path full_ clock -derate
Point Derate Incr Path
--------------------------------------------------------------------------
clock CLK (rise edge) 0.0000 0.0000
clock source latency 0.0000 0.0000
CLK (in) 0.0000 & 0.0000 r
U1/I (BUFFD1) 1.04 0.0000 & 0.0000 r
U1/Z (BUFFD1) 1.04 0.2667 & 0.2667 r
U2/I (BUFFD1) 1.04 0.0000 & 0.2667 r
U2/Z (BUFFD1) 1.04 0.1092 0.3758 r
FF1/CP (DFD1) 1.04 0.0000 0.3758 r
FF1/Q (DFD1) 1.04 0.2587 & 0.6345 f
FF2/D (DFD1) 1.04 0.0000 & 0.6345 f
data arrival time 0.6345
clock CLK (rise edge) 5.0000 5.0000
clock source latency 0.0000 5.0000
CLK (in) 0.0000 & 5.0000 r
U1/I (BUFFD1) 0.92 0.0000 & 5.0000 r
U1/Z (BUFFD1) 0.92 0.1942 & 5.1942 r
U2/I (BUFFD1) 0.92 0.0000 & 5.1942 r
U2/Z (BUFFD1) 0.92 0.0950 5.2892 r
FF2/CP (DFD1) 0.92 0.0000 5.2892 r
clock reconvergence pessimism 0.0866 5.3758
library setup time 1.00 -0.0076 5.3683
data required time 5.3683
--------------------------------------------------------------------------
data required time 5.3683
data arrival time -0.6345
--------------------------------------------------------------------------
slack (MET) 4.7338
Launch Path
Capture Path

Timing Pessimism with OCV Analysis
The “min-max” OCV delay range of BF1 in the SLOW corner is 90-100 ps:
1. Assume the above OCV is modeled by early/late derating:
If the launch and capture clock paths each contain ten BFI buffers, setup timing analysis
assumes:
a. 900 ps for launch path; 1000 ps for capture path
b. 1000 ps for launch path; 900 ps for capture path
2. On actual silicon, the more realistic total delay for ten BFI buffers will be between 900ps
and 1000ps. Therefore, OCV timing analysis is:
a. Optimistic
b. Pessimistic
3. The closer the cells are physically placed to each other:
a. The larger their systemic V/T variations can be
b. The smaller their systemic V/T variations can be
4. Since process (P) variation is random, its effects are smaller in a path with:
a. 30 BF1 cells
b. 3 BF1 cells
BF1 BF1 BF1 BF1 BF1 BF1 BF1 BF1
BF1 BF1

Timing Pessimism with OCV - CRPR
❑ Clock reconvergence pessimism (CRP) is a difference in delay along the
common part of launching and capturing clock path when you simultaneously
use minimum and maximum delays during on-chip variation analysis.
❑ It is an accuracy limitation in timing analysis.
❑ Automated correction of clock reconvergence pessimism is called clock
reconvergence pessimism removal (CRPR).

AOCV Calculates Derating Based on Depth
and Distance
❑ Advanced On-Chip Variation provides more realistic variable derating by taking path
depth and distance into account
• Random P variation modeled as a
function of logical path depth
• Systemic V/T variation modeled as a
function of the maximum physical distance
between related timing path cells and nets
Depth 1 2 3 4 5 …
Variable
Derate
1.214 1.153 1.109 1.075 1.056 …
Flat
Derate
1.15 1.15 1.15 1.15 1.15 …

Enabling Advanced On-Chip Variation Modeling
❑ AOCVM reduces excessive timing margin or pessimism
❑ If you have AOCVM tables, use them!
set_app_options -name time.aocvm_enable_analysis -value true
set_app_options -name time.ocvm_enable_distance_analysis -value true
read_ocvm -corners SLOW SLOW_derate_table
read_ocvm -corners FAST FAST_derate_table
report_ocvm -type aocvm
Derate tables
provided by your
library supplier

Graph-Based Analysis (GBA) VS Path-Based
Analysis (PBA)

Pessimism in Graph-Based Analysis
(GBA) AOCV

Parametric On-Chip Variation Modeling of
Random Variation
❑ POCV does not rely on path depths to model random variation- instead uses a Gaussian
Distribution model for individual cell delays
• Each cell has a nominal or mean (m) delay and a standard deviation (σ) delay value (σ is
also called sensitivity)
❑ The cumulative delay of a path is
determined by statistically adding the
delay distribution of each stage
❑ Eliminates GBA-based pessimism

POCV Input Data: Sigma (a) - Two Formats
❑ LVF: Cell delay variation or o (time units) is
modeled as a function of input transition and
output load per timing arc
• For finer geometries ( <= 20nm ) and low
voltage, delay variation(s) can strongly
depend on the input slew and output load
❑ The POCV Coefficient is
characterized by a particular input
transition and output load per
library cell (σ = C * m)
• No delay variation dependency to
input transition and output load

POCV Path Calculation Example
Timing analysis uses 3 sigmas, by default:
Data Arrival or Required𝑙𝑎𝑡𝑒 = 𝑚𝑝𝑎𝑡ℎ + 3 * 𝜎𝑝𝑎𝑡ℎ
Data Arrival or Required𝑒𝑎𝑟𝑙𝑦 = 𝑚𝑝𝑎𝑡ℎ - 3 ∗ 𝜎𝑝𝑎𝑡ℎ
Slack = 𝑚𝑠𝑙𝑎𝑐𝑘 − 3 ∗ 𝜎𝑠𝑙𝑎𝑐𝑘

POCV Input Data: Distance-based Derating
❑ Systemic or distance-based (V/T) derating factors can also be taken into account in
POCV, and can also be specified in two formats:
• The distance derate factor is applied to
the mean delay, independent of the Sigma delay

POCV Setup
❑ Both POCV formats can be applied at the same time
• POCV LVF library (→.db/NDM) on some cells and POCV side file on others
set_app_options -name time.pocvm_enable_analysis -value true
set_app_options -name time.ocvm_enable_distance_analysis -value true
# POCV data can be in LVF or in side files:
read_ocvm -corners SLOW SLOW_pocv_coefficient_file
read_ocvm -corners SLOW SLOW_Pocv_distance_table
report_ocvm -type pocvm
report_timing -variation

POCV Additional Setup
❑ If your LVF contains setup/hold constraint variation data, use:
❑ If your LVF contains output slew variation tables, use:
❑ Modify the number of sigmas (𝜎) for timing analysis, if needed:
• By default, timing analysis (and report_timing)uses values at 3 standard deviations (3 𝜎)
from the mean
• Increasing a tightens, and decreasing a relaxes the timing requirement
set_pocvm_corner_sigma -corners {ff_corner} 4.0
report_ocvm -type pocvm —corner_sigma -corner ff_corner
time.enable_constraint_variation
time.enable_slew_variation
Default: false
Default: false

Perform a 'Timing Sanity Check'
❑ Before starting placement it is important to ensure that the design is not over-
constrained
• Constraints should match the design’s specification
❑ Report ‘ZIC’ setup timing before placement
• Check for unrealistic or incorrect constraints
• Investigate large zero-interconnect timing violations
set_app_options -list {
time.delay_calculation_style zero_interconnect
time.high_fanout_net—pin_capacitance OpF
time.high_fanout_net_threshold 32
}
update_timing -full
report_constraints -all_violators -max_delay
report_qor -summary -include setup
report—timing -slack_lesser_than 0
Use if design
has unbuffered
high fanout
nets
Use one of
these reports to
get the WNS

What is a Gate in “Gate-level Netlist”?
Gate: Basic Logic Component
Other Gates:
Buffer, Nand, Nor, Xor, AOI, Mux, D-FF, Latch, etc
Inverter Gate (or Logic) Level
Schematic
Input “A” Output “Z”
INV1
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Transistor or Device Representation
Gates are made up of active devices or transistors.
CMOS Inverter Example
OUT
IN
Gate Schematic
IN OUT
PMOS
NMOS
Transistor or Device View
VDD
GND
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Basic Devices and Interconnect
❑ Integrated circuits are built out of active and passive
components, also called devices:
◦ Active devices
◦ Transistors
◦ Diodes
◦ Passive devices
◦ Resistors
◦ Capacitors
❑ Devices are connected together with polysilicon or metal
interconnect:
◦ Interconnect can add unwanted or parasitic capacitance, resistance and
inductance effects
❑ Device types and sizes are process or technology-specific:
◦ The focus here is on CMOS technology
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What is “Physical Layout”?
Physical Layout – Topography of devices and interconnects, made up of
polygons that represent different layers of material.
CMOS Inverter Example
IN OUT
PMOS
NMOS
Transistor or Device View
VDD
GND
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NMOS
PMOS
OUT
VDD
GND
Physical or Layout View
IN

Layout or Mask (aerial) view
Silicon Substrate
Process of Device Fabrication
❑ Devices are fabricated vertically on a silicon substrate wafer by layering
different materials in specific locations and shapes on top of each other
❑ Each of many process masks defines the shapes and locations of a
specific layer of material (diffusion, polysilicon, metal, contact, etc)
❑ Mask shapes, derived from the layout view, are transformed to silicon
via photolithographic and chemical processes
Wafer (cross-sectional) view
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Wafer Representation of Layout Polygons
Example of complimentary devices in 0.25 um CMOS technology or process.
Input
VDD
GND
Output
PMOS
NMOS
0.25 um
Aerial or Layout View Wafer Cross-sectional View
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What is Meant by “0.xx um Technology”?
- In CMOS Technology the um or nm dimension refers to the channel length, a
minimum dimension which is fixed for most devices in the same library.
- Current flow or drive strength of the device is proportional to W/L; Device size or
area is proportional to W x L.
Gate or Channel Dimensions (L and W)
Narrower
Width
=
Lower
current
through
channel
Length
Width
G
A
T
E
W
L
L
Width (W)
Wider
Width
=
Higher
current
through
channel
G
A
T
E
Length
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Comparing Technologies
The drive strength of both devices is the same: W/L = 6. The diffusion
area (5xLxW) of A is 4x that of B. Which is preferred?
A: 0.5 um Technology
L = 0.5 um
2L 2L
W = 3 um
L = 0.25 um
W = 1.5 um
2L 2L
B: 0.25 um Technology Area Comparison
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Relative Device Drive Strengths
To double the drive strength of a device, double the channel width (W), or
connect two 1X devices in parallel. The latter approach keeps the height at a
fixed or “standard” height.
“1X” NMOS (W/L = 6)
GND
OUT
L = 0.25 um
W = 1.5 um
IN
0.25 um
GND
3 um OUT
IN
“2X” NMOS (W/L = 12)
1.5 um
GND
0.25 um
OUT
IN
“2X” NMOS (W/L = 6 + 6)
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Input Output
Gate Drive Strength Example
PMOS
transistor
1x
NMOS
transistor
Input Output
Parallel PMOS
transistors
2x
inv1 inv2
Parallel NMOS
transistors
Each gate in the library is represented by multiple cells with different drive
strengths for effective speed vs. area optimization.
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Logical DRC
1x 2x 1x
1x
1x
Maximum Transition Rule
Violation
Maximum Transition Rule
Met
Upsized Driver or Added Buffers
After
Optimization
Before
Optimization
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Quiz 1: Technology
A 90 nm technology implies that:
a. Cell phones built with this technology can receive signals up
to 90 nautical miles away.
b. The minimum channel width for all transistors is 90nm.
c. The maximum channel length is 90nm.
d. The minimum width of a polysilicon trace is 90nm.
e. None of the above.
Length
Width
G
A
T
E
W
L
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Quiz 2: Technology
Which of the following is true:
a. B has the same area as A and double the drive.
b. B has double the area of A and half the drive.
c. B has the same area as A and the same drive.
d. B has 4X the area as A and and the same drive.
e. None of the above.
A: W/L = 2/0.5 B: W/L = 4/0.25
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Contacts: Connecting Metal 1 to Poly/Diff’n
Diffusion, Poly and Metal layers are separated by insulating oxide. Connecting
from Poly or Diffusion to Metal 1 requires a contact or cut.
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Cut or
Contact (a
hole in the
oxide)
VDD
IN
GND
Diffusion Diffusion
Poly
Oxide insulation Metal 1
Metal 1

Channel-Based Routing
❑ Cells are abutted in rows
❑ Routing is in channel area only
❑ Overall chip requires more area to allow for
channels
❑ Older P&R technology
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BUF2B
VDD
VSS
MUX21
VDD
VSS
INV1
VDD
VSS
NOR3
VDD
VSS
XOR2
VDD
VSS
INV1
VDD
VSS
NA21
VDD
VSS
INV1
VSS
VDD
JKF
F
VSS
VDD
DFFSR
1
VSS
VDD
AOI221
VSS
VDD
AND2
VSS
VDD
INV1
VSS
VDD
AND2
VSS
VDD
DFFSR1
VSS
VDD
AOI221
VSS
VDD
JKFF
VSS
VDD
BUF2B
VDD
VSS
NOR3
VDD
VSS
NA21
VDD
VSS
INV1
VDD
VSS
INV1
VDD
VSS
XOR2
VDD
VSS
MUX21
VDD
VSS

Area-Based Routing
❑ Newer P&R technology
❑ Same area is used for placement
and routing (over the cell)
❑ More efficient use of chip real
estate
❑ Requires additional metal layers
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Routing Blockages
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MACRO
Metal 2
blockage
Metal 2
blockage
Metal 3
blockage
Metal 3
blockage
Metal 3
blockage
Metal 2
Routing
Metal 3
Routing
MACRO
CORE AREA

References
❑ CMOS VLSI Design: A Circuits and Systems Perspective 4th Edition by Neil Weste, David Harris.
❑ Synopsys slides
❑ Cadence slides
❑ CMPE 641: Topics in VLSI
❑ Team VLSI
❑ A year of experiences
❑ …….
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5. Data and Timing Setup Introduction.pdf

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