1. Introduction to PnR.pptx

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Introduction to PnR
Ahmed Abdelazeem
1
NTI - National Telecommunication Institute

Index
1. Introduction to VLSI
2. ASIC Design
• Design approaches
• ASIC VS FPGA
• ASIC Cost
• Fabless VS FABs
3. CMOS Basics
• CMOS Characteristics
• Delay in CMOS circuits
• Power in CMOS circuits
4. Basics of Microfabrication
5. Introduction to PnR
6. Standard Cell libraries
7. Analysis Corners
2

Cell-Based Design Flow
• Front-End “Digital Design”
1. System specification and architecture
2. HDL (verilog or VHDL) coding
 Behavioral simulations using RTL (HDL)
3. Synthesis
4. Gate-level simulations
• Back-End “Digital Implementation”
1. Floorplanning, Power grid design
2. Standard-cell Placement
3. Interconnect routing
4. DRC (Design Rule Check)
5. LVS (Layout vs Schematic)
6. Static timing analysis
3
Logic synthesis
Place&Route
Gate-Level netlist
Post layout
Gate-Level netlist
GDS layout
RTL code
always @ (posedgeclk)
if (in1==1)
a=c+d
else
a=c-d
Formal
Formal
LVS
RTL Simulation
Lint check
code coverage analysis
Gate level Simulation
Static Timing Analysis
Power Analysis
Gate level Simulation
Static Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level Simulation
Transistor-level STA
Power Analysis
Implenentation Verification

Motivation
4
First Integrated circuit,
1964 The Intel 4004, 1971
2,300 Transistors
The Intel 486 DX2, 1992
1.2M Transistors
Itanium 2 “Montecito”,
2006
1.7B Transistors

Motivation
5
Apple M2
Introduced 2022
Technology TSMC 5nm
memory 2MB L1
20MB L2$
8MB L3$
Cores 8
Threads 16
Frequency 2.42- 3.5 GHz
Die Size 141.7 mm2
#Transistors 20 B
Apple_M2

Motivation
• Hummmm!!, we have a problem…
6
“Moore’s Law of Engineers”
Logic
transistors
per
chip
“in
Millions”
Productivity
Trans./
Stuff-Mo

Motivation
• How on earth do we design such a thing???
7

The Solution
8
Design
Abstraction
Design Reuse
(IP)
Design
Automation
(EDA)

Introduction to VLSI
Very large-scale integration (VLSI)
Various circuit elements: transistors, capacitors, resistors , and
even small inductances can be integrated on one chip.
• Integrating different devices on the same chip enhances
performance and decreases area.
• SoCs allows semiconductor manufacturers to build smaller
and simpler systems embedded in a single chip, resulting in a
reduction of cost and increased efficiency of a particular
system as opposed to its equivalent board-level system, built
with standard parts and additional components.
9

Moore’s Law
• Moore’s Law predicts that the number of transistors
per device will double every two years.
• Moore's prediction has been used in the
semiconductor industry to guide long-term planning
and to set targets for research and development, thus
functioning to some extent as a self-fulfilling
prophecy.
• Moore’s Law is and always has been driven by
innovation.
10

“Moore’s Law is alive and well”
11

VLSI Design Styles
• Due to time and cost constraints, very few teams and/or companies develop products from device level
through to system level.
• Various Design Styles are available to shorten the time-to-market and development cost.
• Trade-offs are taken into consideration, as abstractions are usually designed generically and therefore come
with some overhead.
• In the following slides, we will briefly discuss:
1. Full custom design
2. Standard Cell based ASIC design
3. Field-Programmable Gate Array (FPGA) design
4. Microprocessor (Software)
12

ASIC
Application-Specific Integrated Circuit (ASIC)
• is an integrated circuit (IC) chip customized for a
particular use, rather than intended for general-
purpose use. 100’s of millions of logic gates can be
integrated on the same chip using ASICs to create
incredibly large and complex functions.
 Example: Cell Phone SoC
• Due to the extremely expensive cost of building a
new silicon foundry , many companies work in
design only and few companies specialize in
fabricating their designs.
13

The VLSI Design Ecosystem
14
ASIC

VLSI Design Styles – Full Custom
Full Custom Design
A design methodology useful for integrated circuits. In
this design, the resistors, transistors, digital logic,
capacitors and analog circuits are all positioned in the
circuit layout.
• Design all by yourself
• Analog Design, and Standard Cell.
• Pros “highest degree of flexibility”
- Higher performance
- Lower energy per workload (lower power)
- Smaller chip area.
• Cons
- Huge design effort
- High Design cost and NRE cost.
- Design is frozen in silicon, and
- Long time to market..
15

VLSI Design Styles – Semi-Custom
Semi-Custom [Standard Cell Based ASICs]
• Design using standard cells
• Standard cells come from library provider
• All logic cells are predesigned, and some mask layers
are only customized
• HDLs are mapped to Libraries
• Pros.
- Many different choices for cell size, delay, leakage power
- Many EDA tools to automate this flow
- Shorter design time.
16

VLSI Design Styles – FPGA
• FPGA – Field Programmable Gate Array
1. Array of configurable logic blocks, and
programmable interconnect structures
2. Fast prototyping, cost effective for low volume
production
3. HDL (hardware description language) –
is used
17

Design Styles – Pros and Cons
• Full Custom Design:
1. Customization for optimized power, performance, area.
2. High complexity = cost, time-to-market, high risk.
• Standard Cell:
1. Simple, fast, reliable.
2. Only Digital designs. Excess power, wirelength, etc.
• FPGA:
1. Post silicon configurability, very inexpensive.
2. High percentage of overhead. High cost per chip.
• Microcontroller (Software)
1. Programmable, very inexpensive
2. Very slow compared to hardware implementation.
18

ASIC Cost
• Total Product Cost = NRE + (Number of parts ∗ recurring cost per part)
1. NER “Fixed Non-Recurring Engineering cost”
• EDA tools and training.
• Project Development/Verification cost.
a. Analog design and layout design, Logic synthesis, DFT/ATPG, PnR.
b. Formal verification, logic simulation, functional simulation, Co-simulation, Physical verification, EMIR,
Static Timing Analysis.
c. A single EDA tool license can cost hundreds of thousands of dollars.
d. ASIC vendor costs (ex. masks).
2. Unit Cost
• Wafer cost.
• Wafer processing.
• Production yield.
• Packaging.
• Testing
19

Exercise 1
• What is the best design approach for implementing each of the following: [hint: you can use a mix of
approaches when needed]
1. ADC
2. Microcontroller
3. AI accelerator HW testing and prototyping.
4. Mobile application chip.
5. Medical and Aerospace applications. [Low volume and high complexity]
20

Exercise 2
• What makes an FPGA relatively consumes more power than a corresponding ASIC?
• What makes an FPGA relatively has less performance (Fmax) than a corresponding
ASIC?[Please list 3 reasons at least]
• When can we consider the high NRE cost of ASIC development make sense economically?
21

CMOS
• CMOS is the most commonly used technology in
integrated Circuits
• It uses complementary and symmetrical pairs of p-
type and n-type MOSFETs
• No power dissipation at steady state. [Ideally!]
• CMOS is the dominant technology for IC fabrication
mainly due to its efficiency in using electric power
and versatility.
22

Transistor Operation
• Current depends on region of transistor behavior
• For what 𝑉𝑖𝑛 and 𝑉𝑂𝑈𝑇 are NMOS and PMOS in
I. Cutoff ?
II. Linear ?
III.Saturation ?
𝐼𝑑 =
0, 𝑉
𝑔𝑠 < 𝑉𝑇𝐻 𝐶𝑢𝑡𝑜𝑓𝑓
𝛽 𝑉𝐺𝑇 −
𝑉𝑑𝑠
2 𝑉𝑑𝑠, 𝑉𝑑𝑠 < 𝑉𝑑𝑠𝑎𝑡 𝐿𝑖𝑛𝑒𝑎𝑟
𝛽
2
𝑉𝐺𝑇
2
, 𝑉𝑑𝑠 > 𝑉𝑑𝑠𝑎𝑡 𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛
𝛽 = 𝜇𝐶𝑜𝑥
𝑊
𝐿
𝑉𝐺𝑇= 𝑉
𝑔𝑠 − 𝑉𝑇𝐻
23

CMOS Operation
24
Cutoff Linear Saturation
NMOS
𝑉
𝑔𝑠𝑛 < 𝑉𝑡ℎ𝑛
𝑉𝑖𝑛 < 𝑉𝑡ℎ𝑛
𝑉
𝑔𝑠𝑛 > 𝑉𝑡ℎ𝑛
𝑉𝑖𝑛 > 𝑉𝑡ℎ𝑛
𝑉𝑑𝑠𝑛 < 𝑉
𝑔𝑠𝑛 − 𝑉𝑡ℎ𝑛
𝑉𝑜𝑢𝑡 < 𝑉𝑖𝑛 −𝑉𝑡ℎ𝑛
𝑉
𝑔𝑠𝑛 > 𝑉𝑡ℎ𝑛
𝑉𝑖𝑛 > 𝑉𝑡ℎ𝑛
𝑉𝑑𝑠𝑛 > 𝑉
𝑔𝑠𝑛 − 𝑉𝑡ℎ𝑛
𝑉𝑜𝑢𝑡 > 𝑉𝑖𝑛 −𝑉𝑡ℎ𝑛
PMOS 𝑉
𝑔𝑠𝑝 > 𝑉𝑡ℎ𝑝
𝑉𝑖𝑛 > 𝑉𝐷𝐷 + 𝑉𝑡ℎ𝑝
𝑉
𝑔𝑠𝑝 < 𝑉𝑡ℎ𝑝
𝑉𝑖𝑛 < 𝑉𝐷𝐷 + 𝑉𝑡ℎ𝑝
𝑉𝑑𝑠𝑝 > 𝑉
𝑔𝑠𝑝 − 𝑉𝑡ℎ𝑝
𝑉𝑜𝑢𝑡 > 𝑉𝑖𝑛 −𝑉𝑡ℎ𝑝
𝑉
𝑔𝑠𝑝 < 𝑉𝑡ℎ𝑝
𝑉𝑖𝑛 < 𝑉𝐷𝐷 + 𝑉𝑡ℎ𝑝
𝑉𝑑𝑠𝑝 < 𝑉
𝑔𝑠𝑝 − 𝑉𝑡ℎ𝑝
𝑉𝑜𝑢𝑡 < 𝑉𝑖𝑛 −𝑉𝑡ℎ𝑝
𝑉
𝑔𝑠𝑛 = 𝑉𝑖𝑛
𝑉𝑑𝑠𝑛 = 𝑉𝑜𝑢𝑡
𝑉
𝑔𝑠𝑝 = 𝑉𝑖𝑛 − 𝑉𝐷𝐷
𝑉𝑑𝑠𝑛 = 𝑉𝑜𝑢𝑡 − 𝑉𝐷𝐷

Operating Regions
25
Region NMOS PMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff

Delay Definitions
26
 Why delay may be different?
• Rise/fall time of input
• Multiple inputs or paths
• Slow when hot and fast when cold
 𝒕𝒑𝒅𝑷𝒓𝒐𝒑𝒂𝒈𝒂𝒕𝒊𝒐𝒏 𝑫𝒆𝒍𝒂𝒚
 maximum time from the input crossing 50% to the output
crossing 50%
 𝒕𝒄𝒅𝑪𝒐𝒏𝒕𝒂𝒎𝒊𝒏𝒂𝒕𝒊𝒐𝒏 𝑫𝒆𝒍𝒂𝒚 NTI - National Telecommunication
 minimum time from the input crossing 50% to the output
crossing 50%

Delay Definitions
27
 𝒕𝒓 𝑹𝒊𝒔𝒆 𝑻𝒊𝒎𝒆
 from the output crossing 0.2 𝑉𝐷𝐷 to 0.8 𝑉𝐷𝐷
 𝒕𝒇 𝑭𝒂𝒍𝒍 𝑻𝒊𝒎𝒆NTI - National Telecommunication
 from the output crossing 0.8 𝑉𝐷𝐷 to 0.2 𝑉𝐷𝐷
 Driver : The gate that charges or discharges a node
 Load : The gates and wire being driven

CMOS Power Basics
• Power is the energy dissipated in a device per unit of time.
• CMOS cell power model
 Switch power (dynamic):
I. Charging Output Load
 Internal power (dynamic):
I. Short Circuit
II. Charging internal Load
 Leakage power (static):
I. when the device is at steady state, no activity in the
device.
28
Internal power != Short Circuit Power

CMOS Power Basics –Static Power
• 𝑷𝒕𝒐𝒕𝒂𝒍 = 𝑷𝒔𝒕𝒂𝒕𝒊𝒄 + 𝑷𝒅𝒚𝒏𝒂𝒎𝒊𝒄
• 𝑷𝒔𝒕𝒂𝒕𝒊𝒄 = 𝑰𝒍𝒆𝒂𝒌𝑽𝑫𝑫
• 𝑷𝒅𝒚𝒏𝒂𝒎𝒊𝒄 = 𝑷𝑺𝒘𝒊𝒕𝒄𝒉𝒊𝒏𝒈 + 𝑷𝒊𝒏𝒕𝒆𝒓𝒏𝒂𝒍
• 𝑷𝑺𝒘𝒊𝒕𝒄𝒉𝒊𝒏𝒈 = 𝜶𝑪𝒍𝒐𝒂𝒅𝑽𝒅𝒅
𝟐
𝑻𝒓𝒂𝒕𝒆
• 𝑷𝒊𝒏𝒕𝒆𝒓𝒏𝒂𝒍= 𝑷𝑺𝒉𝒐𝒓𝒕 𝑪𝒊𝒓𝒄𝒖𝒊𝒕 + 𝑷𝒊𝒏𝒕𝒆𝒓𝒏𝒂𝒍 𝑺𝒘𝒊𝒕𝒄𝒉𝒊𝒏𝒈
• 𝑷𝑺𝒉𝒐𝒓𝒕 𝑪𝒊𝒓𝒄𝒖𝒊𝒕= 𝑰𝑺𝒉𝒕𝑽𝑫𝑫
• 𝑷𝒊𝒏𝒕𝒆𝒓𝒏𝒂𝒍 𝑺𝒘𝒊𝒕𝒄𝒉𝒊𝒏𝒈= 𝜶𝑪𝒊𝒏𝒕𝑽𝒅𝒅
𝟐
29

CMOS Power – Static Power
• Static or leakage power is the power consumed when the CMOS logic is not
switching.
• It is state, temperature, process and voltage dependent.
• The non-zero leakage current is due to
I. Subthreshold leakage: as channel is not 100% off due to reduced
transistor geometries and reduced Vth.
II.Gate-oxide tunneling: the charge can tunnel through the gate oxide
III.Revers-biased junction leakage current: There can be leakage
between the diffusion layers and the substrate. Though the p–n junctions
between the source/drain and the substrate are reverse-biased, a small
current can still flow.
30

CMOS Power Basics
• For all deep submicron technologies, any cell with an active
device is consuming static power even if it isn’t switching!
• For advanced technologies, leakage power can be a major
contributor to the total power, especially at worst-case
leakage corner.
31

Exercise 3
• Why ARM is popularly used for smartphones and embedded systems and Intel is not?
• For FPGAs, what is the major component of power, static or dynamic power?
• When a new smaller technology node is provided by a semiconductor foundry, what is expected for power and
performance w.r.t older technology with larger dimensions
32

CMOS Power Basics –Dynamic Power
• Dynamic power is the power consumed when the circuit is in operation, which means we have applied
supply voltage, applied clock and changed the inputs.
• It is mainly due to the dynamic currents, such as capacitance currents (switching power) and short-circuit
currents (short-circuit power) It is mainly due to the dynamic currents, such as capacitance currents (switching
power) and short-circuit currents (short-circuit power)
• Switching power is the power consumed by the charging and discharging of the load capacitance at the
output of a cell.
• Internal power : Power consumed within the standard cell when the cell is switching.
• 𝑷𝒅𝒚𝒏𝒂𝒎𝒊𝒄 = 𝑷𝑺𝒘𝒊𝒕𝒄𝒉𝒊𝒏𝒈 + 𝑷𝒊𝒏𝒕𝒆𝒓𝒏𝒂𝒍
• 𝑷𝑺𝒘𝒊𝒕𝒄𝒉𝒊𝒏𝒈 = 𝜶𝑪𝒍𝒐𝒂𝒅𝑽𝒅𝒅
𝟐
• 𝑷𝒊𝒏𝒕𝒆𝒓𝒏𝒂𝒍= 𝑷𝑺𝒉𝒐𝒓𝒕 𝑪𝒊𝒓𝒄𝒖𝒊𝒕 + 𝑷𝒊𝒏𝒕𝒆𝒓𝒏𝒂𝒍 𝑺𝒘𝒊𝒕𝒄𝒉𝒊𝒏𝒈
• 𝑷𝑺𝒉𝒐𝒓𝒕 𝑪𝒊𝒓𝒄𝒖𝒊𝒕= 𝑰𝑺𝒉𝒕𝑽𝑫𝑫
• 𝑷𝒊𝒏𝒕𝒆𝒓𝒏𝒂𝒍 𝑺𝒘𝒊𝒕𝒄𝒉𝒊𝒏𝒈= 𝜶𝑪𝒊𝒏𝒕𝑽𝒅𝒅
𝟐
33

Dynamic Power – Switching Power
• The power dissipated due to the charging and discharging of
the capacitive load at the output.
• The load capacitance at the output is a function of
interconnects’ capacitance, input pin capacitances of fanout,
and diffusion Capacitance of Drain.
34
𝑷𝑺𝒘𝒊𝒕𝒄𝒉𝒊𝒏𝒈 = 𝜶𝑪𝒍𝒐𝒂𝒅𝑽𝒅𝒅
𝟐

Dynamic Power – Internal Power
• This is the power consumed by the cell when an input
changes, but output does not change.
• Consist of Short Circuit Power and Internal Switching
Power.
• Short Circuit Power: Power dissipated when CMOS
logic gate is switching.
• The major cause is the power dissipated during the brief
interval of time when both the pull-up and the pull-down
structures are “ON”
• Internal Switching power : The power incurred during
the charging and discharging of Cint.
• Internal power is modeled in .libs as a function of input
transition and output capacitance. Its calculation is also
function of toggle rate.
35

Layout Vs Cross-Section
36

Inverter Mask Set
37
 Fabricated masks
1. N-well
2. Polysilico
3. n+ diffusion
4. p+ diffusion
5. Contact
6. Metal

Basics of Microfabrication
38
‘Semiconductor Manufacturing Process’

Photolithography
39

CMOS Fabrication
40

CMOS Fabrication
41

CMOS Fabrication
42

Introduction to Digital Backend Design (PnR)
• What is Digital Implementation and PnR Engineer role?
• How to implement digital designs from RTL to GDSII?
• How very large designs with millions of transistors can be implemented ?
43

How to Design a Billion Transistor Chip
• Design Complexity is increasing
• Need for fast time to market
• Reasonable Engineering effort
• Answer:
1. Abstraction
 Hiding details until they become necessary
2. Structured design
 Hierarchy: Blocks, sub-blocks
 Regularity/Modularity : Block reuse (ex: standard cells)
3. Automation using CAD tools
44

Design Abstraction
45
Level Modeling Object
Example of Modeling
Object
Hardware
Description
Language
Used
System
(Electronic System
Level – ESL)
Structural Circuit
C/C++
System
Verilog
System C
Register-Transfer
Level (RTL)
Functional
Circuits on the
level of multibit
devices – registers,
and data transfer
between them
Verilog
VHDL
Gate Level
(Gate level netlist,
Logic circuit)
Circuit containing
logic gates (AND,
OR, etc.) and flip
flops.

Design Abstraction
46
Level Modeling Object
Example of Modeling
Object
Hardware
Description
Language
Used
Circuit Level
(Transistor Level,
SPICE Netlist)
Electrical Circuit SPICE, CDL
Device Level IC Components

Digital Backend Design
• It’s the transformation of a digital circuit design (RTL in Verilog or VHDL) into a physical representation
(layout) for manufacturing (GDS/Oasis).
• Mainly relying on:
1. Standard cells libraries.
2. Automation in all analysis and verification steps with APR tools.
3. Accurate characterization of all sub-blocks used. [libraries and macros]
47

CAD/EDA tools
• Digital design
1. Design entry (e.g., HDL) and simulation
2. Automated synthesis (from HDL to gates)
3. Automated place and route (from gates to transistor layout)
4. Verification (LVS/DRC/Timing analysis/EMIR analysis)
48

Design Verification
Static Timing Analysis:
 Checks timing against constraints
1. setup/hold/recovery/removal
2. max transition / max capacitance..
Physical transistor-level verification
 Layout vs. schematic (LVS)
 Design rule check (DRC)
EMIR/power Verifications:
 Electromigration and IR drop analysis
Formal (static) verification:
 Checks logic equivalence between different abstraction levels
49

Digital Implementation / PnR Engineer Role
Digital Implementation is the last step in the VLSI design flow
 Basically, transform RTL to GDSII and verify your design
 Any mistake in the flow ripples to the DI team!
 Interface with other design teams ex: Digital design-verification /analog layout / other DI teams / Fab
house / Cad team / Packaging team / lab team / ..”
Automation has limitations!
 EDA (Electronic Design Automation) tools are limited, and the design problem is very hard!
 Tradeoffs to consider: (mainly PPA: Power Performance Area):
 Ex: Reduce congestion by placing cells apart VS Improve timing by placing cells closer.
 More performance always require more power and area.
50

Digital ASIC Design Flow Responsibilities:
Frontend VS Backend
51
Digital Frontend team
• Choosing microarchitecture, suitable algorithms to use,
number of pipeline stages…etc according to the system
specifications.
• Developing synthesizable RTL and constraints.
• Developing suitable DC scripts for synthesis and DFT.
• Specifying power domains and generating UPF maps.
• Performing verification for the RTL.
• Performing gatelevel simulations to check backend
deliverables.
Digital Backend team
• Meeting timing requirements of setup and hold according
to SC library specifications.
• Meeting special timing requirements asked by the digital
team (ex. Skew balancing).
• Matching digital team intended design: gatelevel netlist
matching RTL,
• Meeting physical design rules specified by the foundry
(DRC, LVS, Antenna, DFM)
• Minimizing IR drop over the design so that it is below a
defined threshold (~2%)
• Minimizing power consumption so that it’s comparable to
a similar node or similar design.

Overall Design Flow
52

Standard Cell Library
• A good application of design abstraction.
• A standard cell is a group of transistor and
interconnect structures that provides a Boolean logic
function (e.g., AND, OR inverters) or a storage
function (flipflop or latch).
• Standard cell library is a collection of well defined
and pre-characterized logic cells with multi-
drive strength and multi-threshold voltage
cells in the form of a predefined standard cell layout.
It also contains several physical only cells and a set of
library files required by Place and Route (PnR) tool
for automatic placement and routing (APR).
53

Standard Cell Library
Cell categories:
1.All basic and universal gates (AND, OR, NOT,
NAND, NOR, XOR etc.)
2.Complex gates (MUX, HA, FA, Comparators, AOI,
OAI etc.)
3.Clock tree cells (Clock buffers, clock inverters, ICG
cells etc.)
4.Flip flops and latches
5.Delay cells
6.Physical only cells
7.Scannable Flip flops, Latches
 Cell Files
1.LIB files (.lib)
2.LEF files (.lef)
3.Netlist file (.v )
4.GDS file (.gds)
5.SPICE Netlist (.sp)
6.Model file (.m)
54

Standard Cell Library: Typical views
Behavioral views
• Gatelevel netlist(.v): used for simulation a
logic equivalence.
• Timing/Power views (.lib): contains
characterization of library used for STA and
EMIR
analysis. Also input to logic synthesis and PnR
tools for optimization.
Physical views
• .lef: abstract format for modeling of cells in PnR
tools.
• .gds: graphical representation of the layout
going to be fabricated, used for DRC and LVS.
• .sp: spice netlist contains transistor level
representation of cells, used for LVS.
55

Standard Cell Layout
• All the Standard cells are in equal in height and
varying width.
• At the top of the standard cell, there is VDD rail and
bottom there is a VSS rail.
• Both the Power rails are drawn in the Metal-1 layer
• Nwell region, near to the VDD rail where PMOS
transistors are built.
• A gap of Nwell and Pwell dedicated usually for
wiring.
• Pwell region near the VSS rail where nMOS
transistors are built
• There may be double height cells , triple height cell,
etc. Similarly, the rows also have heights accordingly.
The standard cells will fit in the row with proper
orientation.
56

Cell variants: Drive strengths
• Each logic cell (NAND, NOR, INV…) is implemented
in the SC library in:
1.Multiple sizes (x1, x2, x4, x8..etc).
2.Multiple flavors (LVT, SVT, HVT).
• Each cell will have various drive strengths for
effective speed VS area optimization.
• Larger output stage leads to better driving of
fanouts, better delay/performance at the cost of
increased area and leakage power.
• Smaller drive strength less area, leakage and
input cap.
 The higher the width; the more current going
through the channel.
 Each dive strength will have different footprints, so
if we need to swap the 1x by 2x or vise versa then we
need to return to the placement stage.
57

Cell variants: MT-CMOS
• One additional mask can provide more or less doping in
a transistor channel, shifting the threshold voltage.
• Most libraries provide equivalent cells with three VTs:
SVT,HVT, LVT to tradeoff speed vs. leakage.
• All threshold varieties have same footprint and therefore
can be
swapped without any placement/routing
iterations.[Footprint: pins and obstructions]
• The HVT/LVT cells are (usually) provided within the
same footprint as their SVT counterparts, and so you
can swap them without causing any DRC violations. In
other words, they have the same LEF abstract as the SVT
cells.
• Larger/Smaller cells have a different footprint/different
LEF. So they may be larger and therefore overlap with
an adjacent cell and many have their pins and blockages
in different locations and therefore cause shorts/opens
or other DRCs. - Therefore, when swapping for a
larger/smaller cell you must:
58
footprint is a summary of (cell width/heigth) plus (cell pin
location and geometry) plus (cell metal polygons geometry).
If two cells have the same width/heigth, the same pin
geometry and all other metal polygons are the same, it means
these two cells have equivalent footprint.
It is needed, when you do want to replace one cell for
another (timing optimization or other reason), but do not want
to touch existing placement and/or existing routing.
It is obsolete (still supported) feature. Usually, the tools
derive such info from LEF or Milkyway (not from .lib).

Standard Cell List Example
59
No Cell name Cell Description
Type&Drive
Strength
Inverters. Buffers
1. SAED14_INV_* Inverter
0.5, 0.75, 1, 10,
12, 16, 1.5, 2, 20,
3, 4, 6, 8
2. SAED14_INV_ECO_* Inverter 1, 2, 3, 4, 6, 8
3. SAED14_DEL_R2V3_* Delay buffer 1, 2
4. SAED14_DEL_L4D100_* Delay buffer 1, 2
5. SAED14_CLKSPLT_* Clock Splitter 1, 8

Standard Cell List Example 2
60
No Cell name Cell Description
Type&Drive
Strength
Logic Gates
7. SAED14_AN2B_MM_*
2-Input AND (A
inverted input),
symmetric
rise/fall
1, 12, 16, 2, 20, 4, 6, 8
8. SAED14_AN2_* 2-Input AND 0.5, 0.75, 1, 2, 4, 8
9. SAED14_AN2_ECO_* 2-Input AND 2
10. SAED14_AN2_MM_*
2-Input AND,
symmetric rise/fall
0.5, 1, 12, 16, 2, 20, 3,
4, 6, 8
11. SAED14_AN3_* 3-Input AND 0.5, 0.75, 1, 2, 4, 8
13. SAED14_AN4_* 4-Input AND 0.5, 0.75, 1, 2, 4, 8

Standard Cell List Example 3
61
No Cell name
Cell
Description
Type&Drive Strength
Complex Logic Gates
15. SAED14_NR2B_*
2-Input NOR (A inverted
input)
0.75, 1, 1.5, 2, 4
16. SAED14_NR2B_U_*
input)
0.5
17. SAED14_NR2_* 2-Input NOR
0.5, 1, 16, 1.5, 2, 3, 4, 5, 6,
8
18. SAED14_NR2_ECO_* 2-Input NOR 1, 2
19. SAED14_NR2_MM_*
Symmetric rise/fall time 2-
input NOR
0.5, 1, 10, 12, 16, 2, 3, 4, 6,
8
20. SAED14_NR3B_*
input)
0.75, 1, 1.5, 2, 4
21. SAED14_NR3B_U_*
input)
0.5
22. SAED14_NR3_* 3-Input NOR 0.5, 0.75, 1, 2, 3, 4, 8
23. SAED14_NR2B_*
2-Input NOR (A
inverted input)
0.75, 1, 1.5, 2, 4

Standard Cell : Exercise 1
 What is the preferred cells to be used for the following applications: [size and flavor]
• Heart peacemaker.
• Datacenter processor.
• Battery powered IoT device.
 Compare the following cells in terms of: speed, area, and leakage power.
• svt_x2_buf, svt_x8_buf, svt_x16_buf
• svt_x2_buf, lvt_x2_buf [lvt: low V-threshold cell]
 Compare between using a complex “AOI” cell, and implementing same logic using equivalent
NAND2 cells, w.r.t overall delay and performance.
62

Standard cell library Characterization- LIB
• It’s a readable ASCII format that characterizes the standard cell library cells in terms of timing,
area, power and other parameters.
• The cell is characterized using spice simulation, timing and power results are obtained under a
variety of conditions, and the data is represented in the .lib format.
• Lib file is basically a timing model file which contains cell delay, cell transition time, setup and
hold time requirement of the cell. So, Lib file basically contains the timing and electrical
characteristics of a cell or macros.
63
0.7
0.5
0.2
0.1
.023 .047 .065 .078 .091
output cap
slew
0.7
0.5
0.2
0.1
.023 .047 .065 .078 .091
output cap
slew
Iout
Cchar
Input Slew
0.7
0.5
0.2
0.1
.023 .047 .065 .078 .091
output cap
slew
Process: Typical
Temp: 25o
Voltage: 1.2v
Process: Slow
Temp: -40o
Voltage: 1.08v
Process: Fast
Temp: 125o
Voltage: 1.32v

LIB/db
• The information inside the Lib file can be divided
into two main parts, in the first part, it contains some
information which is common for all the standard
cells.
• The common part of Lib file contains
I. Library name and technology name
II. Units (of time, power, voltage, current, resistance
and capacitance)
III. Value of operating condition ( process, voltage
and temperature) – Max, Min and Typical.
Based on operating conditions there are three
different lib files for Max, Min and Typical corners.
64

LIB/db
• In the second part of Lib file, it contains cell-specific
information for each cell.
• Cell-specific information in Lib file is mainly
I. Cell name
II. PG Pin name
III.Area of cell
IV.Leakage power in respect of input pins logic state
V. Pins details
1. Pin name
2. Pin direction
3. Internal power
4. Capacitance
5. Raise capacitance
6. Fall Capacitance
7. Fanout load
65

Liberty file (.lib or .db file)
66

Liberty file (.lib or .db file)
• Why to use .lib?
To know if the design meets timing or not:
o Running SPICE will consume a lot of time and
computing resources.
o Instead, we use a timing model that abstracts cell
behavior and simplify calculations.
For every timing arc, the .lib enables us to calculate:
A. Propagation delay
B. Output transition
Based on:
A. Input transition
B. Output load capacitance
For each signoff corner, we use the provided .lib file for
this corner to perform timing analysis (STA) and Power
analysis as well.
67

Parasitic Estimation: WLM
• Parasitics are inevitable.
• Parasitics are not known without layout.
• Delay and Area will be incorrect/optimistic without
estimation of Parasitics.
• To calculate output load capacitance of a cell; we need to
calculate both:
1. Input capacitance of the load(s).
2. Wire delay of the interconnect.
During logic synthesis; we don’t have actual placed cells
• We use WLM to estimate interconnect Parasitics, based on
the fanout of the net.
68
R = length ∙ Runit length
C = length ∙ Cunit length

Path Delay Calculation
69

Exercise
• For critical timing paths, which cells should be used by logic synthesis tools?
(size/flavor/complex or simple cells) Critical Timing Path:
• For calculating the propagation delay of a specific cell, how can DC/ICC calculate its input
transition and load capacitance?
• If the input transition is outside cell’s delay characterization LUT; how will STA engine
calculate propagation delay?
70

DC Parameters and Measurement
Conditions of Digital Cells
71
N Parameter Unit Symbol Figure Definition
1. Voltage
Transfer
Characteristic -
VTC DC functional
dependence
between input
and output
voltages.
2. Output high level
voltage (nominal)
V VOHN=VDD Output high
voltage at
nominal
condition,
usually equals to
VDD
3. Output low level
voltage (nominal)
V VOLN=0
(VOLN=VSS)
Output low
voltage at
nominal
condition,
usually VOLN=0
4. Switching point
voltage
V VSP Point on VTC
where
VOUT =VIN
VOUT
VIN
VDD
0
VDD
VOUT
VIN
VDD
0 VDD
VOHN =VDD
VOUT
VIN
VDD
0 VDD
VOLN= 0
VOUT
VIN
VDD
0 VDD
swp
VSP
V SP
slope= 1

72
5. Output high level
minimum voltage
V VOHMIN Highest output
voltage at
slope= -1.
6. Output low level
maximum voltage
V VOLMAX Lowest output
voltage at
slope= -1
7. Input minimum high
voltage
V VIHMIN Highest input
voltage at slope
= -1
8.
Input maximum low
voltage
V VILMAX Lowest input
voltage at
slope = -1
VOUT
VIN
VDD
0 VDD
VOHMIN
slope=-1
VOUT
VDD
0 VDD
VOLMAX
slope=-1
VIN
VOUT
VDD
0 VDD
VOMAX
slope=- 1
V
IHMIN
VIN
VOUT
VDD
0 VDD
slope=-1
VOHMIN
VILMAX

73
9.
High state noise
Margin
V NMH= VOHMIN-VIHMIN
The maximum input noise
voltage which does not change
the output state when its value
is subtracted from the input
high level voltage
10.
Low state noise margin
V NML=VILMAX-VOLMAX
The maximum input noise
voltage which does not change
the output state when added to
the input low level voltage
11. Static leakage current
consumption at output
on high state
uA
ILEAKH None
The current consumed when
the output is high
12. Leakage power
consumption
(dissipation) at output
pW PLEAKL=VDD x ILEAK None The power consumed when
the output is high
13. Leakage power
consumption
on high state
pW PLEAKL=VDD x ILEAKH None The power consumed when
the output is high
14. Leakage power
consumption
on high state
pW PLEAKL=VDD x
ILEAKL
None The power consumed when
the output is low
Voltage
NMH
Undefined
VIHMIN
VOHMIN
VILMAX
VDD
0
Voltage
NML
Undefined
VIHMIN
VILMAX
VOLMAX

AC Parameters and Measurement
74
1. Rise transition time ns tR
The time it takes a driving
pin to make a transition
from kVDD to (1-k)VDD value.
Usually k=0.1 (also possible
k=0.2, 0.3, etc)
2. Fall transition time ns tF The time it takes a driving
pin to make a transition
from (1-k)VDD to kVDD value.
Usually k=0.1 (also possible
k=0.2, 0.3, etc)
3. Propagation delay
low-to-high
(Rise propagation)
ns tPLH
(tPR)
Time difference between the
input signal crossing a
0.5VDD and the output signal
crossing its 0.5VDD when the
output signal is changing
from low to high
VSS
0.1VDD
0.9VDD
tR
VDD
VSS
0.1VDD
0.9VDD
tF
VDD
tPLH
0.5VDD
0.5VDD
IN
OUT

75
4. Propagation delay
high-to-low
(Fall
propagation)
ns tPHL
(tPF)
Time difference between the input signal
crossing a 0.5VDD and the output signal
crossing its 0.5VDD when the output signal is
changing from high to low
5. Average supply
current
uA The power supply current average value for a
period (T)
6. Supply peak
current
uA IVDDPEAK=
=max(IVDD(t))
t[0;T]
The peak value of power supply current
within one period (T)
7. Dynamic power
dissipation
pW PDISDYN=
=IVDDAVG x VDD
The average power consumed from the
power supply
8. Power-delay
product
nJ PD=PDISDYN x
x max
(tPHL,tPLH)
The product of consumed power and the
largest propagation delay
tPHL
0.5VDD
0.5VDD
IN
OUT


T
0
dt
)
t
(
V
I
AVG
V
I
DD
DD

76
N Parameter Un
it
Symbol Figure Definition
9. Energy-delay
product
nJs ED=PD x
x max(tPHL,tPLH)
The product of PD and the largest
propagation delay
10. Switching fall power nJ PSWF =
=(CLOAD+COUTF) x
x VDD
2/2
The energy dissipated on a fall transition.
(COUTF is the output fall capacitance)
11. Minimum clock
pulse (only for flip-
flops or latches)
ns tPWH (tPWL) The time interval during which the clock
signal is high or low, so that it ensures
proper operation of a flip-flop or a latch
12. Setup time
(only for flip-flops or
latches)
ns tPWH (tPWL) The time interval during which the clock
signal is high or low, so that it ensures
proper operation of a flip-flop or a latch
13. Setup time
(only for flip-flops or
latches)
ns tSU The minimum period in which the input
data to a flip-flop or a latch must be stable
before the active edge of the clock occurs
OUT
CLOCK
DATA
tPWH
0.5VDD
0.5VDD
DATA
CLOCK
tSU

77
14. Hold time
(only for flip-
flops or latches)
ns tH The minimum period in which the
input data to a flip-flop or a latch
must remain stable after the active
edge of the clock has occurred
15. Clock-to-output
time
(only for flip-
flops or latches)
ns tCLKQ The amount of time that takes the
output signal to change after clock’s
active edge is applied
16. Removal time
(only for flip-
flops or latches
with
asynchronous
Set or Reset).
ns tREM The minimum time in which the
asynchronous Set or Reset pin to a
flip-flop or latch must remain
enabled after the active edge of the
clock has occurred
0.5VDD
0.5VDD
DATA
CLOCK tH
0.5VDD
DATA
CLOCK
tCLKQ
0.5VDD
OUT
SET (RESET)
CLOCK
tREM
0.5VDD
0.5VDD

78
N Parameter Un
it
Symb
ol
Figure Definition
17. Recovery time
(only for flip-flops and
latches with
asynchronous Set or
Reset)
ns tREC The minimum time in which Set or Reset
must be held stable after being deasserted
before next active edge of the clock occurs
18. From high to Z-state
entry time, (only for
tri-state output cells)
ns tHZ The amount of time that takes the output
to change from high to Z-state after
control signal is applied
19. From low to Z-state
entry time, (only for
tri-state output cells)
ns tLZ The amount of time that takes the output
to change from low to Z-state after control
signal is applied
20. From Z to high-state
exit time
(only for tri-state
output cells)
ns tZH The amount of time that takes the output
to change from Z to high-state after
control signal is applied
21. From Z to low-state
exit time
(only for tri-state
output cells)
ns tZL The amount of time that takes the output
to change from Z to low-state after control
signal is applied
22. Input pin capacitance pF CIN Defines the load of an output pin
23. Maximum
capacitance
pF CMAX Defines the maximum total capacitive load
that an output pin can drive
0.5VDD
SET (RESET)
CLOCK
tREC
0.5VDD

LEF: Library exchange format (.lef file)
• LEF is a short form of Library Exchange Format. LEF file is written in ASCII format, so this file is a human-
readable file.
• The LEF file abstracts the following information to PnR tools:
1. Cell size and shape.
2. Pin locations and layer.
3. Metal blockages (OBS section), that represent internal metal shapes of the cell not to be touched by
routing.
• A LEF file describing the Library has mainly two parts.
1. Technology LEF
2. Cell LEF
79

Technology LEF
• Technology LEF part contains the information regarding
all the metal interconnects, via information and related
design rules whereas cell LEF part contains information
related to the geometry of each cell.
• Technology LEF part contains the following
information:
1. LEF Version ( like 5.7 or 5.8 )
2. Units (for database, time, resistance, capacitance)
3. Manufacturing grids
4. Design rules and other details of BEOL (Back End Of
Layers)
a. Layer name (like poly, contact, via1, metal1 etc.)
b. Layer type ( like routing, master slice, cut etc.)
c. Preferred direction (like horizontal or vertical)
d. Pitch
e. Minimum width
f. Spacing
g. Sheet resistance
80

Cell LEF:
• Cell LEF part contains the information related to each
cell present in the standard cell library in separate
sections.
• Cell LEF basically contains the following information
1. Cell name (like AND2X2, CLKBUF1 etc.)
2. Class ( like CORE or PAD)
3. Origin 0 0
4. Size (width x height)
5. Symmetry ( like XY, X, Y etc.)
6. Pin Information
i. Pin name (like A, B, Y etc.)
ii. Direction (like input, output, inout etc. )
iii.Use (like Signal, clock, power etc.)
iv. Shape (Abutment in case of power pin)
v. Layer (like Metal1, Metal2 etc. )
vi. The rectangular coordinate of pin (llx lly urx ury)
81
reference point
(typically 0,0)
Dimension
“bounding
box”
Pins
(direction,
layer and
shape)
VDD
GND
A B
Y
NAND_1
Blockage
Symmetry
(X, Y, or 90º)
F
Abstract View
FF
BUF
INV
NOR
unit tile (site)

LEF
82

Spice and GDS
• SPICE netlist is the netlist of cell in SPICE
format is used for simulation.
• Typically used in digital implementation
for LVS checking
• GDSII file is a binary file format representing
planar geometric shapes, text labels, and other
information about the layout in hierarchical form.
• A better alternative widely used now:
Oasis format.
83

Overall Design Flow
• The operating conditions of a design include the following parameters:
−Process
− Voltage
− Temperature
• The chip is intended to operate under this parameters.
• Process variation
This variation accounts for deviations in the semiconductor fabrication process. Usually process variation is treated as a
percentage variation in the performance calculation.
• Supply voltage variation
The design’s supply voltage can vary from the established ideal value during day-to-day operation. Often a complex
calculation (using a shift in threshold voltages) is employed, but a simple linear scaling factor is also used for logic- level
performance calculations.
• Operating temperature variation
Temperature variation is unavoidable in the everyday operation of a design. Effects on performance caused by temperature
fluctuations are most often handled as linear scaling effects, but some submicron silicon processes require nonlinear
calculations.
84

The Multiple Analysis Corners
85
Corner
Name
Process
(NMOS proc. –
PMOS proc.)
Temperature (T) Power Supply (V) Notes
TTNT1p20v Typical - Typical 25 1.2 Typical corner
SSHT1p08v Slow - Slow 125 1.08 Slow corner
FFLT1p32v Fast - Fast -40 1.32 Fast corner
FFHT1p32v Fast - Fast 125 1.32
High leakage
corner
SSLT1p08v Slow - Slow -40 1.08 Low temperature
• A corner is defined as a PVT, and it is provided to the analysis and
optimization tool as logic libraries per PVT and Parasitics data.
• Corners are not due to functional settings, but rather result from process
variations during manufacturing, and voltage and temperature variations in
the environment in which the chip will operate.
• Each standard cell library is characterized for a set of signoff corners,
according to the required signoff corner for the design(s) that will use the
library later.
V
P
T
MC => Opt(P,V,T)
Best, Worst
Cap (Best, Worst)

The Multiple Analysis Corners- Process:
• Process variation is the deviation in attributes of transistor during the fabrication.
• During manufacturing a die, the area at the centre and that at the boundary will have different process variation. This
happens because layers which will be getting fabricated can not be uniform all over the die. As we go away from the
center of the die, layers can differ in their sizes.
• Process variation is gradual . It can not be abrupt.
• Process variation is different for different technologies but is more dominant in lower node technologies (<65nm).
• Below are few important factors which can cause process variation;
1.Wavelength of the UV light
2.Manufacturing defects
• The affects of process variation are listed below;
1.Oxide thickness variation
2.Dopant and mobility fluctuation
3.Transistor width, length etc.
4.RC Variation
86

The Multiple Analysis Corners- Voltage:
• Now a days, supply voltage for a chip is very less. Lets say chip is operating
at 1V. So there are chances that at certain instance of time this voltage may
vary. It can go to 1.1V or 0.9V. To take care of this scenerio, we consider
voltage variation.
• There are multiple reasons for voltage variation. These are discussed below.
• The important reason for supply voltage fluctuations is IR drop. IR drop is
caused by the current flow over the parasitic resistance of the power grid. IR
drop reduces the supply voltage from the required value.
• The second important reason for voltage variation is supply noise caused by
parasitic inductance in combination with resistance and capacitance. The
current through parasitic inductance causes the voltage bounce. Both these
effects together can not only lead to voltage drops but also voltage
overshoot.
• Supply voltage that any chip works on is given externally. It can come from
DC source or some voltage regulator. Voltage regulator will not give same
voltage over a period of time. It can go above or below the expected voltage
and hence it will cause current to change making the circuit slower or faster
than earlier.
87

Multiple Analysis Corners - Temperature
• The temperature variation is with respect to junction and not ambient
temperature. The temperature at the junction inside the chip can vary
within a big range and that’s why temperature variation need to be
considered. Figure 3 shows the variation of delay with respect to
temperature. Delay of a cell increases with increase in temperature. But
this is not true for all technology nodes. For deep sub-micron
technologies this behavior is contrary. This phenomenon is called as
temperature inversion.
• Temperature inversion: The delay depends on the output
capacitance and ID current (directly proportional to Cout and inversely
proportional to ID). When the temperature increases, delay also
increases (due to the variation in carrier concentration and mobility).
But when temperature decreases, delay variation shows different
characteristics for submicron technologies. For technology nodes below
65nm, the delay will increase with decrease in temperature, and it will
be maximum at -40°C. This phenomena is known as “temperature
inversion”.
88

RC Variation:
• RC variation is also considered as corners for the setup and hold checks.
RC variation can happen because of fabrication process and the width of
metal layer can vary from the desired one.
• We always check our chip to work in worst scenarios. We should be very
pessimistic about setup and hold checks. So, consider worst case scenarios.
• Setup violation can be caused if data is coming very slow. So, the condition
when process is slow, voltage is minimum, and temperature is maximum is
the worst case for setup check. Also because of temperature inversion at
lower technology node, delay will increase as temperature decrease. Hence
lowest temperature results in more delay. It is not compulsory that the
delay at lowest temperature is always less than delay at highest
temperature.
• Hold violation is caused if data comes faster. So, process should be faster,
voltage should be maximum, and temperature should be minimum.
• Now if setup and hold are checked in worst corners, then the chip should
work in every scenario. Still, we check them in typical corners because we
need to analyze power consumption. Refer following table for the worst-
case scenarios for setup and hold.
89

Example
• For Automotive chips; which corners do you expect to have more than usual to ensure chip will reliably operate
in car’s harsh environment?
• What do you expect in the following scenarios for your design’s area and power:
1. If you have extremely slow corners in your required signoff corners.
2. If you have extremely fast corners in your required signoff corners
• If you are a product marketing manager for an MCU chip vendor specialized in automotive MCUs (ex.
Renesas), how would you choose your signoff corners?
• If you are a project manager for an IP vendor (ex. ARM), and a customer is asking for signoff corners 1.5x
slower what is usual, what is the impact on the IP? [area, power, timing, development time, how much you
charge the customer]
90

Further Reading
• CMOS VLSI Design: A Circuits and Systems Perspective 4th Edition by Neil Weste , David Harris.
• Synopsys slides
• Cadence slides
• CMPE 641: Topics in VLSI
• Logic Synthesis - Part I (Standard Cell Libraries) by Adam Teman.
• Team VLSI
• …a number of years of experience!
91

Thank You 
92

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