6. Design Planning.pdf

Digital
Implementation
Design Planning
1
© Ahmed Abdelazeem. All rights reserved
IP

Contents
After completing this unit, you should be able to:
❑ Implement a given floorplan, this includes:
◦ Defining the core area
◦ Creating and placing power pads
◦ Placing the IO pads and macros
◦ Modifying the orientation of macros
◦ Implement a P/G grid according to given parameters
◦ Defining placement and routing blockages
❑ Create a rectilinear block abstract
❑ Power Planning
◦ Design the Power Network
◦ Apply the PG Strategies
◦ PG Verification and Analysis
2/28/2024 2
IP

Facilities
Building Hours
Restrooms
Meals
Messages
Smoking
Recycling
Phones
Emergency EXIT
Please turn off cell phones and pagers
3
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Workshop Goal
Use IC Compiler II to perform placement, DFT,
CTS, routing and optimization, achieving timing
closure for designs with moderate to high design
challenges.
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2/28/2024

Target Audience
ASIC, back-end or layout designers with
experience in standard cell-based automatic
Place&Route.
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2/28/2024

High-Level IC Compiler Flow
Gate-level netlist
Synthesis
Design & Time Setup
Floorplan Definition
Placement & Optimization
CTS & Optimization
Routing & Optimization
Signoff
IC
Compiler
II
6
2/28/2024 © Ahmed Abdelazeem. All rights reserved

✓

What Is Floorplanning?
2/28/2024 7
IP
ROM
RAM
The location of the core,
periphery areas, and the
P/G grid, define the
Floorplan of the chip.
Core
placement
area
Periphery
area
Rings
Straps
P/G
Grid
With a top-level netlist, you can
start to floorplan the chip.
▪ Define Die Size.
▪ Place the IOs.
▪ Perform macro placement.
▪ Perform power planning.
▪ Power domain definition
▪ Flip-chip bump placement
Floorplanning is the process of
deriving the die size, allocating space
for soft blocks, planning power, and
macro placement.

Floorplanning
❑ Floorplanning consists of defining the Core Placement area, the Periphery area and the
Power/Ground grid.
❑ The Core Placement area consists of Placement Rows where standard cells and macro cells
are placed.
❑ A placement row consists of a row of “unit tile” cells (part of the standard cell library, width
defined by the minimum metal pitch). Standard cells are placed in the core of a chip and
occupy specific tile(s) within the placement rows. A standard cell may occupy a single or
multiple tiles.
❑ The pad cells (input, output, bi-dir, power and ground pads) are placed in the Periphery Area,
which is defined by the area around the outside boundary of the core, usually separated by a
“core-to-pad” spacing distance.
2/28/2024 © Ahmed Abdelazeem. All rights reserved 8

Floorplanning: Creation of Site Rows
◼ Placement requires grid in which cells will be placed
◼ Floorplanning uses ‘unit tile’ cell to build this grid
❑ It is defined by a library developer and library cells are designed to be
multiple of unit tile
Creation of sites for
detailed placement
FF
BUF
INV
NOR
unit tile
(site)

What Are Sites and Rows?
❑ A site is the minimum unit of placement. It represents a slot where a cell can be placed.
Rows are multiples of sites and define locations where the placement tool places cells.
❑ Placement tools place cells in locations defined by the cell’s description in the LEF file. If a
cell is of type CORE, then it can only be placed in a CORE rows. If a cell is of type IO, it can
only be placed in IO rows.

Floorplan Areas
Pad Area
Core Area
❑ In general, a chip is a combination of:
◦ Core Area
◦ Pad Area

Pad Area
❑ Pad area consists of:
◦ Input/Output/InOut pads
◦ Power pads and corner pads
◦ Pad fillers
◦ P/G rings
CornerUR
Reset
Filler
VDD
VSS
VSS
VDD

Initialize Floorplan and Create Core Area
Row 1
Row 3
Row 2
Bottom of row key
Core To
Bottom
Distance
Core To
Left
Distance
Width
Height
Control Parameters
* Aspect Ratio
→Utilization
→Aspect ratio (H/W)
→Row/core ratio
* Width & Height
→Width
→Height
→Row/core ratio
* ……….
* ……….
Example of a horizontal, no double back, no-flip first row with Row/Core <1.

Utilization: A Factor in Determining Core Size
Macro
◼ Core “utilization” is the
percentage of the core that is used
by placed std cells and macros
◼ Ideally would like to achieve 100%
utilization at tape-out. In practice
range is 80-85%
◼ Recommended starting netlist
utilization should not exceed 60-
75% to allow for logic
optimizations and DFM
𝑼𝒕𝒊𝒍𝒊𝒛𝒂𝒕𝒊𝒐𝒏 =
(𝑻𝒐𝒕𝒂𝒍 𝑺𝒕𝒅 𝑪𝒆𝒍𝒍 + 𝑴𝒂𝒄𝒓𝒐 𝑪𝒆𝒍𝒍 𝑨𝒓𝒆𝒂)
𝑪𝒐𝒓𝒆 𝑨𝒓𝒆𝒂
∗ 𝟏𝟎𝟎%

Core and IO Region
❑ From:
• A gate-level netlist of Relevant physical libraries
• Default or user-specified aspect ratio and utilization.
❑ Calculate the area of all macro cells and leaf cells Generate bounding shapes and cell placement
rows Place IO PADs
• Signal pads
• Filler and corner pads Bump or flip-chip IO pads
𝑼𝒕𝒊𝒍𝒊𝒛𝒂𝒕𝒊𝒐𝒏 =
(𝑻𝒐𝒕𝒂𝒍 𝑺𝒕𝒅 𝑪𝒆𝒍𝒍 + 𝑴𝒂𝒄𝒓𝒐 𝑪𝒆𝒍𝒍 𝑨𝒓𝒆𝒂)
𝑪𝒐𝒓𝒆 𝑨𝒓𝒆𝒂
∗ 𝟏𝟎𝟎%

Aspect Ratio: A Factor in Determining Core Size
❑ Aspect ratio is the ratio between vertical routing resources to horizontal routing resources.
❑ If you specify a ratio of 1.00, the height and width are the same and therefore the core is a
square.
❑ If you specify a ratio of 2.00, the height is two times the width.

Floorplanning: Space for Power Rings
◼ A fixed space is required to be available around core for
power supply rings
Core

Floorplanning: Pin Locations
◼ Pins can be spread automatically by IC Compiler II around the boundary
◼ The exact side and/or location, layers, size for pins can be set by a designer
Pins
Core
set_pin_physical_constraints -pin_name "mypin"
-layers {M2 M3 M4 M5}
-width 0.28 -depth 0.28 -side 1 -offset 5

Floorplanning: I/O Placement
Core
Periphery
(I/O) area

Initialize the Floorplan
❑ Floorplan Initialization
◦ Sets the boundary and defines
standard cell placement site array
within the core area.
◦ Support Various core shapes:
◦ Rectangle
◦ L-, U-, T- Shapes
◦ Rectilinear
◦ Initialization does not place chip-
level IO-pads nor block-level pins
initialize_floorplan -core_utilization 0.7 -shape L -orientation N
-side_ratio {1 1 1 1} -core_offset {100.0} -flip_first_row true
-coincident_boundary true

Cell View after Initialize Floorplan
Flip first
row, double
back,
row/core = 1
Unplaced
Macro
cells
Unplaced
Standard
cells
Core area
with rows
and tracks
inserted
Periphery
w/ IO pad
cells

Pad-Limited Design
Core Placement
Area
Core Placement area uses
less real estate than
available.
If the utilization of a pad-limited design is too high
during floorplanning will reducing it affect die size?
The large number of pad
cells determines die-size.

Core-Limited Designs
Core Placement
Area
Pads use less than
available periphery area.
The large number of
standard cells and macros
determine die-size.
If the utilization of a core-limited design is too high
during floorplanning will reducing it affect die size?

Cell Types
VS VS
Standard
cells
IP I/O Pad
Ring IP
Flip Chip Bump
I/O Ring
Core

I/O Cell Placement
Wire Bond Flip-Chip
IC
Dielectric
Underfill
http://ffden-2.phys.uaf.edu/212_spring2005.web.dir/george_walker/uses.htm http://blog.daum.net/dourira/6824688

Wire Bond
❑ Most widespread method
❑ IC is connected with
package pins with thin wires
Wire Bonding Example
http://www.era.co.uk/case-studies/improving-the-reliability-of-chip-on-board-assembly/

Flip-Chip
IC
Dielectric
Underfill
Rigid Laminate
Solder Ball
Flip Chip Cross Section
▪ Modern method of I/O
connection
▪ IC is connected with
package using solder
balls
http://www.izm.fraunhofer.de/en/abteilungen/high_density_interconnec
twaferlevelpackaging/arbeitsgebiete/arbeitsgebiet1.html

Wire Bond Placement
core area
Wire Bond
wide
wire
route
I/O driver
bond
pad

Flip-Chip Placement
core area
Flip Chip Driver Cells Placed
around Perimeter of Chip
core area
Bump Cells
Overlaying the Chip
IO
Driver
bump
wide wire pins

I/O Cell Physical Structures
BUMP
d
d
VDD
VSSIO
VSS
VDDIO
VSSIO
VDDIO
VDDIO
b
b
b
b
b
b
b
VSSIO
VDDIO
VSSIO
VDDIO
b
b
b
b
VSSIO
VDDIO
VDDIO
b1
b
b
a
VSSIO
b1
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
VDD
VSSIO
VSS
VDDIO
VSSIO
VDDIO
VDDIO
b
b
b
b
b
b
b
?
VSSIO
VDDIO
VSSIO
VDDIO
b
b
b
b
VSSIO
VDDIO
VDDIO
b1
b
b
a
VSSIO
b1

Flip-Chip Routed Example

I/O Placement and Flip Chip
❑ I/O cell Placement is performed
after initial floorplan creation
❑ Flip-chip and non-flip chip
designs use the same I/O cell
placement command.
❑ I/O constraints provide easy and
flexible driver location control.
* Create Bump Cells
Create I/O Guides
Set I/O Constraints (Optional)
Place I/O Cells
* RDL Routing
* Flip-Chip specific steps

Bump Cell Creation
* Create Bump Cells
Create I/O Guides
Place I/O Cells
Create Initial Floorplan
Met Requirements?
NO
❑ Instantiate the bump cells
before placing the I/O drivers.
❑ Bump Cells can be created by
reading DEF, AIF, or by using:
Create_bump_array

Placing Bump Cell
❑ Bump array pattern options
❑ Example of an inline bump array
create_bump_array -lib_cell bc -bbox {{x1 y1} {x2 y2}}
-origin {offset_x offset_y} -pattern inline -delta {dx dy}

Create I/O Guides
* Create Bump Cells
Create I/O Guides
Place I/O Cells
Met Requirements?
NO
❑ I/O Cells are placed along I/O guides
o Must be created before placing the
I/O Cells
o or:
create_io_guide
create_io_ring

Create I/O Guide Examples

I/O Placement Constraints
* Create Bump Cells
Create I/O Guides
Place I/O Cells
Met Requirements?
NO
❑ Control I/O driver location and Pad
abutment.
❑ Adjustable I/O driver ordering
spacing
❑ Supports signal as well as power I/O
drivers
set_signal_io_constraints

Specifying Signal I/O Constraints

Specifying Signal I/O Constraints
❑ Signal ordering begins at the lower-left pad for the left edge, the
upper-left pad for the top edge, the upper-right pad for the right
edge, and the lower-right pad for the bottom edge as shown in Figure.
Example 1: I/O Constraints File Example
ring.top
{80}
{{55} Pad_1 Pad_2 Pad_3}
{10}
{Pad_4 40 Pad_5 60 Pad_6}
{Pad_7 Pad_8}
;

I/O Signal Constraints File Example

Placing I/O Cells
* Create Bump Cells
Create I/O Guides
Place I/O Cells
Met Requirements?
NO
❑ I/O drivers are placed in the
specified I/O guides, according to
the constraints.
❑ The location of all I/O drivers is
derived by searching for mapping,
and then connecting the RDL net to
the bumps
Place_io

RDL Pathline Display
❑ What is a Pathline used for?
• RDL Pathlines show the possible paths of RDL routes
• RDL Pathlines help to identify problems in I/O driver placement
• RDL Pathlines are piecewise linear and do not overlap with bumps
❑ TO view pathlines from the GUI:
View → RDL Flylines

Identifying Macro Placements
❑ Use flylines to show macro connections
❑ Place macros so that the connections between
them and the IO pads are direct and shortest
❑ Modifying macro-orientation can often make
shorter, more direct connections

Hard Macro Placement
❑ When placing large macros we must consider impacts on routing, timing and power.
Usually, push them to the sides of the floorplan.
o Placement algorithms generally perform better with a single large rectangular placement
area
o For wire-bond place power-hungry macros away from the chip center
❑ After placing hard macros, mark them as FIXED.

Placement Blockages and Halos
❑ Placement blockage halos are areas that the tools
should not place any cells.
❑ These, too, have several types:
• Hard Blockage – no cells can be placed
inside.
• Soft Blockage – cannot be used during
placement but may be used during
optimization.
• Partial Blockage – an area with lower
utilization.
❑ Halo (padding) – an area outside a macro that
should be kept clear of standard cells
RAM5
Pins are on
left and right
Create_placement_blockage -type hard -outer {10 0 10 0} RAM5
{left bottom right top}
hard or soft

Macro Keepout Margin (Padding)
RAM5
Pins are
on left
and right
A keepout margin is a region around the boundary of
fixed macros in the design in which no other cells are
placed.
Keepout
margin
set_keepout_margin -type hard -outer {10 0 10 0} RAM5
{left bottom right top}
hard or soft

Placemen Blockages and Halos
RAM4
RAM2
RAM1 RAM3
RAM5
Soft blockage created
only for the channels
between the macros or
between the macro and
the core boundary
Hard blockage
always created on all
four sides

Soft and Hard Placement Blockage
Macro 1 Macro 2
Hard blockage prevents
standard cells from being
placed in this region.
Soft blockage allows new
buffers/inverters to be
inserted during optimization.
Hard placement blockage
Soft placement blockage

Routing Blockage (Route Guide)
create_route_guide –no_signal_layer {METAL5 METAL6}
-coordinate {{20 20} {75 95}}
RAM4
(20,20)
(75,95)
Routing
blockage
❑ Routing blockages are used to
prevent the route in a particular
area for the specific metal layer for
all nets or only signal nets or PG
nets.
❑ Routing blockages – areas where
routing is not allowed

A Good Floorplan
PLL
RAM
RAM
RAMS out of
the way in the
corner
Large
routing
channels
RAM
No 4 way
intersections.
MY_SUB_BLOCK
Standard cells area
Single large
partition
Pins away
from corners

Balance Routing Resources
❑ If less vertical routing resources are available, make floorplan wider
(aspect ratio < 1) if possible, to increase vertical routing resources
❑ If less horizontal routing resources are available, make floorplan
taller (aspect ratio > 1) if possible,
to increase horizontal routing resources
Balancing vertical/horizontal routing resources reduces overall
congestion.

Crater Lake or Thousand Island
RAM
RAM
RAM
STANDARD
CELLS
RAM RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
Crater Lake
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
STANDARD
CELLS
Thousand Island

Guidelines for a good floorplan
RAM 1 RAM 2 RAM 3
RAM 4 RAM 5 RAM 6
RAM 8
Use blockage
to improve pin
accessibility.
RAM 7
Avoid many pins in the
narrow channel. Rotate
for pin accessibility.
Avoid constrictive
channels.

Placement Bounds
© Ahmed Abdelazeem. All rights reserved 54
2/28/2024
❑ Sometimes, we want to “help” the tool put certain logic in
certain regions or cluster them together.
❑ Place and Route tools define several types of placement
bounds:
• Soft move bounds specify placement goals, with no
guarantee that the cells will be placed inside the
bounds.
• Hard move bounds force placement of the specified
cells inside the bounds.
• Exclusive move bounds force the placement of the
specified cells inside the bounds. All other cells must
be placed outside the bounds.

Hierarchical Approach
◼ Chip is partitioned into smaller blocks
◼ Each block is P&R'ed
individually in ICC II
◼ Blocks are integrated
back into the chip
◼ ICC II routes top-level
nets
IP
RAM
Block 2
Block 1
Block 3

Chip vs. Block
Blocks can be rectangular or rectilinear in
shape.
◼ Chip has:
⚫ Pads (signal and P/G)
◼ Block has:
⚫ Pins (signals and P/G)
IP
RAM
Block 2
Block 1
Block 3

Building The Power Network
Design the Power Network
Apply the PG Strategies
PG Verification and Analysis

Objective of Power Network
❑ Power planning is deciding how
we will deliver power to the
design’s standard cells!
❑ What is the importance of having a
power network with low impedance?
• All analysis and optimization done in
logic synthesis and PnR is based on the
fact that cells are supplied with ideal
voltage…
• If the actual circuit supply is significantly
different, cell operation will be different
from the behavior characterized in the
.libs, which will cause all types of timing
Violations

Objective of Power Network
❑ To distribute the power from power
pads to all elements in the chip.
❑ Unified supply of power with less
voltage drop
❑ A proper Power design should aim
at using as less routing recourse as
possible.
❑ Power Analysis (EMIR) check
should be done after power planning
is completed
❑ A design with a robust power and
ground (PG) grid reduces IR drop
and electromigration by providing
an adequate number of power and
ground pads and rails.
Power pads
(VDD, VSS)
Power straps
(in Red)
(VDD, VSS)
Power rings
(VDD, VSS)
Power trunks
(VDD, VSS)

Power Planning
❑ Creation of the power network within a design
❑ Power planning is integrated with the overall design flow and must be taken into
account early in the design process because:
• # of pads may determine physical size (pad limited). The power structures within the core
area consume the physical area.
• The power grid topology affects top-level routability, and also placement and routing
within the child blocks.
• The power structure affects functionality and reliability.

Power Network Elements
❑ Power Pad
❑ Trunks
• Connects Ring to Power Pad
❑ Power Rings
• Form complete rings around the periphery of the die,
around individual hard macros, or inside of
hierarchical blocks with higher-level Metal layers
Power
❑ Power Stripes
• Carries VDD and VSS from Rings across the chip
Horizontal and vertical metal wires placed in an array
across the entire section die
• higher level routing layers
• typically uniformly distributed across the die.
❑ Power Rails
• Is used to connect the standard cell power rails
together, and or power straps.
• Low level, typically metal 1.
Power pads
( VDD, VSS )
Power straps
( VDD, VSS )
Power rings
( VDD, VSS )

Power Planning
❑ Power Planning includes:
• Proper estimation of the power of the chip.
• power routing the design based on the estimation.
❑ We create a mesh kind of structure so that instance(s) can
take direct supply from the nearest point
❑ We create multiple VDD and VSS lines(for each power
domain)
❑ Hierarchical Mesh from upper metal layers to lowest(Ml or
M2 layers for standard cells). Connection from higher to
adjacent lower metal layer is through VIAs

Power Mesh
❑ Power/Ground mesh will allow multiple
paths from P/G sources to destinations
• Hierarchical power and ground meshes
from upper metal layers to lower metal
layers
• Multiple vias between layers

Why create mesh kind of structure ?
❑ To distribute the Power from power
pads/pins to all elements of the chip.
❑ Provides multiple paths from PG sources to
destinations (less series resistance)
❑ Uniformly distribute power with less voltage
drop.
❑ To meet IR/EM targets
❑ For meeting timing requirements

Power Grid Planning
❑ Steps in Power Grid Planning
◦ Determine the number of power pads
◦ Determine which metal layers will be used for
power routing
◦ Define the width of the top-level power bus
◦ Determine the structure for block and macro-
level power routing
◦ Power Network Analysis (PNA)

Top-level Power Network
❑Supported topology with PNS
◦ PNS currently creates a (rectilinear)
power plan with/without a core ring
connected to a power mesh
❑ User can specify
◦ Number of straps: Min, max
◦ Width of straps: Min, Max
◦ Width of ring
◦ Layers

Block Level Power Network
IP2
IP1
❑ Power network synthesis can
automatically create the power
structures for the whole chip,
including rings and strapping for
macros and IP.
❑ This is done based upon power
estimates or power analysis and
utilizes IR-drop requirements as
well as metal layer information
like layers to be used with max
number and max width of straps,
etc. to constrain the meshes that
are created.

Inputs and Outputs of PNS

Power Planning vs. Power Routing

Power Planning Challenges
❑ Many designs have multiple voltage areas
and hierarchical blocks
• Each area requires a specific mesh
structure
❑ Complex Core rings
❑ Special P/G Patterns

Pattern-Based Power Network Synthesis
❑ Define regions for PG routing
❑ Define Patterns (PG Structure)
• Metal layer, spacing, width, ...
• Can use parameters
❑ Define Strategy (P/G topology)
• Applies specific patterns to specific regions,
and specific power/ground nets, using
flexible via control
• Flexible to floorplan change (no fixed
coordinates)
❑ Create the power network

PPNS Flow
Define PG region
Patterns:
Define PG Structure
Strategy:
Define PG topology
Compile:
Synthesize PG
𝑀𝑒𝑠ℎ 𝑃𝑎𝑡𝑡𝑒𝑟𝑛
𝐶𝑜𝑚𝑝𝑜𝑠𝑖𝑡𝑒 𝑃𝑎𝑡𝑡𝑒𝑟𝑛
𝑊𝑖𝑟𝑒 𝑃𝑎𝑡𝑡𝑒𝑟𝑛
𝑆𝑝𝑒𝑐𝑖𝑎𝑙 𝑃𝑎𝑡𝑡𝑒𝑟𝑛
𝑆𝑡𝑎𝑛𝑑𝑎𝑟𝑑 𝐶𝑒𝑙𝑙 𝑟𝑎𝑖𝑙 𝑃𝑎𝑡𝑡𝑒𝑟𝑛
𝑃𝑎𝑡𝑡𝑒𝑟𝑛 𝑁𝑎𝑚𝑒
𝑁𝑒𝑡 𝑁𝑎𝑚𝑒𝑠
𝑂𝑓𝑓𝑠𝑒𝑡
𝑅𝑒𝑔𝑖𝑜𝑛
𝐵𝑙𝑜𝑘𝑎𝑔𝑒
𝐸𝑥𝑡𝑒𝑛𝑠𝑖𝑜𝑛
ቊ
𝑆𝑡𝑟𝑎𝑡𝑒𝑔𝑦 𝑛𝑎𝑚𝑒𝑠
𝑉𝑖𝑎 𝑅𝑢𝑙𝑒𝑠
ሼ𝑃𝐺 𝑁𝑒𝑡𝑤𝑜𝑟𝑘 𝑅𝑜𝑢𝑡𝑖𝑛𝑔 𝑎𝑟𝑒𝑎

PG Region
Region r1
Defined on the core area.
Two large macros excluded.
create_pg_region r1 –core
-exclude_macros {u_one u_two}
-macro_offset 5.0
❑ PG regions can be created on
• Core area
• Blocks
• Voltage area
• Macros/groups of macros
• Groups of regions
• Polygon

PG Rings
create_pg_region r1 -core
-exclude_macros {u_one u_two}
-macro_offset 5.0
create_pg_ring_pattern ring1
-horizontal_layer M5
-vertical_layer M4
-horizontal_width 2.0
-vertical_width 2.0
set_pg_strategy s1
-pg_regions {r1}
-pattern {
{name: ring1}
{nets: {vdd vss}} }
compile_pg -strategies s1

Blockage, Parameters, Extension
create_pg_ring_pattern ring1
-paramters {hw vw}
-horizontal_layer M5 -vertical_layer M4
-horizontal_width {@hw}
-vertical_width {@vw}
set_pg_strategy s2
-pg_regions {r1}
-blockage {voltage_areas: r2}
-pattern {
{name: ring1}
{nets: {vdd vss}}
{paramters: {3 2}}
{offset: {4 2}}
{skip_sides: 1} }
-extension {
{side: 2 6}
{direction: L}
{stop: outermost_ring} }

PG Meshes
Optional: Define a via rule
Define a mesh Pattern,
optionally with via rules
between layers
set a strategy on a region, a
block or VA using the pattern
Optional: Define a via rule
between strategies and/or
exiting shapes
compile the strategies,
optionally along with a via
strategy
1
2
3
4
5
set_pg_via_master_rule via1
create_pg_mesh_pattern mesh1
-layers ...
-via_rule ...
set_pg_strategy s_1
-pg_regions | -blockage | -voltage_areas
-pattern ...
set_pg_strategy_via_rule v_1
compile_pg
-strategies {s_1 s_2}
-via_rule {v_1}

Creating a PG Mesh Pattern
create_pg_mesh_pattern mesh1
-layers {
{{horizontal_layer: M5} {width: 6} {spacing: 1} {pitch: 12} {offset: 5} }
{{vertical_layer: M6} {width: 6} {spacing: 2} {pitch: 20} {offset: 6}}
}
-via_rule {
{{layers: M5} {layers: M6} {via_master: VIA56_2x3}}
}

Defining a Custom PG Vias
set_pg_strategy_via_rule VIA36_2x3
-contact_code {VIA34SQ VIA45SQ VIA56SQ}
-via_array_dimension {2 3}
-offset {0.2 0.1}
-offset_start center (default)
intersection of
M3/M6
Default contacts will be used, unless
you specify one or all contact codes
needed to connect from M3 to M6
contact code:
via_array_dimension: 2x3
offset: (xy)
cut_spacing: (dx dy)

Meshes using Wire and Composite Pattern

Setting the Strategy

Defining Via Rules between Objects
Specify via rules to make specific connections between
the straps of different strategies, or between strategies
and existing shapes
set_pg_strategy_via_rule s_via_m2_m7
-via_rule {
{ { {strategies: {s_m2} {layers: {M2}} } }
{ {strategies: {s_m7m8} {layers: {M7}} } }
{via_master: {pgvia_1x3}}
}
}
To prevent vias of begin inserted between 2 strategies, use
the keyword "NIL" for the Via Specification

Standard Cell Connection Pattern
create_pg_std_cell_conn_patter std_pat2
-parameters {w d}
-layers {M2 M1}
-rail_width {@w}
-rail_shift {@d}
create_pg_std_cell_conn_patter std_pat1
-layers {M1}
set_pg_strategy s_std_cells -core
-pattern { {name: std_pat1} {nets: {VDD VSS}} }
-extension {{stop: innermost_ring}}
compile_pg -strategies s_std_cells

Compiling the PG Mesh
compile_pg

PG Network Checks
❑ Verify whether the current routing of PG nets satisfies technology design rules
❑ Check Missing Vias in the PG Network
❑ Connectivity check for PG networks, including macro and standard cell PG pins, PG
pads, and block terminals
Check_pg_drc
Check_pg_missing_vias
Check_pg_connectivity

Power Network Analysis
❑ After the creation of power network rings,
straps, and IO connections:
• The power network does not have to be
complete
❑ Run PNA to analyze the power network
• Voltage drop and electromigration
❑ Early Static IR drop analysis
• Provides rough estimation of the chip IR drop
and Peak Current
❑ Rough Placement Ok
• Detailed, Legalized Placement not required
❑ Adjust the power network to solve reported
issues

Objectives of PNA
❑ Power Network Analysis is needed for power network planning and synthesis as it forms
the core of the IR and EM analysis that is required to ensure that PNS goals are met.
PNS
PNA
Design
Planning

Power Network Analysis
Power
Routing
Pad
AND
gate
NOR
gate
Height of the current density Height of the power voltage
❑ Electromigration analysis
▪ Current density analysis for every power segment
▪ Too high current density leads to damaged interconnect, reduced
the useful life of chip and reliability issue
❑ Voltage Drop Analysis
▪ Voltage drop at each node of power network
▪ Too low power supply voltage leads to increased delay and timing issues

IR-drop
❑ Reduction in voltage that occurs on power supply networks
❑ IC design expects the availability of the ideal power supply
❑ In reality, localized voltage drops within the power grid
• Increasing current/area on the die
• Narrower metal line widths (increases power grid resistance)
❑ Results in decreased power supply voltage at cells/transistors
❑ Decreases the operating voltage of the chip, resulting in timing and functional failures

Reasons for IR Drop Violations
❑ Power structure is not proper.
❑ Cell density is very high.
❑ Instances are not getting proper power because of no straps over there
❑ Mesh structure is proper but there is no via

How to reduce IR drop?
❑ Routing should be from the Top Layer.
❑ By adding some more Power Stripes.
❑ By increasing the width of the metal.
❑ By adding Decaps(DCAP cells).
❑ By using some Low Power Techniques

PNA: IR Drop Analysis
Metal 5 and Metal 4 power trunks and Metal 1 straps
IR Drop = 370mv
Metal 5 and Metal 4 power trunks only, no straps
IR Drop = 378mv
Rail Signoff
Power Network Analysis During
Floorplanning

Electromigration
❑ Electromigration is the movement of atoms based on the flow of current through a
material.
❑ If the current density is high enough, the heat dissipated within the material will
repeatedly break atoms from the structure and move them.
❑ Results of EM in ICs: The VOIDs and HILLOCKS get created and potentially causing
open and short Circuits.

Reasons of EM violation
❑ High Fanout Net (multiple fanout cells switch simultaneously, draw larger current from
driver)
❑ Higher Driver Strength Cells(delivers large current unnecessarily, heating up the wire)
❑ Higher frequency(quick transitions)
❑ Narrow metal width
❑ Metal slotting (resulting in narrower widths)
❑ Long Nets (because of larger resistance, higher localized temperature)

Solutions of EM violations
❑ Decrease Driver’s drive Strength.
❑ Non-Default (wider) rule-based routing.
❑ Insert buffer on long nets.
❑ Route with higher metal layers(less resistive, higher tolerance (current carrying capabilities)
❑ Use multi-Cut Via
❑ Break the fanout (have fewer fanouts)
❑ Use wider metals (more width)

Power Network Analysis Electromigration
❑ PNA checks power grid electromigration with the same parasitic model used by IR-Drop
calculations
❑ Analyzes average current as damage is cumulative
❑ More sensitive to DC current than AC current

Analyze the Power Network
analyze_power_plan -nets {VDD} -voltage 0.75
-power_budget 500
If necessary, modify the patterns and/or
strategies and re-build -repeat until IR
drop is acceptable

A Complete Placed and Routed Chip
IP

References
❑ IDESA
❑ Digital Integrated Circuits: A Design Perspective by Rabaey
❑ CMOS VLSI Design: A circuits and systems perspective by David Harris
and Neil Weste
❑ EPFL Tutorial
❑ Synopsys University Courseware
❑ IC Compiler User Guide
❑ Experience!

Thank You ☺

6. Design Planning.pdf

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6. Design Planning.pdf