9. Routing.pdf

Digital
Implementation
Routing & Optimization
© Ahmed Abdelazeem. All rights reserved 1

Contents
After completing this unit, you should be able to:
❑ Perform pre-routing checks and setup
❑ Route the signal nets using route_auto
❑ Optimize the design using route_opt
❑ Report and fix DRC violations
3/6/2024 2
© Ahmed Abdelazeem. All rights reserved

Facilities
Building Hours
Restrooms
Meals
Messages
Smoking
Recycling
Phones
Emergency EXIT
Please turn off cell phones and pagers
3
3/6/2024

Workshop Goal
Use IC Compiler II to perform placement, DFT,
CTS, routing and optimization, achieving timing
closure for designs with moderate to high design
challenges.
4
3/6/2024

Target Audience
ASIC, back-end or layout designers with
experience in standard cell-based automatic
Place&Route.
5
3/6/2024

High-Level IC Compiler Flow
Gate-level netlist
Synthesis
Design & Time Setup
Floorplan Definition
Placement & Optimization
CTS & Optimization
Routing & Optimization
Signoff
IC
Compiler
II
6
3/6/2024 © Ahmed Abdelazeem. All rights reserved
✓
✓


Design Status, Start of Routing Phase
3/6/2024 © Ahmed Abdelazeem. All rights reserved 7
❑ Placement - completed
❑ CTS – completed
❑ Power and ground nets - routed
❑ Estimated congestion - acceptable
❑ Estimated timing - acceptable (~0ns slack)
❑ Estimated max cap/transition – no violations
check_design –checks pre_route_stage

Routing Phase Goal
❑ Placement and GTS should be completed
• Acceptable congestion, setup/hold timing, and logical DRCs
• Clock nets should be routed
❑ The goal of the routing phase is to:
• Route all the signal nets with minimal physical DRC violations
• Optionally perform post-route CTO or CCD
• Optimize datapath logic for timing, DRCs, and power

Routing Fundamentals: Goal
❑ Routing creates physical connections to all clock and signal pins through metal
interconnects
• Routed paths must meet setup and hold timing, max cap/trans, and clock skew
requirements
• Metal traces must meet physical DRC requirements

Grid-Based Routing System
❑ Metal traces (routes) are built along and
centered upon routing tracks based on a
grid.
❑ Each metal layer has its own grid and
preferred routing direction:
• M1: Horizontal
• M2: Vertical, etc…
❑ The tracks and preferred routing
directions are defined in a "unitTile" cell
in the standard cell library
Track
Pitch
(based on DRC)
Grid Point
M1
Trace
M2
unitTile

ICC II Routing Flow
The "routing phase" involves
several key steps:
❑ Pre-routing checks and setup
❑ signal routing
❑ Optimization and rerouting
CTS + Clock
Routing
Pre-routing checks and
setup
Routing
Optimization and
Reroute
Signoff
Routing

Routing Operations
❑ IC Compiler II performs:
• Global Routing
• Track Assignment
• Detail Routing
• Search and Repair
❑ After global routing, track
assignment and detail routing all clock/signal nets
will be completely routed and should meet all timing,
and most all DRC, requirements
❑ Any remaining DRC violations can be fixed by Search&Repair
Track Assign
Global Route
Detail Route
Search&Repair

Recommended Routing Flow
❑ Clock nets should have been routed already
❑ Signal nets are routed first- no cell optimization:
• Routing performs:
Global Routing →Track Assignment →Detail Routing
❑ Afterwards, post-route optimization is performed:
• Concurrently optimizes:
❖ Timing and max-tran/max-cap (by default),
❖ Clock tree, power (optionally)
❖ Optionally uses PrimeTime delay calculation and StarRC Extraction
route_auto
route_opt

Global Routing
NAND AOI
DFF NOR DFF
INV
DFF NOR
❑ Determining overall path of all
routes
• Picking channels to route through
❑ Seeking to reduce delay, channel
widths

Global Routing :Objectives and Frameworks
❑ Objectives
• Minimizing wire length
• Balancing congestion
• Timing-driven
• Noise-driven
• Keeping buses together
❑ Frameworks
• Channel-based routing

Route Operations: Global Route (GR)
❑ GR assigns nets to specific metal layers (in the preferred routing direction) and through
specific global routing cells (GRC or Gcells)
❑ No metal traces are created
• Uses colored zero-width lines to indicate global routes and
• assigned metal layers
❑ GR tries to avoid congested Gcells while minimizing detours:
• Congestion exists when more tracks are needed than available
• Detours increase wire length (delay)
❑ GR also avoids:
• P/G (rings/straps/rails)
• Routing blockages
global route
congestion area

Route Operations: Global Route Summary
❑ Global routing does not create
metal shapes
• You can select and interact with
global routing in the GUI
Global
route
Global
route
Preroute
Preroute

Route Operations: Track Assignment
❑ Track Assignment (TA):
• Assigns each net to a specific
track and lays down the actual
metal traces
❑ It also attempts to:
• Route each layer in its preferred
direction
• Make long, straight traces
• Reduce the number
of vias
❑ TA does not check or follow
physical DRC rules
❑ After Track Assign, there should
be no global routes or GR vias left
TA metal
traces
TA metal
traces
Preroute
Preroute
Jog reduces
via count

Detailed Routing
Partitioning
Floorplanning
Placement
Global Routing
Detailed Routing
Compaction
NAND AOI
DFF NOR DFF
INV
DFF NOR
Detailed routing realizes the interconnection between each
connected pair of pins in the region, which has been defined
with the result of global routing.
❑ Determining exactly how each signal is
routed through each region
❑ Seeking to reduce routing area

Route Operations: Detail Routing
❑ Detail route fixes physical design rule violations
❑ Performs multiple iterations with varying repair box sizes
Detail Route SBoxes
Min
Spacing
Thin&Fat
Spacing
Notch
Spacing
Notch
Spacing

Detailed Routing: Vias
❑ Via selection
• Via array based on wire size or resistance
• Rectangular via rotation and offset
Rotate and offset horizontal vias No rotation for a “cross” via

Route Operations: Search&Repair
❑ Search&Repair fixes remaining DRC violations through multiple loops using
progressively larger SBox sizes
Note: Even if the design is DRC clean after S&R, you must still run a sign-off DRC
checker (ICV).
• Routing DRC rules are a subset of the complete technology DRC rules
• IC Compiler II works on the FRAM view, not the detailed transistor-level (CEL) view
Loop1
Loop2
Loop3
Loop4

Change the Preferred Routing Direction
❑ By default, physical synthesis tool
will:
• Route over macros
• Not route where there is a routing
blockage
• Not route through a narrow channel in
the non-preferred routing direction
The preferred routing direction needs to be changed
M1- M4 Routing Blockage
Macro
M4 has a horizontal
routing channel but its
preferred routing
direction is vertical

Test for Understanding
❑ What does Global Routing do in congested areas?
❑ Assignment of nets to metal layers is done during the Track Assignment stage. T or F?
❑ When does IC Compiler use SBoxes? Are they always the same size?
❑ Does IC Compiler II find all the DRC violations, making a Hercules or other sign-off
level DRC extraction run unnecessary?
❑ Will IC Compiler II route a metal trace in the “non-preferred” direction?
❑ Serious Congestion can create
1. Timing Violation
2. Max transition/Capacitance DRC Violations
3. An un-routable design
4. All of the above

Routability Check
❑ The routability check calls check_routability to confirm that the design is ready
for routing:
• Blocked ports, out-of-boundary pins
➢ A logical port can have several physical pins
➢ A port is considered blocked if none of its pins are accessible
• Pin access edge rules honored
• Minimum-grid violations
Fix before
performing
detail routing

Secondary PG Pin Connections
❑ Secondary PG pins (e.g. backup power/ground for
always-on cells) should be routed first
❑ By default, there is no maximum to the number of PG
pin connections from a strap - choose your own
maximum value based on your PG grid
route_group -nets {VDDL}
et_app_options -list
{route.common.number_of_secondary_pg_pin_connections 4}
Low
voltage
area
High
voltage
areas
H
H
VDDH
VDDH
VDDL

NDRs for Secondary PG Routing
❑ It is not uncommon to use NDRs for Secondary PG
• Restrict routing to certain layers
• Use only certain vias
• Specify width
set_app_options -list {
route.common.separate_tie_off_from_secondary_pg true }
create_routing_rule sec_pg
-widths {Ml 0.2 M2 0.2 M3 0.2}
-vias {...}
set_routing_rule {VDDH} -rule sec_pg
-min_routing_layer M2
-max_routing_layer M3
route_group -nets {VDDH}
Prevents tie-off
connections from
using NDRs

Inserting Redundant Vias on Signal Nets
❑ Replaces single-cut vias with multiple-cut via arrays or another single-cut via with a
better contact code (done for DFM and Reliability)
• By default, single-cut vias are replaced by two-cut via arrays
➢ Use add_via_mapping for custom via mapping (see appendix)

Redundant Vias and Small Geometries
❑ In smaller geometries (< 20nm), it is recommended to reserve space and run standalone
add_redundant_vias after detail route changes (to improve DRC convergence and
minimize overall runtime)
• Perform redundant via insertion again after completing all post-route optimization runs
➢ RVI runtime is high- perform fewer RVI runs
• Make sure that your design has no routing DRC violations before performing RVI
route.common.post_detail_route_redundant_via_insertion off
route.common.concurrent_redundant_via_mode reserve_space
route.common.eco_route_concurrent_redundant_via_mode reserve_space }
route_auto
route detail -incremental true
add_redundant_vias
...
route_opt
add_redundant_vias

Enable Wire and Via Optimization
❑ Via and wire optimization is recommended when adding redundant vias
• Attempts to make long straight traces and reduce the need for vias (using small jogs in
non-preferred direction)
• Default effort is low → Set to high
• Alternatively, use optimize_routes to run this same optimization stand-alone after
route_auto
route.detail.optimize_wire_via_effort_level high }

Problem: Gate Oxide Integrity
Oxide
Poly
Metal 1
Protective coating
Damaged Gate Oxide
Oscillating charges in Plasma Etch
❑ Metal wires (antennae) placed in an EM field generate voltage gradients
❑ During the metal etch stage, strong EM fields are used to stimulate the plasma
etchant
❑ Resultant voltage gradients at MOSFET gates can damage the thin oxide

Antenna Rules
❑ As the length of the wire increases during processing, the voltage stressing the gate
oxide increases
❑ Antenna rules define the acceptable length of wires
Antenna Ratios:
Area of Metal Connected to Gate
Combined Area of Gate
Or
Area of Metal Connected to Gate
Combined Perimeter of Gate
poly
diffusion
gate

Solution 1: Metal Splitting or Layer Jumping
After layer jumping, to meet Antenna rules
Before layer jumping
Acceptable antenna area
Unacceptable antenna area
driver
diffusion
gate
poly
metal 1
M1
blockage
metal 3
driver
diffusion
gate
poly
metal 1
M1
blockage
metal 3 metal 3
M1 is split
by jumping
to M3 and
back
M3 blockage
M3 blockage

Solution 2: Inserting Diodes
During etch phase, the diode clamps the voltage swings.
Before inserting diodes
Diode Inhibits large voltage
swings on metal tracks

Concurrent Antenna Fixing: Layer Jumping
❑ Antenna rule violations can be fixed by layer jumping (hopping) and by diode insertion
• Layer jumping is recommended during detail route
• Diode insertion is recommended post-route
❑ Concurrent Layer Jumping during detailed routing is enabled, by default
• Requires antenna rules provided as a TCL file
❑ Diode insertion is disabled, by default
• Usually performed during the final block preparation phase
source antenna_rules.tcl

Controlling Router Behavior: Routing Guides
❑ Using a routing guide, you can change the default routing behavior in a particular area,
e.g. change the preferred routing direction:
❑ Other uses:
• Change track utilization percentage
• Use river routing
“If you have limited metal layers (e.g. 5), and a RAM uses M1-M4, so only M5 is
available to route over the macro, river routing will allow M5 to route in the non-
preferred direction over the macro; Without this, the default preferred routing direction
would cause the router to create shorts over the macro”
create_routing_guide -name rg_0 -boundary {{270 340} {491 385}}
-layers {M6} -switch_preferred_direction

Routing over Macros
◼ By default IC Compiler II will:
• Route over macros
• Not route where there is
a routing blockage
• Not route through a narrow
channel in the non-preferred
routing direction
You need to change the preferred routing direction!
Macro
M4 has a horizontal routing channel but
its preferred routing direction is vertical.

Preventing Routing: Routing Blockages
❑ To prevent signal routing in a certain area, define a routing blockage:
❑ Routing guides and blockages should be applied before place_opt, as they are fully
respected by global routing as well
create_routing_blockage
-layers layers
-boundary {list_of_points}
[-net_types net_type_list]
[-zero_spacing]
[-reserve_for_top_level_routing]
[-nets list_of_nets] ...

What is Crosstalk?
Cc
Static victim Switching victim
Aggressor
Victim
net 1
net 2
Aggressor
Crosstalk is the transfer of a voltage transition from one
switching net (aggressor) to another static or switching net
(victim) through a coupling capacitance (Cc)

Crosstalk-Induced Noise (aka Glitches)
Cc
Aggressor nets can create crosstalk-induced noise on static victim nets, also
called “static noise”
Aggressor
Victim
“Static noise”
net 1
net 2

Crosstalk-Induced Delay
Cc
Aggressor/victim nets with overlapping timing windows can cause “crosstalk-induced
delay” on victim nets.
This can lead to a speed-up or a slow-down of the victim net
Aggressor
Victim
Delay
net 1
net 2

Crosstalk Analysis
❑ Enable crosstalk delta delay
• Delta delay affects setup and hold timing
• Affects timing of the net, and therefore affects timing driven routing
❑ Delta Delay Calculation takes timing arrival windows into account
set_app_options -name time.si_enable_analysis -value true
time.enable_si_timing_windows

Crosstalk Prevention
❑ Crosstalk prevention happens during routing
❑ Prevention avoids putting long parallel nets on adjacent tracks
• Focuses on timing-critical nets
❑ Prevention is controlled by:
• Current recommendation:
➢ Enable crosstalk only during track assignment
• Enabling crosstalk during global routing has shown mixed results
route_auto
set_app_options -name route.global.crosstalk_driven -value false
set_app_options -name route.track.crosstalk_driven -value true

Static Noise
❑ Noise analysis is also enabled with SI:
• Uses CCSN libraries
• Supports a user-defined noise margin(set_noise_margin)
• Noise optimization not available currently
❑ To report static noise violations, use:
time.si_enable_analysis
icc2_shell> report_noise -nworst_pins 5
noise_region: above_low
pin name width height slack
----------------------------------------------------
U954/B 1.091 0.290 0.082
noise_region: below_high
pin name width height slack
----------------------------------------------------
U8767/I 2.191 0.407 0.035

Route the Signal Nets
❑ Initial routing entails global routing, track assignment and detail routing - no post-route
optimization
❑ To run the three phases individually:
❑ Modify routing or crosstalk options, routing guides, or via mapping rules and re-route,
as needed
route_auto
route_global
route_track
route_detail

Detail Route Iterations
❑ By default, route_auto performs a maximum of 40 detail route iterations to fix
DRCs
❑ If your technology requires more iterations, set the value using:
route_auto -max_detail_route_iterations 60

Check Zroute DRC Violations
❑ Checks signal and clock routing for physical DRCs, NDRs, shorts, opens, antenna and
voltage area violations
• Does not check DRCs amongst pre-routed nets only (e.g. P/G grid structure)
check_routes

Layout versus Schematic Check
❑ Use check_lvs to check for open, short, and floating nets
• Errors can be displayed using the error browser
check_lvs -checks all -open_reporting detailed
-check—child_cells true

Detail Routing Loops
❑ Run additional detail route iterations at any time to fix DRC violations
• With -coordinates, you can specify the routing area - multiple rectangles are supported
route_detail
-incremental true
-max_number_iterations 50
-coordinates {{llxl llyl) {urxl uryl} ...}

Post Route Full Optimization
❑ Perform post-route optimization, which includes:
• Post route setup/hold timing optimization
• Logical DRC and Area optimization
• ECO placement and routing
❑ Power, CTO and CCD optimizations are OFF by default
❑ Application options that affect route_opt start with route_opt. *
route_opt

ECOs: Making Changes Late in the Flow
Functional changes occur late in the design cycle.
Deleted
cell
Added
cells

The Two Types of ECO Flows
ECO netlist
Placement
Fixed?
Continue with
ECO routing
Yes NO
Freeze Silicon ECO
Requires that no cells are
moved or added.
Uses spare cells to
perform ECO.
Non-freeze Silicon ECO
Allows new added cells.
Does not require spare cells.
Spare cells are
required
ECO placement
derives the
location for new
added cell
instances

Functional ECO Flows
1. Freeze silicon ECO
• Post-tapeout, metal mask changes, using previously inserted spare cells
• Cell placement remains unchanged
• ECO cells are mapped to spare cells that are closest to the optimal location
• Deleted cells become spare cells
2. Non-Freeze silicon ECO
• Pre-tapeout, no restriction on placement or routing
• Minimal disturbances to the existing layout
• ECO cells are placed close to their optimal locations

Main References
❑ Ron Rutenbar “From Logic to Layout”
❑ Synopsys University Courseware
❑ Synopsys Documentation
❑ IDESA
❑ Cadence Documentation

Thank You ☺

9. Routing.pdf

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