The document proposes a new circuit design for fast XOR-XNOR operations that uses 8 transistors, consumes less power, and has less time delay than the typical 10-transistor design. It also removes the skewed output problem and is more noise tolerant. The document compares the key metrics of the earlier and proposed circuits, such as number of transistors, power dissipation, delays, and noise immunity. It concludes the proposed circuit may be well-suited for low voltage applications and fast arithmetic due to its potential for lower power consumption, higher speed, and greater noise immunity.
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Introduction of a new XOR-XNOR circuit design presented by Ila Sharma and Harsh Magotra.
Focus on features like speed, noise immunity, low voltage consumption with fewer CMOS components.
Definition and function of XOR gate in digital circuits.
Definition and function of XNOR gate in digital circuits.
Illustration of a CMOS-based XOR circuit.
Illustration of a CMOS-based XNOR circuit.
Description of limitations in the traditional XOR-XNOR circuit: high power consumption and delays.
Details of the proposed circuit benefits: reduced transistors, power consumption, time delay.
Description of individual units that comprise the proposed XOR-XNOR circuit.
Visual and functional comparison between the earlier and proposed XOR circuits.
Visual and functional comparison between the earlier and proposed XNOR circuits.
Metrics to evaluate circuit performance: cost, speed, power dissipation, delays, noise tolerance.
Explanation of Noise Immunity Curves (NIC) for measuring the noise tolerance of XOR-XNOR circuits.
Summary of the proposed XOR-XNOR circuit's advantages for low voltage and noise immunity in applications.
Introduction to ourIdea Considering the earlier designs for XOR-XNOR CIRCUIT, we are introducing an idea to make the circuit more fast, noise immune, low voltage consuming…… so we have come with a circuit having less no. of CMOS and posses all the above said features.
Design metricsHow to evaluate the performance of the circuit???CostSpeedPower dissipationDelays Noise tolerance
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Noise toleranceweuse the noise immunity curves, NIC to measure the noise-tolerance of XOR-XNOR circuits.The noise immunity curve ,NIC of a digital gate is a locus of points (Tn, Vn) for which the gate just makes a logic error.The higher the NIC of a gate, the less susceptible is the gate to noise.
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conclusionA new XOR-XNOR circuit implementation has been proposed and it seems that our proposal may be particularly suited for low voltage requirements. From our point of view the most important output of the described proposal is emerging hope that proposed circuit would find use in fast arithmetic operations and will be more noise immune.