Design digital logic gates, adders, multiplexers, and latches using cmos logic in Cadence Virtuoso tool.

1. IITG Internship Program Report
Designing digital logic circuits using Cadence virtuoso
Electronics & Electrical Engineering
Ankita Tiwari

2. Index
0. Studying basic theory about MOSFET
1. Inverter circuits using MOSFET, layout of inverter
2. Universal gates (NOR, NAND gate)
3. Basic gates (OR,AND,XOR gate)
4. Adder (half adder, full adder, ripple carry adder)
5. MUX
6. 3bit-Multiplier
7. Flip-Flop (D, SR)
8. Understanding of PP-KSA (Parallel Prefix Kogge Stone Adder) with PTL (pass transistor logic)

3. 0. Studying basic theory about MOSFET (date: 20~26/1/23)
Referenced book: Design of Analog CMOS integrated circuits.(by Behzad Razavi) – chapter
1&2(Basic MOS Device Physics)
Referenced video : Razavi Electronics 1- Lec 29(intro of MOSFET)~35(common source stage)
What I learned
-Definition of two types of doping and semiconductor(p,n), diode, forward and reverse bias
and rectifying.
-Basic structure of MOSFET and phenomena that vary with the change of gate voltage.
- How drain current(Id) flows in each region(triode, saturation) decided by the voltage
difference between drain and source and its equation and plot.
- How MOSFET works when appropriate VGS and VDS is applied.
- Concept of transconductance and its equation.
- MOSFETs connected in series.
- large & small signal models.
- How to make amplifier using MOSFET
- Difference between PMOS and NMOS

4. 1. Inverter circuits using MOSFET, layout of inverter (date: 27/01/23)
<circuit of inverter>
How it works:
If we input high signal, then PMOS is turned off and only NMOS turned on and signal flows
from Vdd to the ground. Eventually there is no signal at output pin.
If we input low signal, then only PMOS is turned on, works as a switch and current flows
from Vdd to output pin. Eventually we can get high signal at output terminal.
Body of the each MOSFET is both connected to source because there should be no current
flowing from body to doped area and vice verse. So we apply low voltage to body of p-
substrate and high voltage to body of n-substrate to use trait of reverse bias.

5. Result
<Plot of pulse input signal>
<Plot of output signal of inverter>
: When the signal is high, output of inverter is low and vice versa. So I can observe it works
well, as I expected.

6. Layout of inverter
: The above figure is layout of NOT gate. I should have added the result of DRC, but there
was a program error, so it was unable to check the rule. PMOS and NMOS are located at
the top and bottom respectively. Vdd is applied to the source of PMOS which is inside the
n-well.

7. 2. Universal gates
2-1) NAND gate (date: 30/01/23)
<Circuit of NAND gate>
Input signal: v1, v2 output signal: out pin
How it works:
If we input two high inputs(V1=1, V2=1), no current flows at PMOS. Current only flows
through NMOS so the output of signal output.
Output of all other cases(one is high and the other is low or both are low) are equal to 1,
since ground is connected to output pin when v1 and v2 are both high signal.
At first, I thought I can make NAND gate by using inverter and AND gate. So I tried to
make AND gate by connecting two NMOS in series since MOSFET works as a switch, but
the total circuit was totally different from mine. After I tried AND gate, I learned NAND
gate is more basic level in digital logic.
Result

8. <Plot of input, output signal of NAND gate>
: Input signal are both pulse, and the result of output is same as the truth table of NAND
gate.
2-2) NOR gate (date: 02/02/23)
<Circuit of NOR gate>
Input signal: A, B output signal: out_NOR pin
How it works:
Unlike NAND gate, 2 PMOS are connected in series and 2 NMOS are connected in parallel.

9. As a result, we can get high output only when we input both low signal.
Result
<Plot of input, output signal of NOR gate>
: Input signal are both pulse, and the result of output is same as the truth table of NOR
gate. For example, when the time is 30ns, A=1, B=1 and output = 0.

10. 3. Basic gates
3-1) AND gate (date: 31/01/23)
<Circuit of AND gate>
Input signal: v1, v2 output signal: out pin
How it works:
AND gate is addition of NAND gate(left side of the above figure) and inverter(right side),
so we can get complementary output of NAND gate. Output of NAND gate is always 1
except when both inputs are high. Therefore the result of complementary of NAND gate is
always 0 except when both inputs are high.
Result

11. <Plot of input, output signal of AND gate>
Output is 0 when one of the two input is 0 or both are 0 as we expected. For example,
when time is 20ns, v1=1, v2=0 and output = 0
3-2) OR gate (date: 02/02/23)
<Circuit of OR gate>
Input signal: A, B output signal: out_OR pin
How it works:
OR gate is addition of NOR gate and inverter, so we can get complementary output of
NOR gate. Output of NOR gate is always 0 except when both signal is low. Therefore,
complementary of NOR is always 1 except when both signal is low.
Result

12. <Plot of input, output signal of OR gate>
: Output is 0 when both two inputs are 0 as we expected. For example, when time is 15ns,
A=0, B=0 and output = 0
3-3) XOR gate (date: 31/01/23)
<Circuit of XOR gate>
Input signal: A, B output signal: out_XOR

13. How it works
: The results of XOR are 1 (when two input signal is different) or 0( when two input signal
is same). Let’s say two input signal A,B are both high signal. Then Only PMOS with inverter
connected and NMOS without inverter connected operate. Therefore current will flow from Vdd to
ground connected to inverter.
If A,B are both low signal, Only NMOS with inverter connected and PMOS without inverter connected
operate. The current will also flow from Vdd to ground connected to inverter.
If A is low signal and B is high signal(or vice versa), current from Vdd can’t pass the 2 consecutive
series Because one of the two is connected to the inverter unconditionally. Therefore the output
always becomes zero.
Result
<Plot of input, output signal of XOR gate>
:The result shows that when A=B, output is 0.
For example when t=10ns, A=B=1 and out_XOR =0. When t=20ns, A=0, B=1 and out_XOR
=1.

14. 4. Adder(half adder, full adder, ripple carry adder)
4-1) Half adder (date: 02/02/23)
<Circuit of Half adder>
Input signal: A, B output signal: sum, carry_out
How it works:
If the two input signal are both 1, by the binary addition the result should be 10(2)
Carry is made when two inputs are both 1 which means AND gate. Sum is 1 when two inputs are
different which means XOR gate. Therefore by using AND and XOR gate we can calculate 1bit binary
addition.
Result

15. <Plot of input, output signal of Half adder >
: We can see the result of addition by arranging carry_out bit and sum bit in order.
4-2) Full adder (date: 03/02/23)
<Circuit of Full adder>
Input signal: A, B, Cin output signal: sum, carry
How it works
: Full_adder can be made by using 2 half adders and 1 OR gate. First, if we input 2 signals,
A and B, to first half adder we can get carry_out and sum of half adder. After the calculation,
if we input sum result of first half adder and Cin(initial value) to second half adder, we can
get total sum of A,B and Cin. Also if we input carry_out of first and second half adder to
OR gate, we can get total Carry_out bit.
Result

16. <Plot of input, output signal of Full adder >
: When t=5ns, A=1, B=1, Cin =1. we know the sum of 3 input is 11(2) by calculating
manually. The simulation results of sum bit and carry bit are both 1 which means 11(2)
<symbol of Full adder>

17. 4-3) Ripple carry adder (date: 05/02/23)
<Circuit of 4-bit Ripple carry adder>
Input signal: A0~A3, B0~B3 output signal: carry_out, sum1~sum3
How it works
: Ripple carry adder is a series of full adders(hereinafter FA).
If we enter the first two bits(A0, B0 in the figure) and Carry-in(cin in the figure) to first FA,
it produces first carry and sum(sum0 in the figure). Then first carry and second two
bits(A1,B1) are connected to second FA and produces second carry and sum(sum1) and so
on. After all sum bits(sum0~sum3) and carry_out were derived, writing them backward(from
carry_out to sum0) becomes the answer.
Result

18. <Plot of input, output signal of Ripple carry adder>
: Above plots when t=0 to t=10ns are result of addition if we input two 4bit numbers,
(A=1101(2), B=1001(2), cin=1(2)). If we manually add to binary number A and B, the result is
11101(2). The same result can be obtained by arranging the values of sum0~sum3 and
carry_out bit in reverse.

19. 5. Multiplexer (date: 03~05/02/23)
<Circuit of 2X1 MUX>
Input signal: V1,V2,S0 output signal: out pin
How it works
:Output of AND gate is always zero if one of two inputs is zero. MUX uses this
characteristic to select which which of the input data to output. By connecting first AND
gate with standard signal and one of two input signal, we can get one input signal
when standard signal is enough high. By connecting second AND gate with
complementary signal of standard signal and the other input signal, we can get the
other input signal as a result when standard signal is not high enough.
Each time we add one more standard signal, we can choose one signal as a result from
two times more input signals.

20. Result
<Plot of input, output signal of MUX>
: If we observe around t = 10ns(when s0=1, v1=1, v2=0), we can see output is same to v1.
Also if we observe around t = 25ns (when s0=0, v1=1, v2=0), output is same to v2.
6. 2bit signed-Multiplier
<First circuit of 2bit signed-Multiplier >

21. How it works
: 2bit binary number needs one more bit to express negative number. Therefore we
need total 3bits and result of multiplication should also be 3bits to avoid overflow.
However if we multiply two 3bit numbers we can get 6 bits as a result. To avoid overflow
I left out some of parts that express fourth~sixth bits from circuits.
Result
<Plot of input, output signal of first model of multiplier>
: when t = 10ns, input signals are A=111(2), B=110(2). Multiplication result of A and B is
101010(2). Since we can express only first 3bits from the circuits, the answer we can get
is 010(2).
We can also check the answer by calculating manually two numbers. A = -1, B = -2 in
decimal. Result of multiplication is obviously 2(10) and it is 010(2) in binary.
We can conclude it is not perfect circuit but it works well if we want to get 3bit answers.

22. <Second circuit of 2bit signed-Multiplier>
Input signal:A0~A2, B0~B2, Cin output signal: sum0~sum4, carry_out
How it works
: The idea of this circuit is using the characteristic that multiplied by zero results in zero.
For example, let’s say two input numbers are A= a2a1a0, B=b2b1b0. If we input 0 and A0
to MUX and set b0 as a standard signal, we can get 0 when b0 is zero and a0 when b0 is
1. Since a0b0 is same to a0 when b0 is zero, we can get first bit of total number.
Second bit of total number can be produced by calculating a1b0 + a0b1. Addition can be
expressed by FA. a1b0 and a0b1 can be obtained by using MUX. So we can get second bit
of total number.
Other bits can also be obtained through similar procedure.
However I failed to obtain accurate results from simulation. I guess the reason why I failed
is that the signal of b0 is not exactly 1, but that there is a decimal point. In theory, it seems
to be the right idea, but it was different from the reality.

23. 7. Flip-Flop(D,SR)
7-1) D-Flip/Flop (date: 11~13/02/23)
<Circuit of D-Flip/Flop >
Input signal: clk, D output signal: Q, Q’
How it works
:Flip-Flop(hereinafter F/F) works when the value of clock called edge changes. Above D
F/F circuit was designed to work at positive edge. Output of D-F/F is always same to
input signal when clock is positive edge and remember the previous value when clock
is level or negative edge.
In the figure of circuit, we input two signals, clock and D. When clock is 0, output of
both AND gate becomes 0. Output of both AND gates are connected to OR gate each
and the output of OR gates is depend on the other input value. It means previous
output value decides the present output and we can say D-F/F remembers the results.

24. Result
<Plot of input, output signal of D-Flip/Flop >
:When t=20ns, clock is at positive edge and D is high input, so Q is also high signal.
It can be also seen that Q changes together as the D value changes when t=20~30ns
which means high level.
When t =30ns, clock is at negative edge and D is high input, but Q is low signal since
D-F/F remembers the previous value 0.
7-2) SR-Flip/Flop (date: 13/02/23)

25. <Circuit of SR-Flip/Flop >
Input signal: S, R output signal: Q, Q’
How it works
: Above SR-F/F circuit was designed to work when clock is positive edge.Output Q, Q’
is controlled by input signal S and R. When S=1 and R=0, Q is set to 1. When S=0, R=1
Q is reset to 1. We prohibit both S and R from giving high inputs.
In the figure of circuit, if we give (S=1, R=0, clock=1), the AND gates connected to S
and R have a result of 1 and 0, respectively. Then output of OR gate connected to S is
always 1, therefore Q’ becomes 0. Since Q’ is 0, all input value of OR gate connected
to R is 0 and output of the OR gate is also 0. This 0 is reversed by inverter and the
final output Q becomes 1.
By a similar process Q becomes 0 when (S=0, R=1, clock=1).
Lastly, when (S=R=0) or (clock=0), both AND gate output becomes 0. Therefore the
final output is depend on the previous output by the same logic as D-F/F.
Result
<Plot of input, output signal of SR-Flip/Flop >
: From t=0 to t= 10ns (when S=1,R=0, clk=1), value of Q is 1 and Q’ is 0.
Around t =10ns S falls to 0 and R rises to 1. Therefore Q falls to 0.

26. Since clk is 0 after t=10ns, value of Q is retained as 0 even when S and R are both high
signal.
8. Understanding of PP-KSA(Parallel Prefix Kogge Stone Adder)
with PTL(pass transistor logic) (date: 13~17/02/23)
8-1) understanding of basic pp-ksa
Parallel Prefix Kogge Stone Adder is one of various adders which has strong point in
reducing delays. Unlike ripple carry adder, it calculates generation and propagations almost
at the same time without waiting carry from previous stage.
<circuit of basic PP-KSA>
How I made
: When I made a circuit, I basically followed the research paper and compared it with my
own calculation. As a result there were some points that I think errors, so I modified the
circuit myself partially. From the paper there was an open terminal which is useless if it
wasn’t connected to next input terminal. Also some input signals were connected
incorrectly. Above figure is my modified circuit.

27. <plot of basic PP-KSA>
When t= 23ns : A = 0011, B = 1100, Cin = 0001 then, sum0~3 = 0, c0~3 = 1, carry_out = 1
If I write in backwards from carry_out to sum0, the result is 10000(2) It's the same as when we calculate
by hand.
When t= 45ns : A = 1011, B = 1100, Cin = 0000 then, sum0~2 = 1, sum3 =0, c0~3 = 0, carry_out = 1
If I also write in backwards from carry_out to sum0, the result is 10111(2) It's the same as when we
calculate by hand.

28. 8-2) Improvements of weak point
The only weak point of this adder is the size of area it occupies when we use it.
To improve area efficiency, pass transistor logic was suggested from the paper. PTL reduces
the number of PMOS used in OR gate.
< OR gate with PTL> <original OR gate>
OR gate with PTL uses 1 inverter and 2 NMOS. On the other hand original original OR
gate uses 1 inverter, 2NMOS and 2PMOS. Therefore OR gate with PTL has advantages in
both area efficiency and speed.
However when we simulate the OR gate with PTL, the plot is not clear as accurate as
original one because of characteristics of MOSFET.
<plot of OR gate with PTL>
: Logical result of OR gate with PTL is same to original one but the plot above slightly
increases as time passes and has some stretching point. I think the reason of this
phenomenon is related to source connection in MOSFET. So far, source of NMOS was

29. connected to the ground but when using PTL, source is connected to the input signal
which various with time.