The document discusses various logic families and their evolution over time. It begins with an overview of different levels of integration from SSI to VLSI. It then covers topics like TTL logic families, ECL, CMOS families and how they have evolved with lower power and higher speeds. Tables provide parameters and specifications to compare performance of logic families like 74LS, 74F, ECL, 4000 series CMOS and others. Charts show how families are optimized for different supply voltages from 5V down to below 1V.
Finite State Machine (FSM)
Example: Turnstile
Types of Clocked Sequential Circuits
Moore Model
Mealy Model
Example circuits
Analysis of Clocked Sequential Circuits
Example 1: Moore Machine (partial)
Scan design is currently the most popular structured DFT approach. It is implemented by Connecting selected storage elements present in the design into multiple shift registers, called Scan chains.
Scannability Rules -->
The tool perform basic two check
1) It ensures all the defined clocks including set/Reset are at their off-states, the sequential element remain stable and inactive. (S1)
2) It ensures for each defined clocks can capture data when all other defined clocks are off. (S2)
Finite State Machine (FSM)
Example: Turnstile
Types of Clocked Sequential Circuits
Moore Model
Mealy Model
Example circuits
Analysis of Clocked Sequential Circuits
Example 1: Moore Machine (partial)
Scan design is currently the most popular structured DFT approach. It is implemented by Connecting selected storage elements present in the design into multiple shift registers, called Scan chains.
Scannability Rules -->
The tool perform basic two check
1) It ensures all the defined clocks including set/Reset are at their off-states, the sequential element remain stable and inactive. (S1)
2) It ensures for each defined clocks can capture data when all other defined clocks are off. (S2)
Spyglass DFT is comprehensive process of resolving RTL Design issues, thereby ensuring high quality RTL with fewer design bugs.
Improves test quality by diagnosing DFT issues early at RTL or netlist.
Shortens test implementation time and cost by ensuring RTL or netlist is scan-compliant.
A VLSI (Very Large Scale Integration) system integrates millions of “electronic components” in a small area (few mm2 few cm2).
design “efficient” VLSI systems that has:
Circuit Speed ( high )
Power consumption ( low )
Design Area ( low )
I made this presentation for you , I hope its useful for you all, and I hate Plagiarism please, I also used some slides here but I mentioned all in the last slide :)
Hope you can get benefits from it
Introduction to SOC Verification Fundamentals and System Verilog language coding. Explains concepts on Functional Verification methodologies used in industry like OVM, UVM
Spyglass DFT is comprehensive process of resolving RTL Design issues, thereby ensuring high quality RTL with fewer design bugs.
Improves test quality by diagnosing DFT issues early at RTL or netlist.
Shortens test implementation time and cost by ensuring RTL or netlist is scan-compliant.
A VLSI (Very Large Scale Integration) system integrates millions of “electronic components” in a small area (few mm2 few cm2).
design “efficient” VLSI systems that has:
Circuit Speed ( high )
Power consumption ( low )
Design Area ( low )
I made this presentation for you , I hope its useful for you all, and I hate Plagiarism please, I also used some slides here but I mentioned all in the last slide :)
Hope you can get benefits from it
Introduction to SOC Verification Fundamentals and System Verilog language coding. Explains concepts on Functional Verification methodologies used in industry like OVM, UVM
Presentation on various logic families like RTL, DTL, TTL, IIL etc with diagram, advantages and limitations plus some basic concepts like fan out, noise margin, propagation delay.
Power point presentation on logical families.
A good presentation cover all topics.
For any other type of ppt's or pdf's to be created on demand contact -dhawalm8@gmail.com
mob. no-7023419969
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
1. 29/09/2005 EE6471 (KR) 121
– Digital Logic Voltage and Current Parameters
• Fan-out, Noise Margin, Propagation Delay
– TTL Logic Family
– TTL Logic Family Evolution
– ECL
– CMOS Logic Families and Evolution
– Logic Family Overview
Logic Families/Objectives
2. 29/09/2005 EE6471 (KR) 122
– SSI <12 gates/chip
– MSI 12..99 gates/chip
– LSI ..1000 gates/chip
– VLSI …10k gates/chip
– ULSI …100k gates/chip
– GSI …1Meg gates/chip
Level of integration ever
increasing, because of
•cost
•speed
•size
•power
•reliability
Limits of integration:
•packaging
•power dissipation
•inductive and capacitive
components
•flexibility
•critical quantity
Logic Families/Level of Integration
Note: Ratio gate count/transistor count
is roughly 1/10
3. 29/09/2005 EE6471 (KR) 123
Logic Families/Level of Integration
– Remember: Gordon Moore, 1975. Predictions:
• Mosfet device dimensions scale down by a factor of 2 every 3 years
• #transistors/chip double every 1-2 years.
Source: G. Sery, Intel
4. 29/09/2005 EE6471 (KR) 124
Vcc Vcc
Ioh Iih
Voh Vih
Vcc
Iol Iil
Vol Vil
Parameter Comment
Voh(min) High-Level Output Voltage. The minimum voltage level at a logic
circuit output in the logical 1 state under defined load conditions.
Vol(max) Low-Level Output Voltage. The maximum voltage level at a logic
circuit output in the logical 0 state under defined load conditions.
Logic Families/Static VI Parameters
5. 29/09/2005 EE6471 (KR) 125
Vcc Vcc
Ioh Iih
Voh Vih
Vcc
Iol Iil
Vol Vil
Parameter Comment
Vih(min) High-Level Input Voltage. The minimum voltage level required for
a logical 1 at an input. Any voltage below this level may not be
recognized as a logical 1 by the logic circuit.
Vil(max) Low-Level Input Voltage. The maximum voltage level required for
a logical 0 at an input. Any voltage above this level may not be
recognized as a logical 0 by the logic circuit.
Logic Families/Static VI Parameters
6. 29/09/2005 EE6471 (KR) 126
Vcc Vcc
Ioh Iih
Voh Vih
Vcc
Iol Iil
Vol Vil
Parameter Comment
Ioh High-Level Output Current. Current flowing into an output in the
logical 1 state under specified load conditions.
Iol Low-Level Output Current. Current flowing into an output in the
logical 0 state under specified load conditions.
Logic Families/Static VI Parameters
7. 29/09/2005 EE6471 (KR) 127
Vcc Vcc
Ioh Iih
Voh Vih
Vcc
Iol Iil
Vol Vil
Parameter Comment
Iih High-Level Input Current. Current flowing into an input when a
specified high-level voltage is applied to that input.
Iil Low-Level Input Current. Current flowing into an input when a
specified low-level voltage is applied to that input.
Logic Families/Static VI Parameters
8. 29/09/2005 EE6471 (KR) 128
– Fan-out: The maximum number of
logic inputs that an output can drive
reliably.
Beware:
Modern mixed-technology digital systems often employ logic from different logic families. In
this case Fan-out is meaningless, unless the operating condition is specified exactly.
Unless otherwise specified, fan-out is always assumed to refer to load devices of the same
family as the driving output.
Logic Families/Fan-Out
9. 29/09/2005 EE6471 (KR) 129
Vih(min)Voh(min)Vnh −=
:marginnoisestateHigh
Vol(max)Vil(max)Vnl −=
:marginnoisestateLow
Noise margin required for reliable operation
of digital systems in the presence of noise,
crosscoupling, and ground-bounce.
l)min(Vnh,VnVn =
:marginNoise
Sometimes quoted: Percentage noise
margin… bears little practical value.
Output Input
Indetermined
Range
Abnormal
Operation
Voh(min)
Vih(min)
Vil(max)
Vol(max)
Vcc Vcc
Vnh
Vnl
Logic 1 Logic 1
Logic 0 Logic 0
Logic Families/Noise (Voltage) Margin
10. 29/09/2005 EE6471 (KR) 130
avgavg Pdisstp ⋅
:ProductPowerSpeedGate(Vague) comparison between logic families:
(e.g. for 74HC00: 25ns*100µW=2.5pJ)
Parameter Comment
tphl Input-to-output propagation delay time for output going from high
to low.
tplh Input-to-output propagation delay time for output going from low
to high.
vi
vo
t
t
tphl tplh
Input
Output
50%
vi
vo
50%
Logic Families/Propagation Delay
11. 29/09/2005 EE6471 (KR) 131
A
B
Inputs
Output
Q1
Q2
Q3
Q4
D1
R1
4k
R2
1.6k
R4
130
R3
1k
A
B
Inputs
Output
Vcc
5V
Standard TTL Logic:
•Bipolar Transistor-Transistor Logic
•Introduced in 1964 (Texas Instruments)
•Tremendous influence on the characteristics
of all logic devices today
•Standard TTL shaped digital technology
•Standard TTL Logic (e.g. 7400) practically
obsolete (i.e. replaced by more advanced
logic families, e.g. 74ALS00)
•A large variety of logic functions available
•Single- or multi-emitter input transistor Q1
(up to eight emitters)
•Totem-pole output arrangement (Q3, Q4)
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Logic Families/TTL Logic
12. 29/09/2005 EE6471 (KR) 140
Q1
Q2
Q3
Q4
D1
R1
4k
R2
1.6k
R4
130
R3
1k
A
B
Y
Vcc
Q1
Q2
Q3
Q4
D1
R1
4k
R2
1.6k
R4
130
R3
1k
A
B
Y
Vcc
BJT (Bipolar Junction Transistor) storage time
reduction by using a BC Schottky diode.
Schottky diode has a Vfw=0.25V. When BC
junction becomes forward biased Schottky diode
will bypass base current.
Logic Families/TTL/Logic Evolution
13. 29/09/2005 EE6471 (KR) 141
74 Series
Bipolar. Saturated BJTs. Practically
obsolete. Don't use in new designs!
74S Series
Bipolar. Deep saturation prevented by
BC Schottky Diode. Reduced storage-
time delay. Practically obsolete.
74LS Series
Bipolar. Lower-power slower-speed
version of the 74S Series.
74AS Series
Innovations in IC design and
fabrication. Improvement in speed and
power dissipation. Relatively popular.
Fastest TTL available.
74ALS Series
Innovations in IC design and
fabrication. Improvement in speed and
power dissipation. Popular.
74F Series
Innovations in IC design and
fabrication. Popular.
Logic Families/TTL/Logic Evolution
14. 29/09/2005 EE6471 (KR) 142
Advantages of ECL
•fastest logic family available
TTL
•BJTs operating in saturated mode
•Limited switching speed (storage time)
Disadvantages of ECL
•negative supply (awkward)
•high static power dissipation
•limited choice of manufacturers and devices
•low noise margin
ECL (Emitter-Coupled Logic)
•BJTs operating in unsaturated mode (i.e.
emitter-follower mode)
•Principle: Current switching (ECL is also
sometimes called Current-Mode-Logic CML)Vee
-5.2V
Vss
A
Logic Families/ECL
15. 29/09/2005 EE6471 (KR) 145
MOS Logic:
MOS: Metal-Oxide-Semiconductor (Metal-
Oxide-Silicon
Advantages of MOS
•inexpensive and simple to fabricate
•high speed
•low static power consumption
•scaling of mosfets: higher integration possible
•rail-to-rail outputs
MOS Logic Categories:
•NMOS (obsolete)
•PMOS (obsolete)
•CMOS: complementary MOS
Disadvantages of MOS
•susceptibility to electro-static damage, ESD
•susceptibility to latch-up
Because of their advantages CMOS devices
have become dominant in the IC market
First CMOS logic family CD4000 introduced in
1968.
Logic Families/CMOS
16. 29/09/2005 EE6471 (KR) 146
CMOS Gate Characteristics:
•No resistive elements (resistors elements
require large chip areas in bipolar ICs)
•Extremely low static power consumption
(Roff > 1010Ω)
•Extremely low static input currents
•Cross-conduction and charge/discharge of
internal capacitances lead to dynamic power
dissipation
•Output Y swings rail-to-rail (low Ron)
•Supply voltage can be reduced to 1V and
below
DO NOT leave CMOS inputs floating !
Unused CMOS inputs must be tied to a fixed voltage level (or to another input).
A
B
Y
Logic Families/CMOS
17. 29/09/2005 EE6471 (KR) 147
CMOS Logic Trend:
Reduction of dynamic losses (cross-conduction,
capacitive charge/discharge cycles) by decreasing
supply voltages
(12V→5V → 3.3V → 2.5V → 1.8V → 1.5V…).
Reduction of IC power dissipation is the key to:
•lower cost (packaging)
•higher integration
•improved reliability
4000 Series
CMOS. Wide supplyvoltage range.
High noisemargin. Low speed. Weak
output drive. Practically obsolete.
74C Series
CMOS. Pin-compatible with TTL
devices. Low speed. Obsolete.
Replaced by HC/HCT family.
74HC/HCT Series
CMOS. Drastic increase in speed.
Higher output drive capability. HCT
input voltage levels compatible with
TTL.
74AC/ACT Series
CMOS. Functionally compatible, but
not pin-compatible to TTL. Improved
noise immunity and speed. ACT inputs
are TTL compatible.
74AHC/AHCT Series
CMOS. Improved speed, lower power,
lower drive capability.
BiCMOS Logic
CMOS/Bipolar. Combine the best
features of CMOS and bipolar. Low
power high speed. Bus interfacing
applications (74BCT, 74ABT)
74LVC/ALVC/LV/AVC
CMOS. Reduced supply voltage.
LVC: 5V/3.3V translation
ALVC: Fast 3.3V only
AVC: Optimised for 2.5V, down to 1.2V
Logic Families/CMOS/Logic Evolution
18. 29/09/2005 EE6471 (KR) 148
Care is needed when driving inputs of one logic family by outputs of a different family !
Watch voltage levels and fan-out !
Logic
Family
Prop.
Delay
Rise/Fall
Time
Vihmin Vilmax Vohmin Volmax Noise
Margin
74 22ns 2.0V 0.8V 2.4V 0.4V 0.4V
74LS 15ns 2.0V 0.8V 2.7V 0.5V 0.3V
74F 5ns 2.3ns 2.0V 0.8V 2.7V 0.5V 0.3V
74AS 4.5ns 1.5ns 2.0V 0.8V 2.7V 0.5V 0.3V
74ALS 11ns 2.3ns 2.0V 0.8V 2.5V 0.5V 0.3V
ECL 1.45ns 0.35ns -1.165V -1.475V -1.025V -1.610V 0.135V
4000 250ns 90ns 3.5V 1.5V 4.95V 0.05V 1.45V
74C 90ns 3.5V 1.5V 4.5V 0.5V 1V
74HC 18ns 3.6ns 3.5V 1.0V 4.9V 0.1V 0.9V
74HCT 23ns 3.9ns 2.0V 0.8V 4.9V 0.1V 0.7V
74AC 9ns 1.5ns 3.5V 1.5V 4.9V 0.1V 1.4V
74ACT 9ns 1.5ns 2.0V 0.8V 4.9V 0.1V 0.7V
74AHC 3.7ns 3.85V 1.65V 4.4V 0.44V 0.55V
(Typical values for rough comparison only. Refer to datasheet. Values valid for Vcc=5V)
Logic Families/Overview
19. Welcome to the World of TI Logic
1.8 V Logic
LVC
ALVC
2.5 V Logic
LV LVC
ALVC
LV
AC
ALB
LVC
LVT
AHC
ALVC
3.3 V Logic
CBT
AHC
AHCT
HC/HCT
AC/ACT
BCT
F
ALS
AS
TTL LS
S
ABT
LV
5+ V Logic
CD4000 FCT
Harris now TI
ETL
BTL
GTL
HSTL
SSTL
Specialty
1.5 V Logic 1.2 V Logic
Cypress now TI
TVC
AVC
AUC
AUC
AVC
ALVT
ALVT
AVC
CBTLV
AUC
0.8 V Logic
AUC
GTLP
SSTV
LV-A CBTLV
AUC
VME
AUP AUP
AUP
AUP
AUP
AUP
LV-A
LV-A
11––55
AVC AVC
20. TI remains committed to be the last supplier in the older families.
Bipolar
CMOS
BiCMOS
Introduction Growth Maturity Decline Obsolescence
ALVC
LV
HC/HCT
AS
ALS
F
S
TTL
BCT
LS
CD4000
LVT-A
ABT
AC/ACT
FCT
AHC/AHCT
ALVT
LVC
CBT
CBTLV
AVC
GTLP
Little Logic
SSTV
AUC
TVC
VME
CB3T/Q
SSTU
AUP
Product Life Cycle
CBT-C
11––66
21. ABTABT
HC/HCTHC/HCT
LVTLVT
64
24
12
8
5 10 15 20
Speed - max tpd (ns)
BCTBCT
IOLDrive(mA)
AC/ACTAC/ACT
AHC/AHCTAHC/AHCT
ALVTALVT
5 V
3.3 V
2.5 V
1.8 V
100
GTLPGTLP
FCTFCT
LVLV
AUPAUP
LVCLVCALVCALVC
AUCAUC
AVCAVC
Optimized Vcc
ABT Advanced BiCMOS Technology
AC/T Advanced CMOS
AHC/T Advanced High Speed CMOS
ALVC Advanced Low Voltage CMOS
ALVT Advanced Low Voltage BiCMOS
AUC Advanced Ultra Low Voltage CMOS
AUP Advanced Ultra Low Power CMOS
AVC Advanced Very Low Voltage CMOS
BCT BiCMOS Technology
FCT Fast CMOS Technology
GTLP Gunning Transceiver Logic Plus
HC/T High Speed CMOS
LV Low Voltage HCMOS
LVC Low Voltage CMOS
LVT Low Voltage BiCMOS Technology
Family Performance Positioning
11––1010
22. CMOS Voltage Roadmap
Optimized
Voltage
Data Sheet
Limits
Functional
Voltage
Tolerance
CD4K HCT
AHCT
ACT
AHC AC LV-A LVC ALVC AVC AUP AUC
5
4
3
2
1
Voltage
6
15
18
HC
11––1111
23. CMOS Voltage vs. Speed
Comparison of 16245 functions with 500 ohm/30pF load. (AUC not yet tested)
0
5
10
15
20
25
0 1 2 3 4 5 6
VCC (V)
HC
AHC
LV-A
AC
LVC
ALVC
AVC
AUC
TypicalPropagationDelayTime(ns)
11––1212
24. 5-V TTL
Standard TTL: ABT,
AHCT, HCT, ACT, Bipolar
1.5
0 GND
2.4
2.0
0.4 VOL
0.8
5 V VCC
VOH
VIH
Vt
VIL
VOH
GND
VIH
5-V CMOS
Rail-to-Rail 5 V
HC, AHC, AC, LV-A
4.44
3.5
2.5
1.5
0.5
0
5 V VCC
Vt
VIL
VOL
3.3-V LVTTL
LVT, LVC, ALVC
AUP, LV-A, ALVT
1.5
0 GND
2.4
0.4
3.3 V
0.8
2.0
VCC
VOH
VIH
Vt
VIL
VOL
VIH
VOH
2.5-V CMOS
AUC, AUP, AVC,
ALVC, LVC, ALVT
2.3
1.7
1.2
0.7
0.2
0
2.5 V VCC
GND
Vt
VIL
VOL
1.8 V VCC
VIH
VOH1.2
1.17
0.9
0.7
0.45
0 GND
Vt
VIL
VOL
1.8-V CMOS
AUC, AUP, AVC,
ALVC, LVC
IsIs VOH higher than VIH?
D RD R
5TTL 5CMOS 3LVTTL 2.5CMOS 1.85TTL 5CMOS 3LVTTL 2.5CMOS 1.8CMOSCMOS
5TTL Yes No Yes * Yes5TTL Yes No Yes * Yes** Yes*Yes*
5 CMOS Yes Yes Yes* Yes*5 CMOS Yes Yes Yes* Yes* Yes*Yes*
3 LVTTL Yes No Yes Yes3 LVTTL Yes No Yes Yes** Yes*Yes*
2.5 CMOS Yes No Yes Yes2.5 CMOS Yes No Yes Yes Yes*Yes*
1.8 CMOS No1.8 CMOS No NoNo No No YesNo No Yes
* Requires V* Requires VIH ToleranceTolerance
DD
RR
IsIs VOL less than VIL?
IC Basics
Comparison of Switching Standards
11––1616
25. Open-Drain Outputs 05/06/07 Functions
Functions Available
VCC2
Required Input level
depends on VCC1
RPULLUP
T1
VCC1
Output level
depends on VCC2
Also Possible
Wired-Function Technique
Phantom links on output side
can reduce component count.
07
07
RPULLUP
Vcc
05 -
06 -
07 -
S, LS, ALS, AC, HC,
AHC, LV, LVC
TTL, LS, LV, LVC,
LVC1G/3G, AUC1G
TTL, LS, LV, LVC,
LVC1G/3G, AUC1G
NOTE: Over voltage tolerance is
required to support UP translation.
Mixed-Voltage Interfacing
11––2323
26. • ICs are at the core of a modern digital system
• Many systems fit entirely on a single IC (SOC)
– a single (15-mm)2 chip can hold several million gates
(1997)
– a simple 32-bit CPU can be realised in an area of 1mm2
• Biggest limitation of a modern digital IC: Large
reduction in signal count between on-chip wires and
package pins. Typical IC
– 104 wiring tracks on each of four metal layers
– 103 signals can leave the chip (for cheaper packages: 40..200)
– Chips are often “pad-limited”. Peripheral-bonded chips. Chip area increases
as the square of the number of pads
IC Packaging/Intro
27. • Most ICs are bonded to small IC packages
Although it is possible to attach chips directly to boards. Method used
extensively in low-cost consumer electronics. Placing chips in packages
enables independent testing of packaged parts, and eases requirements on
board pitch and P&P (pick-and-place) equipment.
• IC Packages
– inexpensive plastic packages: <200 pins
– packages with >1000 pins available
(e.g. Xilinx FF1704: 1704-ball flip-chip BGA)
• IC Packaging Materials
– Plastic, ceramic, laminates (fiberglass, epoxy resin), metal
IC Packaging/Intro
28. • IC package categories:
– PTH (pin-through-hole)
Pins are inserted into through-holes in the circuit
board and soldered in place from the opposite side of
the board
» Sockets available
» Manual P&P possible
– SMT (surface-mount-technology)
SMT packages have leads that are soldered directly to
corresponding exposed metal lands on the surface of
the circuit board
» Elimination of holes
» Ease of manufacturing (high-speed P&P)
» Components on both sides of the PCB
» Smaller dimensions
» Improved package parasitic components
» Increased circuit-board wiring density
SMT packages offer many benefits and are generally preferred.
IC Packaging/Categories
29. • IC packaging material: Plastic
– die-bonding and wire-bonding
the chip to a metal lead frame
– encapsulation in injection-molded plastic
– inexpensive but high thermal resistance
– Warning: Plastic molds are hygroscopic
» Absorb moisture
Storage in low-humidity environment. Observation of factory floor-life
» Stored moisture can vapourise during rapid heating
can lead to hydrostatic pressure during reflow process. Consequences
can be: Delamination within the package, and package cracking. Early
device failure.
IC Packaging/Materials
30. • IC packaging materials: Ceramic
» consists of several layers of conductors separated by
layers of ceramic (Al2O3 “Alumina”)
» chip placed in a cavity and bonded to the conductors
Note: no lead-frame
» metal lid soldered on to the package
» sealed against the environment
» ground layers and direct bypass capacitors possible
within a ceramic package
» high permittivity of alumina (εr=10)
Note: High permittivity leads to higher propagation delay!
» expensive
IC Packaging/Materials
31. Plastic Dual-In-Line
(PDIP)
here: PDIP14
Small Outline
Integrated Circuit
(SOIC)
here: SO14
SC70
here: SC70-5
Plastic Lead Chip Carrier (PLCC)
here: PLCC28
Thin Shrink Small Outline
(TSSOP)
here: TSSOP14
Thin Quad Flat Package
(TQFP)
here: TQFP32
IC Packaging/Popular IC Packages
32. Small Outline Integrated Circuit
(SOIC)
•Shown: SO14, but available from SO8..SO28
•Gull-wing leads
•Popular, cost effective, and widely available IC
package for low-pin-count ICs
•Dimensions: 8.6mm x 3.9mm x 1.75mm
•Pin-to-pin: 1.27mm (50mil)
IC Packaging/Popular IC Packages
33. Thin Shrink Small Outline (TSSOP)
•Shown: TSSOP14, but available up to TSSOP64
•Popular, cost effective, and widely available IC
package for low-profile applications
•Dimensions: 5.0mm x 4.4mm x 1.2mm
•Pin-to-pin: 0.65mm (25mil)
IC Packaging/Popular IC Packages
34. Ball Grid Arrays (BGA)
•Shown: BGA54
•Available pin count >1700
•Advanced IC package for high-density
low-profile applications
•Chip-scale package (CSP)
•Dimensions: 8.0mm x 5.5mm x 1.4mm
•Pin-to-pin: 0.8mm
•Low lead inductance
Challenges:
•Integrity of solder joints
•Solder joint inspection (X-ray)
•Availability of 2nd source
•Routing
Altera Ultra-Fine-Line
BGA
•Pin-Count: 169
•Dimensions 11mm x 11mm
•Profile: 1.2mm
IC Packaging/Popular IC Packages
35. die
bond wire
land
package trace
via and ball
metal substrate
Physical construction of a BGA
•Shown: Type-II BGA (cavity-down design)
•Interconnect: multi-layer laminated construction
•Die bonded onto a metal heat slug
•Solder balls make connection to a PC board
•50µm bond wires
•Copper conductor thickness 20µm
•Layer separation 150µm
IC Packaging/BGA Physical Construction