This paper proposes a novel design for a high-speed six-transistor full adder using a two-transistor XOR gate to reduce power dissipation and area. Previous full adder designs used more transistors, resulting in higher power consumption and area. The proposed design uses a two-transistor XOR gate as a building block for an eight-transistor full adder. Simulation results show the new design has lower power consumption and transistor count compared to previous designs.

1. ISSN: 2277 – 9043
International Journal of Advanced Research in Computer Science and Electronics Engineering
Volume 1, Issue 5, July 2012
Design of High Speed Six Transistor Full Adder
using a Novel Two Transistor XOR Gates
1
Pakkiraiah Chakali, 2Adilakshmi Siliveru, 3Neelima Koppala
Abstract—In modern era, the number of transistors are To reduce the power and area requirements of the
reduced in the circuit and ultra low power design have computational complexities, the size of transistors are
emerged as an active research topic due to its various shrunk into the deep sub-micron region and
applications. A full adder is one of the essential component predominantly handled by process engineering. Many
in digital circuit design, many improvements have been made design architecture and techniques have been developed
to reduce the architecture of a full adder.The main aim of this to reduce power dissipation complementary logic,
paper is to reduce the power dissipation and area by redusing Pseudo NMOS[10], Dynamic CMOS[3], Clocked CMOS
the number of transistors.By using general logic of pmos logic (C2MOS), CMOS Domino logic[1], Cascade
transistor, the two transistor xor gate can be voltage switch logic (CVSL), Modified Domino logic,
implemented. In this paper proposes the novel design of Pass Transistor Logic (PTL)[3] have been proposed.
a 2T XOR gate. The design has been compared with Among the various building blocks in digital designs
earlier proposed 3T, 4T and 6T XOR gates and a one of the most complex and power consuming is the
significant improvement in silicon area and power-delay Adders. Although several Adder designs[14] have been
product has been obtained. An 8-T full adder has been proposed to reduce power consumption[12], they are not
designed using the proposed 2-T XOR gate and its suitable for operation in the sub-threshold region. In
performance has been obtained. the design is simulated addition these designs require a large number of
in Mentor graphics tool . transistors, resulting in a large area, not suitable for
small, low-priced systems. The power consumption of a
Keywords — XOR gate, full adder, speed, area, power CMOS circuit can be decomposed into two basic
dissipation. classes: static and dynamic.
I. INTRODUCTION The steady state power dissipation[12] of a circuit is
expressed by the following relation
Moore’s[17] law explains the requirement of the
transistors for VLSI design it gives the empirical P =I V
observation that transistor density and performance of stat stat DD --------------(1)
integrated circuits, doubles every year, which was then
revised to doubling every two years[18]. Unfortunately, The dynamic[3] component of power dissipation is
such performance improvements have been due to its transient switching behavior of the CMOS
accompanied by an increase in power[2] and energy device
dissipation of the systems. Higher power and energy 2
dissipation in high performance systems require more P = αCV f ……………..(2)
expensive packaging and cooling technologies, increase dyn DD
cost, and decrease system reliability. Nonetheless, the
level of on-chip integration and clock frequency will This paper is organized as following. Section II
continue to grow with increasing performance demands, reviews previous work and implementation of 2T XOR
and the power and energy dissipation[13] of high- gate. Section III introduces implementation of full
performance systems will be a critical design constraint. adder. Simulation and results are shown in Section IV,
followed by the conclusion in Section V.
Pakkiraiah Chakali, ECE Department, Sree Vidyanikethan
Egineering College (Autonomou), JNTUA, Anantapur.( II. DESIGN OF A TWO - TRANSISTOR XOR GATE
Pakkiraiah1988@yahoo.co.in). Tirupati, INDIA,
Adilakshmi Siliveru, ECE Department, Sree Vidyanikethan
Egineering College (Autonomou), JNTUA, The circuit performance improvement in through
Anantapur.(adilakshmi458@gmail.com). Tirupati, INDIA, transistor count minimization.XOR gates form the
Neelima Koppala, ECE Department, Sree Vidyanikethan fundamental building block of full adders. The early
Egineering College (Autonomou), JNTUA, Anantapur.Tirupati, designs of XOR gates were based on either four
INDIA, Mobile No.09966547895(koppalaneelima@gmail.com).
transistors[4] or three transistors[5] that are
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2. ISSN: 2277 – 9043
International Journal of Advanced Research in Computer Science and Electronics Engineering
Volume 1, Issue 5, July 2012
conventionally used in most designs over the last
decade.The previous designs of the four transistors and
three transistors are shown in figure1.The proposed two
transistor XOR gates can be designed using general
logic implementation. The design[15] of a two transistor
XOR gate is shown in figure 2.
The circuite operation is as follows when A=0 and
B=0 both the pmos transistors are ON and it will
produce the output is low.when either one of the
transistor is ON it Produces output as high, when A=1
and B=1 both the pmos transistors are OFF and it will
produce the output is low.
Fig.2: Proposed Design of 2T -XOR.
III. DESIGN OF THE SIX-TRANSISTOR FULL
ADDER
The new design of full adders[7][11] which forms the
Fig.1(a) Fig.1(b) basic building blocks of all digital VLSI circuits has
been undergoing a considerable improvement, being
motivated by three basic design goals, viz. minimizing
the transistor count, minimizing the power consumption
and increasing the speed.
Conventional Static[3] CMOS full adder: The
conventional CMOS logic gate full adder[16] is shown as
Fig. 2 while the equation of a full adder are present as
equation(1) - (4) [7].
Fig.1(c) Fig.1(d)
x + y + Cin =2Cout + Sum -------------------(3)
Cout =(y(x ⊕ y)) + (Cin(x ⊕ y)) -----------(4)
Sum = x ⊕ y ⊕ Cin -----------------------(5)
The static CMOS Full adder is implemented by using
26 transistors.we can also minimize the number of
Fig.1(e) transistors by using the CMOS Transmission gate and
CMOS inverter.With this logic we reduce the number of
Fig.1: Previous designs of 4-T and 3-T XOR gates. transistors to 20.By using Pass transistor logic we can
minimize the static power dissipation and number of
transistors.Full adder is design with 14 transistors[9] by
using Pass transistor logic.which leads the moderate
power dissipation.The full adder design also
implemented by using 10 transistors[6].
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3. ISSN: 2277 – 9043
International Journal of Advanced Research in Computer Science and Electronics Engineering
Volume 1, Issue 5, July 2012
Fig.3: Previous designs of 8T Full adder.
Fig.5: Wave forms of 2T-XOR gate.
[8]
Mainly the XOR and XNOR circuits are used in
designing of full adder. In previous design the Full
adder is designed by using eight transistors.which can
dissipates more power compare to this work.In this
paper the design of full adder using two transistors xor
gates can ge implemented.The Six transistor Full adder
is shown in Figure.4.
Fig.6: Wave form of 6T-Full adder
The comparison of the different XOR gates and Full
adders are shown in table.1 according to their transistor
count and power dissipation.
Table.1: Comparison of existed full adders with
proposed one in terms of transistor count and power
dissipation
Fig.4: Proposed Design of 6T – Full adder
Strucures No Power
Transistors (μw)
IV. RESULTS AND DISCUSSION XOR (Fig.1(a)) 4 0.499
The exclusive-or gate and full adder are operated at XOR(Fig.1(b)) 4 0.486
100 MHz signal frequency. In fact, in addition to normal XOR(Fig.1(c)) 4 0.140
transistors, circuits are tested in corner cases with fast XOR (Fig.1(d)) 4 0.434
and slow transistors and their combinations too. The XOR (Fig.1(e)) 3 0.435
difference in these stages is in consumption of power XOR (Fig.2) 2 0.135
and falling and rising times which are caused due to the FULLADDER(Fig.3) 8 0.361
difference in NMOS and PMOS transistors power FULLADDER(Fig.4) 6 0.235
consumption and speed. After the simulation, the layout
of circuit is drawn. By the post simulation result along
with a few corrections have achieved in sizes that the V. CONCLUSION
circuit has an accurate operation. Simulation results are
performed by using digital schematic design tool of In this paper different CMOS logic design families
Mentor graphics tool. The waveforms of proposed has been reviewed and evaluated based on the
design as shown in figure 5 and 6 for XOR gate and full performance metrics like area, power, delay and
adder. transistor count. But the previous techniques have the
disadvantages of transistor count, delay and power
dissipation. The current work proposes the design of an
6T full adder, which is by far the full adder with the
lowest transistor count. In designing the proposed 6T
full adder, a novel 2T XOR gate has also been proposed.
The implementation of Full Adder has been presented
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International Journal of Advanced Research in Computer Science and Electronics Engineering
Volume 1, Issue 5, July 2012
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Integr. (VLSI) Syst., vol. 10, no. 1, Feb. 2002, pp. 0– B.Tech in Electronics and Communication
29. Engineering from Sreenivasa Institute of
Technology and mamagement studies,
[8] K.-H. Cheng and C.-S. Huang, “The novel efficient Chittoor, Andhra Pradesh, India in 2009. he is
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(M.Tech) in VLSI at Sree Vidyanikethan
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Engineering College , Tirupati, Andhra
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Pradesh, India. His interest includes Digital
Design, ASIC Design, VLSI Testing.
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with full voltage swing nodes,” in Proc. IEEE
Ms. Adilakshmi Siliveru completed her
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B.Tech in Electronics and Communication
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Engineering from Kandula Obula Reddy
Memorial College Of Engineering, Kadapa,
[10] R. Zimmermann and W. Fichtner, “Low-power Andhra Pradesh, India in 2011. She is now
logic styles: CMOS versus pass-transistor logic,” pursuing her Master of Technology (M.Tech)
IEEE J. Solid-State Circuits, vol. 32, July 1997, in VLSI at Sree Vidyanikethan Engineering
pp.1079–90. College , Tirupati, Andhra Pradesh, India. Her
interest includes Digital Design, VLSI
Testing.
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5. ISSN: 2277 – 9043
International Journal of Advanced Research in Computer Science and Electronics Engineering
Volume 1, Issue 5, July 2012
Ms. Neelima Koppala, M.Tech., is currently
working as an Assistant Professor in ECE
department of Sree Vidyanikethan
Engineering College, Tirupati. She has
completed M.Tech in VLSI Design, from
Satyabhama University. Her research areas are
RFIC Design, Digital Design, Low Power
VLSI Design and VLSI Signal Processing.
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