Advance Microcontroller Bus Architecture(AMBA).
this is a advance bus architecture. it is defined by ARM.
all the content is taken from http://infocenter.arm.com/ website.
2. Introduction to AMBA
• It is an on chip communication standard for designing high
performance embedded microcontroller.
• There are three different busses in AMBA(2.0)
• AHB (Advanced High-performance Bus)
• ASB (Advanced System Bus)
• APB (Advanced Peripheral Bus)
4. Typical AMBA based microcontroller
High bandwidth
external
memory
interface
High- performance
ARM processor
DMA bus
master
High bandwidth
on-chip RAM
B
R
I
D
G
E
UART Timer
Keypad PIO
AHB or ASB
APB
AHB to APB bridge
or
ASP to APB bridge
5. Features of AMBA
• It allows multiple masters use the address and data bus via some
arbitration.
• Arbitration is the interface between master and AMBA system
bus, it means according to the address it gives the access to
master to transfer data at given address.
• Only one master can access the bus at any given time.
• Allows decoding of addresses issued by multiple masters
• Allows peripheral device to connect to the system bus via bridge.
6. AHB (Advanced High-performance Bus)
• It is high performance system bus that supports multiple bus
masters and provides high bandwidth operation.
• Basic features
1. High performance
2. Pipelined operation
3. Multiple bus masters
4. Burst transfer
5. Split transection
8. Architecture of AHB
• There are Three sub busses
• HADDR (it is the address bus of the system)
• HWDATA (it is the write data bus of system, during the write operation
data transfer take place between master and slave.)
• HRDATA (it is the read data bus of system, during the read operation data
transfer take place between slave and master.)
• AHB bus contains of
• AHB Master
• AHB Slave
• AHB Arbiter
• AHB Decoder
9. Continue……
• AHB Master
• It is able to initiate read & write operation by providing an
address and control information.
• Only single master is allowed to transfer data at one time.
• AHB Slave
• According to generated address & control signal appropriate
slave will read or write according to control signal.
• AHB Arbiter
• The main function of arbiter is what operation should execute
and selection of master and slave for that operation.
10. Continue……
• AHB Decoder
• Here there is separated bus for read (slave to master comm.)
operation so for selection of master or destination of data
Decoder is used.
• Basically first slave send address to select appropriate master
and after that it will sends data to it.
11. Control Signals of AHB
HCLK It is a clock signal of AHB bus system. Every operation is executed at rising edge of clock pulse.
HRESETn It is a active low reset signal. It is used to reset the bus and system.
HADDR[31:0] It is 32 bit address bus. It use to select the AHB slave of system.
HTRANS[1:0]
These are a status signals. It is used to indicate the type of transfer.
[1. NON-SEQUENTIAL 2. SEQUENTIAL 3.IDLE 4.BUSY]
HWRITE
It is a control signal which is used to select the operation of read/write
High: Write operation (master to slave)
Low: Read operation (slave to master)
HSIZE[2:0] It indicates the size of data transferring (8/16/32 bit). The maximum size of data is 1024 bit.
HBURST[2.0] It indicates data is transmitting bit by bit or in burst(4/8/16 bit).
HPROT[3:0]
It is the protection control signal. which is used provide additional information about a bus access
and are primarily intended for use by any module that wishes to implement some level of
protection.
12. Control Signals of AHB
HWDATA[31:0] It is 32 bit wide unidirectional data bus. It is used to transfer data between master to slave.
HSELx In AHB system there are multiple AHB slave. To select an AHB slave this control signal is used.
HRDATA[31:0] It is 32 bit wide unidirectional data bus. It is used to transfer data between slave to master.
HREADY
High : data transfer is finished
Low : data transfer is not finished
HRSEP[1:0]
It is a status signal. Which indicates the transfer response.
[1.OKAY 2.ERROR 3.RETRY 4.SPLIT]
13. Interfacing Diagram of AHB
HSELx
HADDR[31:0]
HWRITE
HTRANS[1:0]
HSIZE[2:0]
HBURST[2:0]
HRESETn
HWDATA[31:0]
HCLK
HMASTER[3:0]
HMASTLOCK
HREADY
HRSEP[1:0]
HSPLITx[15:0]
HRDATA[31:0]
AHB
SLAVE
SPLIT
CAPABLE
SLAVE
ADDRESS
AND CONTROL
SELECT
RESET
CLOCK
DATA
TRANSFER
RESPONSE
DATA
15. ASB (Advanced System Bus)
• It is the first generation of AMBA system bus.
• In this bus system it contain one or more bus masters.
• Features of ASB
• Burst transfer
• Pipelined transfer operation
• Multiple bus master
16. Control Signals of ASB
AGNTx
It is a signal from bus arbiter to bus master x. It indicates that the bus master will be granted
when BWAIT is low.
AREQx
It is signal from bus master x to bus arbiter. It indicates that the bus master requests to the bus
arbiter for bus. All master have its own AREQ.
BA[31:0] It is a 32 bit wide address bus. It is used to select the address of ASB slave.
BCLK it is bus clock of the system. All operation or data transfer perform at HIGH or LOW level of clock.
BD[31:0]
It is 32 bit wide bi-directional data bus, which is used to transfers data from bus master to bus
slave and vice-versa.
BERROR
It is a status signal, which indicates the transfer error.
HIGH: transfer error has occurred.
LOW: transfer error has not occurred.
BnRES It is active low reset signal, which is used to reset the ASB system and bus.
BSIZE[1:0]
It is control signal, which is used to select the transfer size of bus.
The transfer size will be 8/16/32 bit.
17. Control Signals of ASB
BPROT[1:0]
It is the protection control signal. which is used provide additional information about a bus access
and are primarily intended for use by a bus decoder when acting as a basic protection unit.
BTRAN[1:0]
It is the control signal. Which is used to select the transfer type.
[1.ADDRESS ONLY 2.NON-SEQUENTIAL 3. SEQUENTIAL]
BWAIT
It is the signal driven by the selected bus slave to indicate if the current transfer may complete.
HIGH: further bus cycle is required.
LOW: the transfer may complete in current bus cycle.
BWRITE
HIGH: write transfer (master to slave)
LOW: read transfer (slave to master)
DSELx
It is a signal from the bus decoder to bus slave x, which indicates that the slave device is selected
and data transfer is required.
18. Typical AMBA ASB based microcontroller
High bandwidth
external
memory
interface
High- performance
ARM processor
DMA bus
master
High bandwidth
on-chip RAM
B
R
I
D
G
E
UART Timer
Keypad PIO
ASB
APB
ASP to APB bridge
20. APB (Advanced Peripheral Bus)
• The AMBA APB bus is used to interface low bandwidth
peripheral to AHB or ASB which does not require high
performance pipeline interface.
• APB is connected with AHB or ASB with bridge. Which is used to
convert suitable format for slave device on the APB.
• The bridge provides latching of all address, data and control
signals as well as providing a second level of decoding to
generate slave select signals for the APB peripherals.
21. Control Signals of APB
PCLK It is the bus clock of APB system. Every transfer occurred at rising edge of clock.
PRESETn It is active low reset signal. It is used to reset the APB system and APB bus.
PADDR[31:0] It is 32 bit wide address bus which is used to select the APB slave address.
PSELx
This signal indicates that the slave device is selected and data transfer is require. There is a PSELx
signal for each bus slave.
PENABLE
It is a strobe signal. This signal is used to start data transfer. It occurs after rising clock when PSELx
is genrated.
PWRITE
High: APB write access (AHB or ASB master to APB slave)
Low: APB read access (APB slave to AHB or ASB master)
PRDTA
It is 32 bit wide unidirectional read data bus. Which is used to transfer data between APB slave to
AHB or ASB master.
PWDATA
It is 32 bit wide unidirectional write data bus. Which is used to transfer data between AHB or ASB
master to APB slave.
22. APB Specification
• APB specification is described under the following headings:
• State diagram
• Write transfer
• Read transfer
23. State Diagram
• The state diagram is used to represent the activity
of the APB bus.
• There are three operation state 1.IDLE 2.SETUP
3.ENABLE
• IDLE: in this state PSELx and PENABLE are low.
Which means that the AHB or ASB master does not
select any slave for communication and master
does not require any data transfer.
• SETUP: In this state PSELx is high and PENABLE is
low. Which means that master is selecting
appropriate APB slave for communication. But data
transfer can’t take place because the PENABLE is
low.
• ENABLE: In this state both PENABLE and PSELx
both are high. Which means APB slave is selected
and data transfer take place.
24. WRITE TRANSFER
• The right transfer starts with the
address, write data, write signal and
select signal.
• All changing after the rising edge of the
clock.
• The first clock cycle of transfer is called
the SETUP cycle.
• After the following clock edge the
enable signal is occurred and this
indicates that the ENABLE cycle is taking
place.
• All other signals are valid till the
ENABLE cycle. After ENABLE cycle the
communication is stopped.
• To reduce power consumption the
address and write signal will not change
until next access occurs.
25. READ TRANSFER
• The timing of the address,
write, select and strobe signals
are same as write transfer.
• In case of read the slave must
provide the data during
ENABLE cycle.
• The data is transferring at
rising edge of clock when
ENABLE signal is occurred.
27. APB Bridge Description
• The bridge unit converts system bus transfers into APB transfers
perform following function:
• It latches the address and holds it valid throughout transfers.
• It decodes the address and generates a peripheral select
(PSELx). only one select signal can be active during transfer.
• It drives the data onto the APB for a write transfer.
• It drives the APB data onto the system bus for a read transfer.
• It generates the timing strobe, PENABLE, for the transfer.
