USART BLOCK DIAGRAM,ARCHITECTURE

1. USART 8251 ARCHITECTURE
B.SARAVANA MANIKANDAN
Assistant Professor
KONGUNADU COLLEGE OF ENGINEERING AND TECHNOLOGY,
TRICHY

2. BLOCK DIAGRAM 8251-USART

3. Features of USART
• It is an universal synchronous and asynchronous communication
controller.
• It supports standard asynchronous protocol wit
a. 5 to 8 bit character format
b. odd, even or no parity generation and detection
c. Automatic break detect and handling
• It is built in baud rate generator
• It allows full duplex transmission
• It provides error detection logic, when detects parity, overrun and
framing errors.
• It has 28 pins.

4. • The read/write control logic determines the functions of the chip
according to the control word in its register and monitors the data
flow.
• The data bus buffer transfers the control word/status information
between the chip and CPU.
• The Transmitter section converts the parallel words received from the
CPU to serial bits and data transmits over the TXD line to
peripherals.
• Te receiver section receives the serial bits from the peripherals
converts them in to parallel word and transfers to the CPU.
• The Modem control section extends the data communication through
any modem through telephone lines.

5. DATA BUS BUFFER:
• This is Tri State Bi-directional 8 bit buffer used to interface 8251 A to
the system data bus.
• Data bus is transmitted or received by the buffer using IN or OUT
instructions of the CPU.
• Control words, Command words and status information are also
transferred through the data bus buffer.
Transmitter Section:
• The transmitter buffer accepts parallel data from the data bus buffer
and converts into a serial bit stream, inserts appropriate characters
or bits and outputs a composite serial stream of Data
• On the TxD pin output on the falling edge of TxC.
• The transmitter will begin transmission if CTS=0 there are three
output signals and one input signal associated with transmitter
section.

6. TxC Transmitter clock:
• The transmitter clock controls the rate at which data bits are
transmitted by 8251A
• In synchronous transmission mode TxC is equal to a baud rate.
• In Asynchronous transmission mode TxC can be 1,16,64 times of
baud rate.
TxRDY:
• This is an output signal which is high 8251 is ready to accept byte.
• It can also be used to interrupt the CPU or to indicate the status.
• It is automatically reset when data byte is loaded to the buffer.
TXE:
• This is an output signal.A high value of TxEmpty indicates the output
register is empty
• It is reset when a byte is transferred from the buffer to the output
register.

7. RECIVER SECTION:
• The receiver accepts serial data through RxD line from a peripheral,
converts the serial bits into parallel data.
• A low signal of RxD indicates the start bit. the feature is only active in
the asynchronous mode.
• This section also has false start bit detection ,parity error detection,
framing error detection and break detection circuits.
• In asynchronous mode this section has two input signals and one
output signals.
Receiver Ready:
• When this output signal goes high the 8251 contains a character is
ready to be input to the CPU.
• The CPU checks the condition of RxDRDY using a status read
operation.

8. RxC:
• This receiver clock controls rate at which bits are received by 8251.
• In synchronous mode RxC is equal to baud rate.
• In the asynchronous mode RxC can be set to 1,16 or 64 timer of
baud rate
BD-Break Dtect:
• This output will go high whenever the receiver remains low through
two consecutive stop bit sequence.
• Break detect may also be read as a status bit.
• It is reset only when master chip reset or receiver data sets to high
state.

9. MODEM CONTROL:
• DSR (Data Set Ready)- A low signal on the pin is used to test
MODEM conditions such as Data set ready
• DTR-A low signal on the pin is used for MODEM control such as
Data Terminal Ready.
• RTS- The pin is asserted low to begin the transmission
• CTS - A low signal on the pin enables the 8251 to transmit the serial
data if the TxC bit in the command byte is set to 1