The document describes the design and implementation of a CAN bus controller to enable reliable communication between nodes using the CAN protocol. It discusses the motivation for using CAN in embedded systems and provides details on the controller's architecture, which includes modules for CAN, APB interface, and interrupts. It also covers the controller's design flow from learning CAN and APB specifications to simulation, synthesis, and layout. The controller was synthesized at 100MHz with low area and power.
In general, to carry out life people living in rural livelihood as farmers. Farming is already ingrained and carried down-temurun.Pertanian have become everyday activities, especially for people who live near these communities pegunungan.Perekonomian largely dependent on agriculture. Sometimes farmers do not always yield a good crop, due to crop failure
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By addressing this we made a prototype device that utilizes Commucations Global System for Mobile (GSM) standard which is one of the wireless communication system (wireless) which is open. In this case been the subject of green house.
it can be concluded that the freehand tool is expected to be used to control lights as a substitute for the lack of sunlight in the process of photosynthesis, so the quantity and quality of crop production in the greenhouse can be increased as optimally as possible. In this case, we limit only on the micro climate and temperature indicator light only. This was chosen because it is considered the second most easy to be controlled and matched to the system Green House.
Programming the ARM CORTEX M3 based STM32F100RBT6 Value Line Discovery BoardGaurav Verma
This programming manual is providing the complete details of programming the STM32 Value-line discovery (a low-cost) evaluation board for Value-line of STM32 microcontrollers from STMicroelectronics.
In general, to carry out life people living in rural livelihood as farmers. Farming is already ingrained and carried down-temurun.Pertanian have become everyday activities, especially for people who live near these communities pegunungan.Perekonomian largely dependent on agriculture. Sometimes farmers do not always yield a good crop, due to crop failure
Plants that have failed to bear fruit one being a contributing factor is something is distorted or there is something wrong during the process of planting. One is a plant that is less than optimal in the sunlight, then the process of photosynthesis is not running optimally. This results in the photosynthesis that produces carbohydrates. As a result, accumulation of carbohydrates to be not optimal so that interest is formed into little or even none at all (quoted in Argoteknologi.Web.id)
By addressing this we made a prototype device that utilizes Commucations Global System for Mobile (GSM) standard which is one of the wireless communication system (wireless) which is open. In this case been the subject of green house.
it can be concluded that the freehand tool is expected to be used to control lights as a substitute for the lack of sunlight in the process of photosynthesis, so the quantity and quality of crop production in the greenhouse can be increased as optimally as possible. In this case, we limit only on the micro climate and temperature indicator light only. This was chosen because it is considered the second most easy to be controlled and matched to the system Green House.
Programming the ARM CORTEX M3 based STM32F100RBT6 Value Line Discovery BoardGaurav Verma
This programming manual is providing the complete details of programming the STM32 Value-line discovery (a low-cost) evaluation board for Value-line of STM32 microcontrollers from STMicroelectronics.
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This presentation course covers full architectural and internal details of one of the most famous processor ARM Cortex M3 and M4. Processor core, NVIC, Register set, Bus interfaces, AHB,APB,SYS BUS,Interrupts,memory fully explained.
Synthesis & FPGA Implementation of UART IP Soft Coreijsrd.com
this paper presents synthesis and hardware implementation of fully functional Universal Asynchronous Receiver Transmitter Intellectual Property core using XILINX SPARTAN-3 XC3S400 series FPGA. The UART soft core module consists of a transmitter along with baud rate generator and a receiver module with false start bit detection features. This has been implemented using VERILOG hardware description language and synthesized using XILINX ISE development tools. All behavioral simulation of UART module performed using MODELSIM simulator. After successful FPGA implementation transmitter and receiver module was tested by connecting FPGA board with Hyper Terminal software via RS232 interface at a data speed of 9.6 kbps.
This Book helps the bargainer to getting started with avr studio and avr Micro controller interfacing. This book covers Navigating the AVR studio and many more avr interfacing examples
Join this video course on Udemy. Click the below link
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This presentation course covers full architectural and internal details of one of the most famous processor ARM Cortex M3 and M4. Processor core, NVIC, Register set, Bus interfaces, AHB,APB,SYS BUS,Interrupts,memory fully explained.
Synthesis & FPGA Implementation of UART IP Soft Coreijsrd.com
this paper presents synthesis and hardware implementation of fully functional Universal Asynchronous Receiver Transmitter Intellectual Property core using XILINX SPARTAN-3 XC3S400 series FPGA. The UART soft core module consists of a transmitter along with baud rate generator and a receiver module with false start bit detection features. This has been implemented using VERILOG hardware description language and synthesized using XILINX ISE development tools. All behavioral simulation of UART module performed using MODELSIM simulator. After successful FPGA implementation transmitter and receiver module was tested by connecting FPGA board with Hyper Terminal software via RS232 interface at a data speed of 9.6 kbps.
This Book helps the bargainer to getting started with avr studio and avr Micro controller interfacing. This book covers Navigating the AVR studio and many more avr interfacing examples
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Ultra sonic sensor network communicating using NRF 24L01 radioAshok Raj
• Designed mixed signal circuit for ultrasonic sensor network using Arduino shield as programmed processor and NRF24L01 as the radio, PAMAS protocol was used for better efficiency.
• Software used: Arduino
Design And Verification of AMBA APB ProtocolIJERA Editor
Advanced microcontroller bus architecture (AMBA) is a well established open specification for the proper management of functional blocks comprising system-on-chips (SOCs). A Memory Controller is designed to cater to this problem. This design presents an intellectual property (IP) for inter-Advanced peripheral bus (APB) protocol. The Memory Controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or can be integrated into the system chipset. This paper revolves around building an Advanced Microcontroller Bus Architecture (AMBA) compliant Memory Controller as an Advanced High-performance Bus (AHB) slave. The work involved is of APB Protocol and its slave Verification. The whole design is captured using VHDL, simulated with ModelSim and configured to a FPGA target device belonging to the Virtex4 family using Xilinx.
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International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
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Asynchronous Transfer Mode ATM is the cell relay protocol designed by ATM Forum and adopted by the ITU-T. Cell, a small fixed size block of information with asynchronous TDM ensures high speed real time transmission with efficient and cheaper technology. Instead of user addresses, it uses virtual circuit identifier and virtual path identifier, which can be repeated at unrelated locations. This technology ensures connectivity to much more users than normal packet switching networks.
ATM and ISDN-B combination allows high-speed interconnection of world's network.
VLSI DESIGN OF AMBA BASED AHB2APB BRIDGEVLSICS Design
The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for highperformance buses to communicate with low-power devices. In the AMBA Advanced High Performance bus (AHB) a system bus is used to connect a processor, a DSP, and high-performance memory controllers where as the AMBA Advanced Peripheral Bus (APB) is used to connect (Universal Asynchronous Receiver Transmitter) UART. It also contains a Bridge, which connects the AHB and APB buses. Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way. So AHB2APB bridge is designed, implemented using VERILOG tool and tested using Verilog testbench and is reported in this paper. A synthesizable RTL code of a complex interface
bridge between AHB and APB is developed and known as AHB2APB Bridge. The simulated AHB2APB Bridge results are promising and can be further tested for its verstality by writing a verification program using UVM in future.
VLSI DESIGN OF AMBA BASED AHB2APB BRIDGEVLSICS Design
The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for highperformance
buses to communicate with low-power devices. In the AMBA Advanced High Performance bus (AHB) a system bus is used to connect a processor, a DSP, and high-performance memory controllers where as the AMBA Advanced Peripheral Bus (APB) is used to connect (Universal Asynchronous Receiver Transmitter) UART. It also contains a Bridge, which connects the AHB and APB buses. Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way. So AHB2APB bridge is designed, implemented using VERILOG tool and tested using Verilog testbench and is reported in this paper. A synthesizable RTL code of a complex interface
bridge between AHB and APB is developed and known as AHB2APB Bridge. The simulated AHB2APB Bridge results are promising and can be further tested for its verstality by writing a verification program using UVM in future.
3. PROJECT GOALS
Design and Implementation of a CAN BUS
Controller for a reliable and robust
communication between different nodes
Using can bus protocol by BOSCH company
4. BACKGROUND AND MOTIVATION
• The can protocol implements
only layers 2 and 3 from
the 7 layers of the OSI model
for communication between
different nodes of a
communication network
5. BACKGROUND AND MOTIVATION
The Controller Area Network (CAN) is a serial
communication protocol used extensively for high-
speed embedded applications where noise immunity
and robustness is necessary.
• The CAN protocol uses a twisted pair cable to communicate
at speeds up to 1 Mbps (minimum 0.125Mbps).
It is highly fault-tolerant, making it ideal for safety-critical
applications.
• It is used for backbone network as well as the powertrain,
6. BACKGROUND AND MOTIVATION
• Asynchronous communication
• Any node can access the bus when the bus is quiet
• Non-destructive arbitration, 100% use of the
bandwidth without loss of data
• Automatic error detection, signaling and retries
• All nodes can send a message at any time, when
two nodes access the bus together, arbitration
decides who will continue.
• Bit stuffing is used to maintain synchronization.
7. HOW DOES A CAN BUS SYSTEM LOOKS LIKE?
COMMONLY USED IN CAR MOBILE SYSTEMS
9. CAN SPECIFICATION
MESSAGE TRANSFER
• 4 different message-types (“frames”): Data, Remote, Error and Overload.
• Faulty nodes are automatically dropped from the bus, which prevents
any single node from bringing a network down, and ensures that
bandwidth is always available for critical message transmission (“Fault
Confinement”).
CAN
frame
DATA/REMO
TE
9
13. ARCHITECTURE AND DESIGN
Node 1
CPU
CAN CONTROLER
CAN Transiver
CAN_H
CAN_L
Node 2
CPU
CAN CONTROLER
CAN Transiver
Node N
CPU
CAN CONTROLER
CAN Transiver
CAN BUS
15. ARCHITECTURE AND DESIGN
CAN CONTROLLER INTERFACE
• fclk – outer clock. Came from the cpu/mcu
which is connected to the controller.
• APB Interface – A transfer protocol for
communication between the cpu/mcu
and the controller (AMBA APB protocol).
• Interrupt – signal’s that one message
(or more) is received.
• Can Tx – the output signal which sent to the bus
• Can Rx – the input signal which came from the bus
paddr
pwrite
psel
penable
fclk
Rst_n
prdata[31:0]
pready
int
pwdata[31:0]
Can_tx
Can_rx
Canbus
InterruptAPBInterface
CAN Module
16. ARCHITECTURE AND DESIGN
BIT TIMING
The can bus uses asynchronous communication. Therefore, a
way to synchronize between the different nodes which connected
to the bus is needed.
Synchronization:
• Bit stuffing – If 5 consecutive bits with the same logic value
(‘0’ or ‘1’) occur in a row,
a bit with the opposite logic value (‘1’ or ‘0’) is sent.
• Hard synchronization – Every time that a data(or remote)
frame is sent, there is a transition from a sequence of logic
‘1’s to logic ‘0’, which represents ‘start of frame’ and used
17. ARCHITECTURE AND DESIGN
BIT TIMING – DEFINES THE BUS CLOCK
/ /Phase_Seg2 max(PhaseSeg1,InfoProcessingTime) time quanta
1
1 Prop_seg Phase_Seg1+Phase_Seg2
1
1 1 Prop_seg Phase_Seg1+Phase_Seg2
BRP
T
Q f
clk
T T
bus Q
f
clkf
bus BRP
18. ARCHITECTURE AND DESIGN
BIT TIMING
• Nominal bit rate is the number of bits per second transmitted in the
absence of resynchronization by an ideal transmitter.
• SYNC_SEG used to synchronize the various nodes on the bus.
• PROP_SEG used to compensate for the physical delay times within the
network.
• PHASE_SEG1, PHASE_SEG2 used to compensate for edge phase errors.
• Sample point is the point in time at which the bus level is read and
interpreted.
• Time quantum is a the fixed unit of time which can be derived from
the oscillator period.
19. SIMULATION
VERIFICATION TEST BENCH
• The simulation is built as two Can Controller
DUT units such as DUT2 is the stub and verifier
of DUT1.
• The APB stub is a functional unit that works by
the AMBA APB protocol and represents the
cpu/mcu that communicates with the controller.
The test-suit included a test for every internal
block, and final integration test for the whole
scheme of the controller.
20. SIMULATION
VERIFICATION TEST BENCH
• Reset Node1 and Node2
• Configure bit timing registers for both Nodes
• Write data to node1 and node 2 to be
transmitted ‘Data Frame’ simultaneously
on bus
initial begin
fclk=0;
rst_n1 = 0;
rst_n2 = 0;
#200
rst_n1 = 1;
rst_n2 = 1;
bit_time_config1;
bit_time_config2;
#10
apb_write_data_frame1;
apb_write_data_frame2;
#400000 $finish;
end
21. SIMULATION
WAVEFORM DIAGRAM
As can be seen, Node1 and
Node2 tried to send
a Data Frame to the bus.
Node1 has won the
arbitration stage and hence
continued to send his message
while Node2 stopped.
It can be seen that Node2 recieved the data which sent by Node1
and in the end of the frame the interrupt signal rose.
23. SYNTHESIS
RESULTS SUMMARIES
The synthesis run with fclk=100Mhz which is the maximum frequency
of the controller.
synthesis result:
Total 9 cells
• Time
data required time 9.88 ns
data arrival time -9.79 ns
• Area
Total cell area: 95864.5
Total area: 136792.9
• Power
total power 68.0113 mW
0.5𝜇𝑚2
0.5𝜇𝑚2
25. SUMMARY
•Explanation for the need of a good
communication controller.
•Can BOSCH and APB protocol specifications
•Architecture and design of the controller
•Test bench Simulation, Synthesis and Layout
חגי
ide – 1 עבור הרחבה ל 29 ביט identifier
Crc-15 +1 delimeter
18+99+9=126 max length
שחר
שחר
שחר
חגי
חגי
חגי
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חגי
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Data Arrival Time
This is the time required for data to travel through data path.
Data Required Time
This is the time taken for the clock to traverse through clock path.
Setup and hold slack is defined as the difference between data required time and data arrival time.
setup slack= Data Required Time- Data Arrival Time
hold slack= Data Arrival Time- Data Required Time
A +ve setup slack means design is working at the specified frequency and it has some more margin as well.
Zero setup slack specifies design is exactly working at the specified frequency and there is no margin available.