The document summarizes a thesis that defines a communication infrastructure for partially reconfigurable architectures. The proposed infrastructure uses a network-based approach with network nodes tailored for partial reconfiguration. It aims to provide a flexible, reliable and adaptable communication schema. The thesis outlines related works on communication infrastructures for FPGAs, presents the proposed layered network approach and implementation, experimental results comparing it to previous works, and conclusions.

1. A Flexible Tile-Based Communication Infrastructure for Partial Reconfigurable Architectures BY Simone Corbetta [email_address] Thesis committee: Shantanu Dutt (chair), Donatella Sciuto, Ashfaq Ahmad Khokhar UIC Thesis Defense: May, 8th 2008

2. Aims [A1] Define a communication infrastructure for partially reconfigurable architectures [A2] Design the communication protocol [A3] Design network nodes [A4] Implementation

3. Rationale and Innovation Problem statement Dynamic capabilities of modern devices demands for flexibility, reliability and adaptability Adaptability to dynamic context changes Innovative contributions Network-based communication infrastructure tailored for partial reconfigurable architectures Device-independent Resource-aware design Reliable communication Adaptable communication schema

4. Outline Introduction Related works Proposed approach & implementation Experimental results Conclusions and future works

5. What’s next Introduction A bird’s eye-view on communication infrastructures Related works Proposed approach & implementation Experimental results Conclusions and future works

6. Communication-centric design Increasing complexity in modern Systems-on-Chips Increasing applications scenarios Communication requirements increase Communication-centric design [1,2] Static versus dynamic environment Executing applications are not known a priori Communication requirements cannot be specified prior to system execution “ Classical” widely-used communication approaches lack of flexibility and scalability Need to define a flexible, adaptable solution [1] “ Communication Centric SoC Design for Nanoscale Domain ”. Ogras, U. Y.; Jingcao, Hu; Marculescu, R. 16th IEEE International Conference on Application-Specific Systems, Architecture and Processors. July 2005. pp.73-78. [2] “ On-Chip Networks: a Scalable, Communication-Centric Embedded System Design Paradigm ”. Henkel, J.; Wolf, W.; Chakradhar, S. Proceedings of the 17th International Conference on VLSI Design, 2004. pp.845.851.

7. Communication infrastructure and dynamic features Dynamic reconfiguration can be used to effectively realize communication infrastructures that are Flexible Reliable Adaptable (at run-time) to communication requirements Dynamic reconfiguration as a specific feature of the communication infrastructure layer design

8. Point-to-point links Directly connect communicating modules (a) ad-hoc connection (b) regular topology (complete graph) Scalability is affected, due to high resource requirements; reusability is low, interfaces are application-dependent Simplicity; ensures high performance, and low latency; no overhead Drawbacks Advantages

9. Bus-based systems Single, centralized and shared communication architecture An arbiter grants access to the shared resource ... Arbiter (a) single bus ... ... Bridge (b) multiple buses Bottleneck; level of contention increases, concurrent accesses are serialized; single point-of-failure Simplicity; reusability, commercial standards Drawbacks Advantages

10. Crossbar switch MxN matrix of programmable components Line 1 Line 2 Programmable interconnect point Resource requirements, in terms of programmable components True parallellism, physically different concurrent communication links can be established Drawbacks Advantages

11. Network-on-Chip Borrow main ideas from data-network (LANs, WANs) Based on distributed communication nodes ( switches ) [3,4] [3] “ Networks-on-Chip: a New SoC Paradigm ”. De Micheli, G.; Benini, L. Computer. 2002, Volume 35. pp.70-78. [4] “ Networks-on-Chip: a New Paradigm for System-on-Chip Design ”. Nurmi, J. Proceedings of the International Symposium on System-on-Chip, Nov. 2005. pp.2-6. Computational overhead; high resource requirements Flexibility; scalability; reusability; reliability, no single point-of-failure Drawbacks Advantages

12. What’s next Introduction FPGAs and dynamic reconfiguration Brief overview of devices and dynamic features Related works Proposed approach & implementation Experimental results Conclusions and future works

13. Field Programmable Gate Arrays Programmable logic devices (Re)programmable logic blocks and interconnects Configuration is stored within the configuration memory architecture Image taken from “ Bebop to the Boolean Boogie: an Unconventional Guide to Electronics Fundamentals, Components and Processes ” by Clive Maxfield [Everyday Practical Electronics]

14. Reconfiguration and Reconfigurability Reconfiguration is the process of alteration of the system configuration/behavior Reconfigurability is the ability to support reconfiguration Which is the granularity of the reconfiguration process Total versus partial reconfiguration Who is the responsible of the reconfiguration task Internal versus external reconfiguration When the reconfiguration is performed Dynamic versus static reconfiguration

15. What’s next Introduction FPGAs and dynamic reconfiguration Related works XPipes DyNoC CoNoChi Proposed approach & implementation Experimental results Conclusions and future works

16. XPipes (1/2) Designed for multi-processors systems [5] Ad-hoc network topology defined at synthesis-time XPipesCompiler Based on a layered approach: Smart Stack protocol [5] Bertozzi, D.; Benini, L. “ XPipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip ”. Circuits and Systems Magazine , IEEE, 2004, 4, pp.18-31. DATA-LINK LAYER NETWORK LAYER TRANSPORT LAYER physical link

17. XPipes (2/2) Advantages Layered stacked protocol allows for independent optimization of different aspects Drawbacks Topology is fixed at synthesis-time No flexibility Routing path is defined once for all at synthesis-time No reliability Resource requirements (See experimental results)

18. DyNoC (1/2) Static NoC for heterogeneous systems [6] Static 2D-mesh interconnection topology Static routing mechanism (modified XY-Algorithm ) [6] Bobda, C.; Ahmadinia, A.; Majer, M.; Teich, J.; Fekete, S.; Van der Veen, J. “ DyNoC: A Dynamic Infrastructure for Communicationin Dynamically Reconfigurable Devices ”. International Conference on Field Programmable Logic and Applications , August 2005, pp.151-158. DyNoC Rule

19. DyNoC (2/2) Advantages 2D-mesh topology guarantess high connectivity DyNoC Rule Drawbacks Static topology guarantees no flexibility High overhead One network node for each “slot” in the architecture

20. CoNoChi (1/2) Reconfigurable packet-switched communication architecture [7] [7] Pionteck, T.; Koch, R.; Albrecth, C. “ Applying Partial Reconfiguration to Networks-on-Chips ”. International Conference on Field Programmable Logic and Applications , August 2006, pp.1-6.

21. CoNoChi (2/2) Advantages Network nodes can be added at run-time Flexibilty Drawbacks No multiple communication sessions are supported No clear distinction between communication and computational layer Hard to manage system complexity Resource requirements

22. Qualitative Comparison No clear distinction Computation and communication Supported Not supported Not supported Dynamic Reconfiguration Flexibility thanks to dynamic reconfiguration No flexibility No flexibility Flexibility Relies on run-time choices Static mesh Relies upon synthesis-time choices Connectivity CoNoChi DyNoC XPipes

23. What’s next Introduction FPGAs and dynamic reconfiguration Related works Proposed approach & implementation Main features and implementation Experimental results Conclusions and future works

24. A light-weight approach “ Light-weight ” w.r.t. Communication protocol , to reduce computational overhead Resource requirements , to keep reconfiguration complexity low Network nodes design , to reduce overhead and latency Routing mechanism , to reduce latency To master system complexity a layered approach has been used COMPUTATIONAL LAYER COMMUNICATION LAYER VS

25. Overview

26. Packet-switched communication Packet-switching instead of circuit-switching [8] General packet structure [8] Dally, W.; Towles, B. “Route packets, not wires: on-chip interconnection networks” . In proceedings of the Design and Automation Conference in Europe, 2001, pp.684-689. Contains communication-related information (route update, communication tail, replies…) Control Contains data of the current communication request Data Contains preliminary information on the current communication session, useful for the recipient Header

27. Session-oriented communication Communication based on the concept of session A precise sequence of packets Communication based on the minimal information required Header Data Tile For each Master-Slave couple multiple concurrent sessions are supported

28. A layered protocol

29. Routing mechanisms (1/2) Who chooses the routing path? INITIATOR-BASED : the initiator chooses the entire path to reach the destination end-point DESTINATION-BASED : information is kept within the routing tables, local decisions initiator-based destination-based VS Switch-related overhead is greater, due to routing table read process Update of the information is complex; overhead increases CONS PROS Flexibilty and transparency on the communication details Switch design has low complexity; switch-related overhead is low Destination-based Initiator-based

30. Routing mechanisms (2/2) An hybrid approach takes advantage from both mechanisms ESEE SEE/ E/// EE// ////

31. What’s next Introduction FPGAs and dynamic reconfiguration Related works Proposed approach & implementation Implementation Experimental results Conclusions and future works

32. Target architecture Target architecture Static side Reconfigurable side Static Reconfigurable FPGA Bus-macro TILE columns rows

33. Switch design

34. Master NI Design

35. Slave NI Design

36. What’s next Introduction FPGAs and dynamic reconfiguration Related works Proposed approach & implementation Experimental results Case studies Conclusions and future works

37. Experimental Results Purpose is to demonstrate the validity of the proposed approach Resource requirements Switch design Master and Slave NI Virtex-II Pro Case Study Comparison with XPipes Virtex-4 Case Study

38. Switch Resource Requirements Switch design is effectively light-weight

39. Switch Performance

40. Master NI Resource Requirements Depends on number of concurrent sessions, packet size Linear relation XC3S200 XC2VP7 XC4VFX12 27-bits packet 32-bits packet

41. Slave NI Resource Requirements Depends expecially on concurrent sessions allowed Linear 27-bits packets case

42. Virtex-II Pro Case Study (1/3)

43. Virtex-II Pro Case Study (2/3)

44. Virtex-II Pro Case Study (3/3) XPipes versus proposed solution Resource requirements 618/1215 = 50.8% 846/1520 = 55.5% Half clock cycles required Latency IMPROVEMENT ! Resource-aware design High performance

45. Virtex-4 Case Study (1/2)

46. Virtex-4 Case Study (2/2)

47. What’s next Introduction FPGAs and dynamic reconfiguration Related works Proposed approach & implementation Experimental results Conclusions and future works

48. Concluding Remarks (1/2) A suitable communication infrastructure has been designed and implemented Communication protocol and Network Interface designs Layered approach Tile-based implementation and tile dimensioning Device independent design Switch-design; communication protocol complexity Resource-aware design Dynamic routing; dynamic topology Reliability Dynamic switch insertion; dynamic switch deletion; dynamic topology; dynamic routing mechanism; support of dynamic reconfiguration Flexibility and adaptability

49. Concluding Remarks (2/2) Work under development for ACM TRETS Transaction (Transactions on Reconfigurable Technology and Systems) Future works Define and realize a tool to automatically generate application-specific network Implement the Network and Reconfiguration Monitor Analysis and study of the power characterization of the proposed approach “ A Light-Weight Network-on-Chip Architecture for Dynamically Reconfigurable Systems ”. Corbetta, S.; Rana, V.; Santambrogio. M. D. Proceedings of the 8th edition of the International Symposium on Systems, Architectures, Modeling and Simulation (IEEE Conference Session), July 2008.

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51. Questions Thanks for your attention. Any questions?